KR20180031898A - Display device having common voltage line - Google Patents

Abstract

The present invention provides a display device including a common voltage wire capable of minimizing a ripple of common voltage. The display device comprises: a plurality of pixels formed on a substrate; a common voltage wire supplying the common voltage to the plurality of pixels, and including first to third common voltage wires arranged on different layers and electrically connected to the substrate; and a contact electrode electrically connecting the first to third common voltage wires.

Description

DISPLAY DEVICE HAVING COMMON VOLTAGE LINE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device including a common voltage wiring.

The display device includes a plurality of gate lines, a plurality of data lines, a plurality of gate lines, and a plurality of pixels connected to the plurality of data lines. The display device includes a gate driving circuit for providing gate signals to a plurality of gate lines and a data driving circuit for outputting data signals to a plurality of data lines. Each of the plurality of pixels includes a switching transistor and a liquid crystal capacitor. One end of the liquid crystal capacitor is connected to one end of the switching transistor and the other end is connected to the common voltage wiring.

Such a display device can display an image by applying a gate-on voltage to a predetermined gate line by a gate driving circuit and then supplying a data voltage corresponding to the video signal to the data lines by a data driving circuit.

The common voltage wiring is arranged in a bezel area where an image of the display panel is not displayed. If the width of the common voltage wiring is reduced in order to reduce the width of the bezel region, the wiring resistance may increase.

It is therefore an object of the present invention to provide a display device including a common voltage wiring capable of minimizing ripple of a common voltage.

According to an aspect of the present invention, there is provided a display device comprising: a plurality of pixels formed on a substrate; a plurality of pixels arranged in different layers on the substrate, A common voltage wiring including first to third common voltage wiring lines electrically connected to each other, and a contact electrode for electrically connecting the first to third common voltage wiring lines to each other.

In this embodiment, each of the plurality of pixels includes a transistor formed on the substrate, and a liquid crystal capacitor including a pixel electrode and a common electrode electrically connected to the transistor.

In this embodiment, the contact electrode includes the same material as the pixel electrode, and is provided in the same process.

In this embodiment, the transistor includes a gate electrode formed on the substrate, an insulating layer stacked over the entire substrate on which the gate electrode is formed, a semiconductor layer formed on the insulating layer, a source electrode formed on the semiconductor layer, Drain electrodes, and a first protective layer stacked over the entire substrate on which the source electrode and the drain electrode are formed.

In this embodiment, the first common voltage wiring is located at the same level as the gate electrode.

In this embodiment, the third common voltage wiring is formed on the first protection layer, and further includes a second protection layer formed on the third common voltage wiring.

In this embodiment, the contact electrode is formed on the second protective layer.

The first common voltage wiring may further include a first contact hole penetrating the second protection layer, the first protection layer, and the insulating layer formed on the first common voltage wiring, And is in direct contact with the contact electrode through the first contact hole.

In this embodiment, the second common voltage wiring is located at the same level as the source electrode and the drain electrode.

The second common voltage wiring may further include a second contact hole penetrating the second protection layer and the first protection layer formed on the second common voltage wiring, The contact electrode is in direct contact with the contact electrode.

In this embodiment, the third common voltage wiring may further include a third contact hole passing through the second protection layer formed on the third common voltage wiring, wherein the third common voltage wiring is directly connected to the contact electrode through the third contact hole Contact.

In this embodiment, the substrate includes a display region and a non-display region surrounding the display region, and the common voltage wiring is arranged in the non-display region.

In this embodiment, the contact electrode electrically connects the first common voltage wiring and the third common voltage wiring, and electrically connects the second common voltage wiring and the third common voltage wiring.

The display device having such a configuration can reduce the resistance of the common voltage wiring by including the first common voltage wiring and the second common voltage wiring as well as the third common voltage wiring corresponding to the gate electrode and the source electrode of the display area . In addition, the first to third common voltage wirings may be electrically connected to each other by a contact electrode formed in the same layer as the pixel electrode of the display region.

As the resistance of the common voltage wiring decreases, the ripple of the common voltage can be minimized, so that degradation of the image displayed on the display panel can be prevented.

1 is a plan view of a display device according to an embodiment of the present invention.
2 is a circuit diagram illustrating a display device according to an embodiment of the present invention.
3 is a plan view showing a portion of the common voltage wiring and the pixel region of the display substrate shown in FIG.
4 is a cross-sectional view taken along the cutting lines II 'and II-II' shown in FIG. 3;
5 is an enlarged plan view of the region A shown in Fig.
6 is a cross-sectional view taken along the cutting line III-III 'shown in FIG.
7 is an enlarged plan view of the region B shown in Fig.
8 is a cross-sectional view taken along line IV-IV 'shown in FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a display device according to an embodiment of the present invention. 2 is a circuit diagram illustrating a display device according to an embodiment of the present invention.

1 and 2, a display device 100 according to an exemplary embodiment of the present invention includes a display substrate DP, a main circuit substrate 120, a data driving circuit 130, a gate driving circuit 150, A voltage generator 121 and a drive controller 122.

The display substrate DP is not particularly limited and may be, for example, a liquid crystal display panel, an organic light emitting display panel, an electrophoretic display panel, An electrowetting display panel, and the like. In this embodiment, the display substrate DP is described as a liquid crystal display panel. Meanwhile, the liquid crystal display device including the liquid crystal display panel may further include a polarizer, a backlight unit, and the like not shown. The display substrate DP according to the present embodiment may be a VA (Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an IPS (in-plane switching) mode or an FFS (fringe- ) Mode, and the like.

The display substrate DP includes a first substrate 200, a second substrate 300 spaced apart from the first substrate 200, a liquid crystal layer LCL (not shown) disposed between the first substrate 200 and the second substrate 300, , Shown in Figure 4). The display substrate DP includes a display area DA in which a plurality of pixels PX are arranged and a non-display area NDA surrounding the display area DA.

The display substrate DP includes a plurality of data lines DL1 to DLm that intersect the plurality of gate lines GL1 to GLn and the gate lines GL1 to GLn. The plurality of gate lines GL1 to GLn are connected to the gate driving circuit 150. [ The plurality of data lines DL1 to DLm are connected to the data driving circuit 130. In FIG. 2, only a part of a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm are shown.

In FIG. 2, only one pixel PX connected to the gate line GL1 and the data line DL1 among the plurality of pixels PX is shown. The plurality of pixels PX are connected to corresponding gate lines of the plurality of gate lines GL1 to GLn and corresponding data lines of the plurality of data lines DL1 to DLm, respectively.

The plurality of pixels PX may be divided into a plurality of groups according to a color to be displayed. The plurality of pixels PX may display one of the primary colors. The primary colors may include red, green, blue and white. However, the present invention is not limited thereto, and the main color may further include various colors such as yellow, cyan, and magenta.

The gate driving circuit 150 and the data driving circuit 130 receive a control signal from the driving controller 122. The common voltage generator 121 and the drive controller 122 may be mounted on the main circuit board MCB. The drive controller 122 receives image data and control signals from an external graphic controller (not shown). The control signal may include a vertical synchronizing signal, a horizontal synchronizing signal, and a data enable signal and a clock signal that are only at a high level during a period in which data is output in order to display an area where data is input.

The gate driving circuit 150 generates gate signals based on the control signal GCS received from the driving controller 122 via the flexible circuit board 141 and the signal line GSL, Lt; RTI ID = 0.0 > GL1-GLn. ≪ / RTI > The gate signals may be sequentially output. The gate drive circuit 150 includes gate drive chips 151 to 154. [ The gate drive chips 151 to 154 may be mounted on the non-display area NDA of the display substrate DP in a chip on glass (COG) manner. In another example, the gate drive circuit 150 may be formed simultaneously with the pixels PX in the display area DA through the thin film process. For example, the gate driving circuit 150 may be mounted in an unshown area NDA with an oxide semiconductor TFT gate driver circuit (OSG).

FIGS. 1 and 2 illustratively show a plurality of gate lines GL1 to GLn connected to one gate driving circuit 150. FIG. In another embodiment of the present invention, the display device may include two gate drive circuits. One of the two gate driving circuits may be connected to the left ends of the plurality of gate lines GL1 to GLn and the other may be connected to the right ends of the plurality of gate lines GL1 to GLn. Further, one of the two gate drive circuits may be connected to the odd gate lines and the other to the even gate lines.

 The data driving circuit 130 generates gradation voltages according to the image data RGB provided from the driving controller 122 based on the control signal DSC received from the driving controller 122. [ The data driving circuit 130 outputs the gradation voltages to the plurality of data lines DL1 to DLm as data voltages.

 The data voltages may include positive data voltages having a positive value for the common voltage VCOM and / or negative data voltages having a negative value. Some of the data voltages applied to the data lines DL1 to DLm during a certain horizontal interval may have a positive polarity and others may have a negative polarity. The polarity of the data voltages may be reversed every frame to prevent deterioration of the liquid crystal.

 The data driving circuit 130 may include flexible circuit boards 141 to 144 for mounting the data driving chips 131 to 134 and the data driving chips 131 to 134, respectively. The data driving circuit 130 may include a plurality of data driving chips 131 to 134 and a plurality of flexible circuit boards 141 to 144. The flexible circuit boards 141 to 144 electrically connect the main circuit board MCB and the display substrate 110. [ The plurality of data driving chips 131 to 134 provide data signals to corresponding ones of the plurality of data lines DL1 to DLm.

FIG. 1 exemplarily shows a data carrier circuit 130 of a tape carrier package (TCP: Tape Carrier Package) type. In another embodiment of the present invention, the data driving circuit 130 may be disposed on the non-display area NDA of the display substrate 110 by a chip on glass (COG) method.

Each of the plurality of pixels PX includes a thin film transistor T and a liquid crystal capacitor CLC. The pixel PX may further include a storage capacitor. The thin film transistor T includes a first electrode connected to the corresponding data line DLi, a second electrode connected to the pixel electrode of the liquid crystal capacitor CLC, and a gate electrode connected to the corresponding gate line GLj, i? m, j? n). The liquid crystal capacitor CLC includes a pixel electrode connected to the second electrode of the thin film transistor T and a common electrode connected to the common voltage line LVCOM. The arrangement of the liquid crystal directors included in the liquid crystal layer (not shown) between the pixel electrode and the common electrode is changed according to the amount of charge charged in the liquid crystal capacitor CLC. The light incident on the liquid crystal layer is transmitted or blocked depending on the arrangement of the liquid crystal directors, thereby displaying an image.

The common voltage generator 121 outputs the common voltage VCOM through the common voltage wiring LVCOM and the feedback common voltage VCOM_F through the feedback wiring LVCOM_F. The common voltage generator 121 can change the voltage level of the common voltage VCOM according to the voltage level of the feedback common voltage VCOM_F.

3 is a plan view showing a portion of the common voltage wiring and the pixel region of the display substrate shown in FIG. 4 is a cross-sectional view taken along the cutting lines I-I 'and II-II' shown in FIG. 3;

In FIG. 3, a pixel PX connected to the third gate line GL3 and the first data line DL1 is shown for convenience of explanation. Each of the plurality of pixels PX has substantially the same structure.

1, 3 and 4, the display substrate DP includes a first substrate 200, a second substrate 300 facing the first substrate 200, a second substrate 300 facing the first substrate 200, And a liquid crystal layer (LCL) disposed between the substrates 300.

The first substrate 200 is a thin film transistor array substrate on which thin film transistors T for driving liquid crystal molecules of the liquid crystal layer LCL are formed and includes a first insulating substrate 210 made of transparent glass or plastic. The first insulating substrate 210 may be a rigid type substrate, or may be a flexible type. The rigid type substrate may include a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystalline glass substrate. The substrate of the flexible type may include a film substrate including a polymer organic substance and a plastic substrate.

N gate lines GL1 to GLn and m data lines DL1 to DLm may be provided on the first insulating substrate 210. [ A first metal layer is formed on the first insulating substrate 210 and the first metal layer is patterned to form a first gate electrode GE and gate lines GL1 and GL2 in the display region DA. The first metal film may be formed of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver or silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum Based metal, chromium (Cr), tantalum (Ta), and titanium (Ti). Although not shown in the drawing, the first metal film may have a multi-film structure including two conductive films (not shown) having different physical properties.

The gate lines GL2 and GL3 may be electrically insulated by the data lines DL1 and DL2 and the gate insulating layer 220. [ The gate insulating layer 220 may be made of silicon nitride (SiNx) or silicon oxide (SiOx). A semiconductor layer AL made of hydrogenated amorphous silicon, polysilicon, or oxide semiconductor is formed on the gate insulating layer 220. The semiconductor layer AL is located above the gate electrode GE. The semiconductor layer AL may include a semiconductor layer and an ohmic contact layer. In this case, a semiconductor layer is disposed on the gate insulating layer 220, and an ohmic contact layer is disposed on the semiconductor layer.

A second metal layer is formed on the gate insulating layer 220 and the semiconductor layer AL and the source electrode SE and the drain electrode DE and the data lines DL1 and DL2 are formed by patterning the second metal layer. The second metal layer may be made of a refractory metal such as molybdenum, chromium, tantalum, and titanium or an alloy thereof. The drain electrode DE is spaced apart from the source electrode SE by a predetermined distance above the gate electrode GE. Thus, the thin film transistor T is completed.

The thin film transistor T and the data lines DL1 and DL2 are covered by the first passivation layer 230. [ The first passivation layer 230 may be formed of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). The first passivation layer 230 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx). In another embodiment, the upper and lower layers may include silicon nitride (SiNx) and silicon oxide ). ≪ / RTI > In another embodiment, an organic insulating layer made of an acrylic resin may be formed on the first passivation layer 230.

A first transparent conductive layer is formed on the first protective layer 230. The first transparent conductive layer may be formed of a transparent conductive material such as indium tin oxide (Indium Tin Oxide). The first transparent conductive layer is patterned to form a common electrode CE on the first passivation layer 230. The common electrode CE is covered by the second passivation layer 240. The second passivation layer 240 may be made of an inorganic insulating material such as silicon nitride or silicon oxide

A second transparent conductive layer is formed on the second protective layer 240. The second transparent conductive layer may be made of a transparent conductive material such as indium tin oxide. An electrode pattern (not shown) is formed on the second passivation layer 240 by patterning the second transparent conductive layer. Through the patterning process, an opening for exposing the second passivation layer 240 is formed on the electrode pattern. The pixel electrode PE can be formed by patterning the electrode pattern.

The common electrode CE is provided on the upper or lower portion of the pixel electrode PE and may be formed to have a size corresponding to the pixel region defined by the gate lines GL2 and GL3 and the data lines DL1 and DL2 have. 4, the common electrode CE is provided on the first passivation layer 230 and is covered by the second passivation layer 240. As shown in FIG. The pixel electrode PE is provided on the second passivation layer 240. As described above, the common electrode CE is provided below the pixel electrode PE and faces the pixel electrode PE with the second protective layer 240 therebetween.

The common electrodes CE included in the same pixel row may be integrally formed or may be electrically connected to each other to form one common electrode row. The common electrode row may be electrically connected to the common voltage line LVCOM on one side of the insulating substrate 210 to receive the common voltage VCOM from the common voltage generator 121 (shown in Fig. 1).

The second substrate 300 includes a second insulating substrate 310 made of transparent glass or plastic and a plurality of color filters 330 provided on the second insulating substrate 310. Although not shown in the drawing, the color filter 330 may further include a black matrix provided in an area between adjacent color filters 330. The black matrix is provided in a region corresponding to the region where the data lines DL1 to DLm are formed, and blocks light leakage due to misalignment of the liquid crystal molecules. The second insulating substrate 310 is opposed to the first insulating substrate 210 and the liquid crystal layer LCL is interposed between the first and second substrates 200 and 300.

A contact hole CNT1 for exposing the first drain electrode DE of the thin film transistor T is formed in the first passivation layer 230 and the second passivation layer 240. [ The pixel electrode PE is formed on the drain electrode DE exposed by the second passivation layer 240 and the contact hole CNT1. The pixel electrode PE directly contacts the first drain electrode DE exposed through the contact hole CNT1 in the region where the contact hole CNT1 is defined in the upper portion of the second passivation layer 240. [

When a gate signal is applied to the pixel PX through the gate line GL3, the thin film transistor T is turned on in response to the gate signal. The data voltage applied to the data line DL1 is output to the drain electrode DE of the turn-on thin film transistor T and is applied to the pixel electrode PE.

An electric field may be formed between the pixel electrode PE receiving the data voltage and the common electrode CE receiving the common voltage VCOM. The liquid crystal molecules in the liquid crystal layer LCL can be rotated in a specific direction between the first insulating substrate 210 and the second insulating substrate 310 by an electric field. As the liquid crystal molecules rotate, the display substrate DP can transmit or block light. The rotation of the liquid crystal molecules may include not only rotation of the liquid crystal molecules but also the change of the orientation direction of the liquid crystal molecules by the electric field. The polarization of the light passing through the liquid crystal layer changes in accordance with the direction of the liquid crystal molecules thus determined.

The pixel electrode PE and the common electrode CE form a liquid crystal capacitor with the liquid crystal layer LCL as a dielectric to maintain the applied voltage even after the thin film transistor Tr is turned off. Although not shown in the figure, the pixel PX may further include a storage line overlapping the pixel electrode PE. The storage line and the pixel electrode PE may be formed by forming a storage capacitor with the gate insulating layer 120 and the first and second protective layers 230 and 250 as a dielectric to enhance the voltage holding capability of the liquid crystal capacitor Clc have.

The common voltage wiring LVCOM includes a first common voltage wiring 212, a second common voltage wiring 222, and a third common voltage wiring 232. The first common voltage wiring 212, the second common voltage wiring 222, and the third common voltage wiring 232 may be electrically connected to each other by the contact electrode 242.

The first common voltage wiring 212 includes the same material as the gate electrode GE and can be provided in the same process. The second common voltage wiring 222 includes the same material as the source electrode SE and the drain electrode DE and can be provided in the same process. The third common voltage wiring 232 can be formed by forming a metal layer on the first protective layer 230 of the non-display area NDA and patterning the metal layer. The metal layer may be formed of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver or silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum , Chromium (Cr), tantalum (Ta), titanium (Ti), and the like. The contact electrode 242 includes the same material as the pixel electrode PE and can be provided in the same process.

5 is an enlarged plan view of the region A shown in Fig. 6 is a cross-sectional view taken along the cutting line III-III 'shown in FIG. The area A shown in Fig. 1 is an area including a common voltage line LVCOM at a position close to the flexible circuit board 141 of the display substrate DP.

Referring to Figs. 1, 5 and 6, the common voltage wiring LVCOM includes a first common voltage wiring 212, a second common voltage wiring 222 and a third common voltage wiring 232.

The first contact hole CH1 exposing the first common voltage wiring 212 is formed in the second passivation layer 240, the first passivation layer 230 and the gate insulating layer 220. [ A second contact hole CH2 exposing the third common voltage wiring 232 and a third contact hole CH3 spaced apart from the second contact hole CH2 by a predetermined distance are formed in the second passivation layer 240. [ A fourth contact hole CH4 is formed in the second passivation layer 240 and the first passivation layer 230 to expose the second common voltage wiring 222. [ Exposed by the first common voltage wiring 212, the second contact hole CH2, and the third contact hole CH3 exposed by the first protective film 240, the second protective layer 240, the first common voltage wiring 212 exposed by the first contact hole CH1, A contact electrode 242 is formed on the second common voltage wiring 222 exposed by the voltage wiring 232 and the fourth contact hole CH4. The contact electrode 242 is directly connected to the first common voltage wiring 212 through the first contact hole CH1 at the upper portion of the second protective layer 240 and the second contact hole CH2 and the third contact hole Is directly connected to the third common voltage wiring 232 through the second contact hole CH3 and directly connected to the second common voltage wiring 222 through the fourth contact hole CH4. Therefore, the first common voltage wiring 212, the second common voltage wiring 222, and the third common voltage wiring 232 can be electrically connected to each other by the contact electrode 242.

 4, the first common voltage wiring 212 includes the same material as the gate electrode GE, and can be provided in the same process. The second common voltage wiring 222 includes the same material as the source electrode SE and the drain electrode DE and can be provided in the same process. Since the third common voltage wiring 232 is formed over the first common voltage wiring 212 and the second common voltage wiring 222, the third common voltage wiring 232 occupies a separate space for forming the third common voltage wiring 232 I never do that. In addition, since the total area of the common voltage wiring (LVCOM) is increased by the third common voltage wiring (232), the resistance of the common voltage wiring (LVCOM) can be reduced.

When the width W of the bezel region in the non-display region NDA of the display substrate DP shown in Fig. 1 is reduced, the line width WC of the common voltage wiring LVCOM shown in Fig. 3 also decreases. The common voltage wiring (LVCOM) further includes the third common voltage wiring (232), thereby preventing the resistance value from increasing even if the line width (WC) decreases.

7 is an enlarged plan view of the region B shown in Fig. 8 is a cross-sectional view taken along line IV-IV 'shown in FIG. The region B shown in FIG. 1 is an area including the common voltage wiring lines (LVCOM) at the lower end of the display substrate (DP) away from the flexible circuit boards (141 to 144).

Referring to FIGS. 1, 7 and 8, a fifth contact hole CH5 is formed in the second passivation layer 240 to expose the third common voltage wiring 232. A sixth contact hole CH6 is formed in the second passivation layer 240 and the first passivation layer 230 to expose the second common voltage wiring line 222. A seventh contact hole CH7 for exposing the first common voltage wiring 212 is formed in the second passivation layer 240, the first passivation layer 230 and the gate insulating layer 220. [

The third common voltage wiring 232 exposed by the fifth contact hole CH5, the second common voltage wiring 222 exposed by the sixth contact hole CH6, A contact electrode 242 is formed on the first common voltage wiring 212 exposed by the contact hole CH7. The contact electrode 242 is directly connected to the third common voltage wiring 232 through the fifth contact hole CH5 at the upper portion of the second protective layer 240 and is connected to the second common electrode 241 through the sixth contact hole CH6. Is directly connected to the voltage wiring 222 and directly connected to the first common voltage wiring 212 through the seventh contact hole CH7. Therefore, the first common voltage wiring 212, the second common voltage wiring 222, and the third common voltage wiring 232 can be electrically connected to each other by the contact electrode 242.

As described above, by electrically connecting the first common voltage wiring 212, the second common voltage wiring 222 and the third common voltage wiring 232 through the contact electrode 242 at a predetermined position of the display substrate DP The resistance of the common voltage wiring (LVCOM) can be lowered.

The following Table 1 exemplarily shows the sheet resistance of the first common voltage wiring 212, the second common voltage wiring 222 and the third common voltage wiring 232, respectively.

Wiring matter Thickness [um] Surface resistance [uΩ / um] The first common voltage wiring 212, Ti / Cu 100/2500 0.096 The second common voltage wiring 222, CBL / Cu / CCL 200/2000/200 0.120 The third common voltage wiring 232, Cu 1000 0.240

In Table 1, the first common voltage wiring 212 has a multilayer including titanium (Ti) and copper (Cu), the second common voltage wiring 222 includes a CBL (Cu barrier layer) And a CC capping layer (CCL). However, the present invention is not limited thereto.

The following Table 2 shows the sheet resistance when the common voltage wiring LVCOM includes some and all of the first common voltage wiring 212, the second common voltage wiring 222 and the third common voltage wiring 232 Show them as enemies.

Common voltage wiring combination Surface resistance [uΩ / um] The first common voltage wiring 212 +
The second common voltage wiring 222, 0.053 The first common voltage wiring 212 +
The third common voltage wiring 232, 0.069 The second common voltage wiring 222 +
The third common voltage wiring 232, 0.080 The first common voltage wiring 212 +
The second common voltage wiring 222 +
The third common voltage wiring 232, 0.044

As can be seen from Table 2, when the common voltage wiring LVCOM includes both the first common voltage wiring 212, the second common voltage wiring 222 and the third common voltage wiring 232, It can be seen that the sheet resistance of the voltage wiring (LVCOM) is the smallest.

As the resistance of the common voltage wiring LVCOM decreases, the ripple decreases in the common voltage VCOM transmitted through the common voltage wiring LVCOM, and as a result, the quality of the image displayed through the display substrate DP is improved .

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. It will be possible. In addition, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, and all technical ideas which fall within the scope of the following claims and equivalents thereof should be interpreted as being included in the scope of the present invention .

100: Display device DP: Display substrate
120: main circuit board 121: common voltage generator
122: driving controller 130: data driving circuit
131 to 133: Data driving chips 141 to 144: Flexible circuit board
150: gate drive circuits 151 to 154: gate drive chips

Claims (13)

A plurality of pixels formed on a substrate;
A common voltage wiring line including first through third common voltage lines electrically connected to the plurality of pixels and arranged on different layers on the substrate; And
And a contact electrode for electrically connecting the first to third common voltage wirings to each other. The method according to claim 1,
Wherein each of the plurality of pixels includes:
A transistor formed on the substrate; And
And a liquid crystal capacitor including a pixel electrode electrically connected to the transistor and a common electrode. 3. The method of claim 2,
Wherein the contact electrode comprises the same material as the pixel electrode and is provided in the same process. 3. The method of claim 2,
The transistor comprising:
A gate electrode formed on the substrate;
An insulating layer stacked over the entire substrate on which the gate electrode is formed;
A semiconductor layer formed on the insulating layer;
A source electrode and a drain electrode formed on the semiconductor layer; And
And a first protective layer stacked over the entire substrate on which the source electrode and the drain electrode are formed. 5. The method of claim 4,
And the first common voltage wiring is located at the same level as the gate electrode. 6. The method of claim 5,
The third common voltage wiring is formed on the first protective layer,
And a second protective layer formed on the third common voltage wiring. The method according to claim 6,
And the contact electrode is formed on the second passivation layer. 8. The method of claim 7,
Further comprising a first contact hole penetrating through the second protection layer, the first protection layer, and the insulation layer formed on the first common voltage wiring,
And the first common voltage wiring is in direct contact with the contact electrode through the first contact hole. 8. The method of claim 7,
And the second common voltage wiring is located at the same level as the source electrode and the drain electrode. 10. The method of claim 9,
And a second contact hole penetrating through the second protection layer and the first protection layer formed on the second common voltage wiring,
And the second common voltage wiring is in direct contact with the contact electrode through the second contact hole. 8. The method of claim 7,
And a third contact hole penetrating the second protection layer formed on the third common voltage wiring,
And the third common voltage wiring is in direct contact with the contact electrode through the third contact hole. The method according to claim 1,
Wherein:
A display device, comprising: a display area; and a non-display area surrounding the display area,
And the common voltage wiring is arranged in the non-display region. The method according to claim 1,
Wherein the contact electrode electrically connects the first common voltage wiring and the third common voltage wiring, and electrically connects the second common voltage wiring and the third common voltage wiring.

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