KR20080098882A - Liquid crystal display - Google Patents

Abstract

A liquid crystal display device is provided to widen viewing angle by generating voltage difference which are applied to each sub pixel electrode, and to reduce the number of driving chips by arranging pixels cross direction. A first and a second gate lines(GLi,GLi+1) are arranged side by side to the first direction. Data lines(DLj,DLj+1) are insulated and intersects with the first gate line. A pixel electrode consisting of the first and the second sub-pixel electrode(Pa,Pb) is positioned within long one pixel and is electrically separated into the first direction. A thin film transistor(T1) is connected to the first gate line, and data line and the first sub-pixel electrode. A second thin film transistor(T2) is connected to the first gate line, and data line and the second sub-pixel electrode. A third thin film transistor(T3) is connected to the charge distribution capacitor distributing data voltage applied at the second gate line, and the second sub-pixel electrode and the second sub-pixel electrode.

Description

Liquid crystal display

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a structure of the liquid crystal display of FIG. 1.

3 is a timing diagram illustrating an operation of a gate driver of FIG. 1.

4 is a layout view of a lower panel of a liquid crystal display according to an exemplary embodiment of the present invention.

5 is a cross-sectional view of the lower panel of FIG. 4 taken along the line VV ′.

6 is a layout view of an upper panel of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 7 is a layout view of a liquid crystal display including the lower panel of FIG. 4 and the upper panel of FIG. 6.

8 is a cross-sectional view of the liquid crystal display of FIG. 7 taken along the line 'VIII'.

(Explanation of symbols for the main parts of the drawing)

10: insulating substrate 30: gate insulating film

40: semiconductor layer 55, 56: ohmic contact layer

70: shield 83: gap

90: common electrode 92: second domain dividing means

94: black matrix 98: color filter

96: insulating substrate 100: lower display panel

150: liquid crystal layer 200: upper display panel

300: liquid crystal panel assembly 400a, 400b: gate driver

500: data driver 600: signal controller

800: gray voltage generator GLi, GLi + 1, GLi + 2: gate line

DLj, DLj + 1: data lines D1, D2, D3: drain electrodes

S1, S2, S3: source electrode G1, G2, G3: gate electrode

H1, H2, H3: contact hole Pa, Pb: subpixel electrode

PE: pixel electrode SLi, SLi + 1, SLi + 2: storage line

The present invention relates to a display device, and more particularly, to a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which field generating electrodes such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. Is applied to generate an electric field in the liquid crystal layer, thereby determining the orientation of liquid crystal molecules in the liquid crystal layer and controlling the polarization of incident light to display an image.

In addition, the vertical alignment mode liquid crystal display in which the long axis of the liquid crystal molecules are arranged perpendicular to the upper and lower display panels without an electric field is applied, and thus the display panel has a high contrast ratio and is easy to implement a wide reference viewing angle. Here, the reference viewing angle refers to a viewing angle having a contrast ratio of 1:10 or a luminance inversion limit angle between gray levels.

Means for implementing a wide viewing angle in a vertical alignment mode liquid crystal display include a method of forming a cutout in the field generating electrode and a method of forming a protrusion on the field generating electrode. Since the inclination and the projection can determine the direction in which the liquid crystal molecules are tilted, the reference viewing angle can be widened by using these to disperse the oblique directions of the liquid crystal molecules in various directions.

However, the liquid crystal display of the vertical alignment type has a problem in that the side visibility is inferior to the front visibility. For example, in the case of a patterned vertically aligned (PVA) type liquid crystal display device having an incision, the image becomes brighter toward the side, and in a severe case, the luminance difference between the high grays disappears and the picture may appear clumped.

In addition, as the resolution of the liquid crystal display increases, the number of data lines and the number of data driving chips increase, leading to an increase in manufacturing cost and difficulty in miniaturizing the liquid crystal display.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a liquid crystal display device capable of lowering manufacturing cost while increasing side visibility.

Technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes: first and second gate lines arranged side by side in a first direction, a data line insulated from and intersecting the first gate line, and the first A pixel electrode including first and second subpixel electrodes positioned in one pixel long in a direction and electrically separated from each other, and a first thin film connected to the first gate line, the data line, and the first subpixel electrode Applied to a transistor, a second thin film transistor connected to the first gate line, the data line, and the second subpixel electrode, the second gate line, the second subpixel electrode, and the second subpixel electrode. And a third thin film transistor connected to the charge distribution capacitor for distributing the data voltage.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

When elements or layers are referred to as "on" or "on" of another element or layer, intervening other elements or layers as well as intervening another layer or element in between. It includes everything. On the other hand, when a device is referred to as "directly on" or "directly on" indicates that no device or layer is intervened in the middle. Like reference numerals refer to like elements throughout. “And / or” includes each and all combinations of one or more of the items mentioned.

The spatially relative terms " below ", " beneath ", " lower ", " above ", " upper " It may be used to easily describe the correlation of a device or components with other devices or components. Spatially relative terms are to be understood as terms that include different directions of the device in use or operation in addition to the directions shown in the figures.

Embodiments described herein will be described with reference to plan and cross-sectional views, which are ideal schematic diagrams of the invention. Accordingly, shapes of the exemplary views may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include variations in forms generated by the manufacturing process. Accordingly, the regions illustrated in the figures have schematic attributes, and the shape of the regions illustrated in the figures is intended to illustrate a particular form of region of the device, and is not intended to limit the scope of the invention.

Hereinafter, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 2 is a circuit diagram illustrating a structure of the liquid crystal display of FIG. 1, and FIG. 3 is a timing diagram of an operation of the gate driver of FIG. 1. .

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, gate drivers 400a and 400b, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 includes a plurality of display signal lines and a plurality of pixels PX connected to the display signal lines and arranged in a substantially matrix form when viewed in an equivalent circuit. The liquid crystal panel assembly 300 may include a lower panel, an upper panel, and a liquid crystal layer interposed therebetween.

The display signal line is provided in the lower panel and includes a plurality of gate lines G1 -Gn for transmitting the gate signal and data lines D1 -Dm for transmitting the data signal. The gate lines G1 -Gn extend substantially in the row direction and are substantially parallel to each other, and the data lines D1 -Dm extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX includes a switching element connected to a corresponding gate line G1 -Gn and data lines D1 -Dm, and a liquid crystal capacitor connected thereto. In this case, a storage capacitor may be formed in the switching device as necessary.

The switching element of each pixel PX is formed of a thin film transistor, and the like, and a control terminal connected to a corresponding gate line G1 -Gn, an input terminal connected to a data line D1 -Dm, and a liquid crystal capacitor, respectively. It is a three-terminal device having an output terminal connected to.

The gate drivers 400a and 400b are connected to the gate lines G1 -Gn to apply a gate signal formed of a combination of a gate on voltage Von and a gate off voltage Voff from the outside to the gate lines G1 -Gn. do. The pair of gate drivers 400a and 400b illustrated in FIG. 1 are positioned at left and right sides of the liquid crystal panel assembly 300, respectively, and are connected to odd-numbered and even-numbered gate lines G1 -Gn, respectively. Of course, the gate drivers 400a and 400b may be disposed on one side of the liquid crystal panel assembly 300. In addition, the gate drivers 400a and 400b may be embedded on the lower panel of the liquid crystal panel assembly 300 in an integrated circuit form.

The gray voltage generator 800 generates a gray voltage related to the transmittance of the pixel. The gray voltage is provided to each pixel, and includes a positive value and a negative value with respect to the common voltage Vcom.

The data driver 500 is connected to the data lines D1 -Dm of the liquid crystal panel assembly 300 to apply the gray voltage from the gray voltage generator 800 as a data voltage to the pixel. Here, when the gray voltage generator 800 does not provide all the voltages for all grays, but only the basic gray voltages, the data driver 500 divides the basic gray voltages to generate gray voltages for all grays. You can select the data voltage among them.

The gate drivers 400a and 400b or the data driver 500 may be integrated in the liquid crystal panel assembly 300 together with the display signal lines G1 -Gn and D1 -Dm and the thin film transistors. Alternatively, the gate drivers 400a and 400b or the data driver 500 may be mounted on a flexible printed circuit film (not shown) to form the liquid crystal panel assembly 300 in the form of a tape carrier package. ) May be attached.

The signal controller 600 controls operations of the gate drivers 400a and 400b and the data driver 500.

2, a liquid crystal display according to an exemplary embodiment of the present invention may include a plurality of gate lines GLi, GLi + 1, and GLi + 2, gate lines GLi, GLi + 1, A plurality of data lines DLj and DLj + 1 are formed to intersect GLi + 2 and transmit data signals.

The first thin film transistor T1 and the second thin film transistor T2 are formed at an intersection point of the i-th gate line GLi and the j-th data line DLj, and the i + 2 th gate line GLi + 2. The third thin film transistor T3 is connected to the third thin film transistor T3.

That is, the first thin film transistor T1 includes a gate electrode connected to the i-th gate line GLi, a source electrode connected to the j-th data line DLj, a first liquid crystal capacitor Clc1 and a first storage capacitor ( And a drain electrode connected to Cst1). The second thin film transistor T2 is connected to the gate electrode connected to the i-th gate line GLi, the source electrode connected to the j-th data line DLj, and the second liquid crystal capacitor Clc2 and the second storage capacitor Cst2. And a connected drain electrode. The third thin film transistor T3 includes a gate electrode connected to the i + 2 gate line GLi + 2, a source electrode connected to the drain electrode of the second thin film transistor T2, and a drain connected to the charge distribution capacitor Ccs. An electrode.

For each pixel constituting the lower panel of the structure, a pixel including a first subpixel electrode connected to the drain electrode of the first thin film transistor T1 and a second subpixel electrode connected to the drain electrode of the second thin film transistor T2. An electrode is formed. The common electrode is formed on the upper panel facing the lower panel.

The first liquid crystal capacitor Clc1 includes a first subpixel electrode connected to the first thin film transistor T1, a common electrode, and a liquid crystal material interposed therebetween. The first storage capacitor Cst1 includes a first subpixel electrode, a storage line formed on the lower panel, and a dielectric material interposed therebetween.

The second liquid crystal capacitor Clc2 includes a second subpixel electrode connected to the second thin film transistor T2, a common electrode, and a liquid crystal material interposed therebetween. The second storage capacitor Cst2 includes a second subpixel electrode, a storage line formed on the lower display panel, and a dielectric material interposed therebetween.

The charge distribution capacitor Ccs is formed of a drain electrode of the third thin film transistor T3, a storage line formed on the lower display panel, and a dielectric material interposed therebetween.

2 and 3, when an ON signal is transmitted to the i-th gate line GLi, the i-th row is provided through the first thin film transistor T1 and the second thin film transistor T2. The same data voltage is transmitted to the located first subpixel electrode and the second subpixel electrode. That is, the same data voltage is charged in the first liquid crystal capacitor Clc1 and the second liquid crystal capacitor Clc2 connected to the i-th gate line GLi. Subsequently, when the OFF signal is transmitted to the i-th gate line GLi, the first subpixel electrode and the second subpixel electrode are separated from each other. That is, each of the first subpixel electrode and the second subpixel electrode maintains a floating state after the same data voltage is applied.

When the on signal is transmitted to the i + 1 th gate line GLi + 1, a pair of subpixels positioned in the i + 1 row through a pair of thin film transistors connected to the i + 1 gate line GLi + 1 The same data voltage is delivered to each electrode. The i + 1 th gate on signal may be transmitted before the i th gate off signal. In this case, while the data voltage is applied to the pair of subpixel electrodes positioned in the i th row, the data voltage may be precharged to the pair of subpixel electrodes positioned in the i + 1 th row. That is, the precharging method means that the gate-on signal is sequentially applied to a plurality of gate lines GLi, GLi + 1, and GLi + 2. Therefore, as in the exemplary embodiment of the present invention, the long side of the pixel is arranged in the horizontal direction, so that the driving time can be shortened even if the number of gate lines is increased. However, the present invention is not limited thereto, and the i + 1 th gate on signal may be transferred after the i th gate off signal. Subsequently, when the OFF signal is transmitted to the i + 1 th gate line GLi + 1, the pair of subpixel electrodes connected thereto are separated from each other to maintain a floating state.

When the on signal is transmitted to the i + 2th gate line GLi + 2, a pair of subpixels positioned in the i + 2th row through a pair of thin film transistors connected to the i + 2th gate line GLi + 2 The same data voltage is delivered to each electrode. As described above, the i + 2 th gate on signal may be transmitted before the i + 1 th gate off signal.

When the on signal is transmitted to the i + 2 th gate line GLi + 2, the data voltage stored in the second subpixel electrode connected to the second thin film transistor T2 is transferred through the third thin film transistor T3. Is distributed to (Ccs). This is because the source electrode of the third thin film transistor T3 is connected to the second subpixel electrode connected to the second thin film transistor, and the drain electrode of the third thin film transistor T3 is connected to the charge distribution capacitor Ccs. to be. Therefore, the data voltages stored in the first subpixel electrode and the second subpixel electrode positioned in the i th row and connected to the first thin film transistor T1 and the second thin film transistor T2 respectively have different values. In detail, since the data voltage of the second subpixel electrode connected to the second thin film transistor T2 is transferred to the charge distribution capacitor Ccs through the third thin film transistor T3, the data voltage of the second subpixel electrode is lowered. do.

As such, when the data voltages respectively stored in the first and second subpixel electrodes positioned in one pixel have different values, side visibility may be improved. That is, a pair of gradation voltage sets having different gamma curves obtained from one image information are stored in the first and second subpixel electrodes, and the gamma curve of one pixel electrode composed of the first and second subpixel electrodes is It becomes a gamma curve which synthesize | combined these. When determining a pair of gradation voltage sets, the side gamma curve is closer to the front reference gamma curve, and the side gamma curve is closest to the front reference gamma curve, thereby improving side visibility. You can.

Subsequently, when the OFF signal is transmitted to the i + 2 th gate line GLi + 2, the pair of subpixel electrodes connected thereto are separated from each other to maintain a floating state. In addition, the second subpixel electrode connected to the second thin film transistor T2 positioned in the i th row and the charge distribution capacitor Ccs are also separated from each other to maintain a floating state.

Hereinafter, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 4 to 8. The liquid crystal display according to the present exemplary embodiment includes a lower panel, an upper panel facing the panel, and a liquid crystal layer interposed therebetween.

First, the lower panel of the liquid crystal display according to the exemplary embodiment will be described with reference to FIGS. 4 and 5. 4 is a layout view of a lower panel of the liquid crystal display according to the exemplary embodiment, and FIG. 5 is a cross-sectional view of the lower panel of FIG. 4 taken along the line VV ′.

Gate lines GLi, GLi + 1, and GLi + 2 are formed on the insulating substrate 10 in a first direction, for example, in a horizontal direction. The first gate electrode G1 and the second gate electrode G2 formed in the form of a protrusion are formed on the i-th gate line GLi. A third gate electrode G3 formed in the form of a protrusion is formed on the i + 2 th gate line GLi + 2. The gate lines GLi, GLi + 1, and GLi + 2 and the gate electrodes G1, G2, and G3 are referred to as gate wirings.

Storage lines SLi, SLi + 1, and SLi + 2 are formed on the insulating substrate 10 in the horizontal direction along the gate lines GLi, GLi + 1, and GLi + 2. The storage lines SLi, SLi + 1, and SLi + 2 may have protrusions to overlap the first subpixel electrode Pa and the second subpixel electrode Pb. However, the shape and arrangement of the storage lines SLi, SLi + 1, and SLi + 2 may be modified in various forms. The common voltage Vcom may be applied to the storage lines SLi, SLi + 1, and SLi + 2.

Gate wirings (GLi, GLi + 1, GLi + 2, G1, G2, G3) and storage lines (SLi, SLi + 1, SLi + 2) include aluminum-based metals such as aluminum (Al) and aluminum alloys, silver (Ag ) Metals such as silver and silver alloys, copper metals such as copper (Cu) and copper alloys, molybdenum metals such as molybdenum (Mo) and molybdenum alloys, chromium (Cr), titanium (Ti), tantalum (Ta) It can be made. In addition, the gate lines GLi, GLi + 1, GLi + 2, G1, G2, and G3 and the storage lines SLi, SLi + 1, and SLi + 2 include two conductive films (not shown) having different physical properties. It may have a multilayer structure. One of these conductive films has a low resistivity to reduce signal delay or voltage drop of the gate wirings (GLi, GLi + 1, GLi + 2, G1, G2, G3) and storage lines (SLi, SLi + 1, SLi + 2). (resistivity) metal, for example, aluminum-based metal, silver-based metal, copper-based metal and the like. In contrast, the other conductive layer is made of a material having excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, titanium, tantalum and the like. A good example of such a combination is a chromium bottom film and an aluminum top film and an aluminum bottom film and a molybdenum top film. However, the present invention is not limited thereto, and the gate lines GLi, GLi + 1, GLi + 2, G1, G2, and G3 and the storage lines SLi, SLi + 1, and SLi + 2 may be formed of various metals. It can be made of a conductor.

The gate insulating layer 30 is formed on the gate lines GLi, GLi + 1, GLi + 2, G1, G2, and G3 and the storage lines SLi, SLi + 1, and SLi + 2.

On the gate insulating film 30, a semiconductor layer 40 made of hydrogenated amorphous silicon, polycrystalline silicon, or the like is formed. The semiconductor layer 40 may have various shapes such as an island shape and a linear shape. For example, the semiconductor layer 40 may be formed in an island shape on the gate electrodes G1, G2, and G3 as in the present embodiment. In addition, when the semiconductor layer 40 is linearly formed, the semiconductor layer 40 may be positioned below the data line DLj and may extend to an upper portion of the gate electrodes G1, G2, and G3.

On the semiconductor layer 40, ohmic contact layers 55 and 56 made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration are formed. The ohmic contact layers 55 and 56 may have various shapes such as island shape and linear shape. For example, in the case of the island type ohmic contact layers 55 and 56 as in the present embodiment, the first drain electrode D1 and The linear ohmic contact layer may be disposed below the first source electrode S1 and may extend to below the data lines DLj and DLj + 1.

The data lines DLj and DLj + 1, the first drain electrode D1, the second drain electrode D2, and the third drain electrode D3 are formed on the ohmic contact layers 55 and 56 and the gate insulating layer 30. It is. The data lines DLj and DLj + 1 extend in the second direction, for example, the vertical direction, and define a pixel by crossing the gate lines GLi, GLi + 1, and GLi + 2. The first source electrode S1 and the second source electrode S2 extending from the j-th data line DLj to the upper portion of the first gate electrode G1 in a branch form are formed. The first drain electrode D1 is separated from the first source electrode S1 and is positioned on the semiconductor layer 40 so as to face the first source electrode S1 about the first gate electrode G1. The second drain electrode D2 is separated from the second source electrode S2 and positioned on the semiconductor layer so as to face the second source electrode S2 about the second gate electrode G2. The first drain electrode D1 and the second drain electrode D2 have a rod-shaped pattern on the semiconductor layer 40, and extend from the rod-shaped pattern to have a large area, and have a first contact hole H1 and a second contact hole. And a drain electrode extension where (H2) is located. The first contact hole H1 and the second contact hole H2 are formed to overlap the first subpixel electrode Pa and the second subpixel electrode Pb, respectively.

The third source electrode S3 extends from the third contact hole H3 overlapping the second subpixel electrode Pb to the upper portion of the third gate electrode G3, and the third drain electrode D3 is formed of a third source electrode S3. It extends from the top of the third gate electrode G3 to the top of the i + 1th storage line SLi + 1. The third drain electrode D3 is separated from the third source electrode S3 and is positioned on the semiconductor layer so as to face the third source electrode S3 about the third gate electrode G3.

The data lines DLj and DLj + 1, the first source electrode S1, the second source electrode S2, the third source electrode S3, the first drain electrode D1, and the second drain electrode D2. And the third drain electrode D3 is called data wiring.

The data wirings DLj, DLj + 1, S1, S2, S3, D1, D2, and D3 are preferably made of refractory metals such as chromium, molybdenum-based metals, tantalum, and titanium. ) And a low resistance material upper layer (not shown) disposed thereon. Examples of the multilayer film structure include a triple film of molybdenum film, aluminum film, and molybdenum film in addition to the above-described double film of chromium lower film and aluminum upper film or aluminum lower film and molybdenum upper film.

At least a portion of the first source electrode S1 overlaps the semiconductor layer 40, and the first drain electrode D1 faces the first source electrode S1 with the center of the first gate electrode G1 facing the semiconductor layer 40. At least a portion overlaps with 40. The ohmic contact layers 55 and 56 are interposed between the semiconductor layer 40 and the first source electrode S1, and the semiconductor layer 40 and the first drain electrode D1 to lower contact resistance therebetween. Do it.

In addition, at least a portion of the second source electrode S2 overlaps with the semiconductor layer, and the second drain electrode D2 faces the second source electrode S2 with respect to the second gate electrode G2 and at least with the semiconductor layer. Some parts overlap. The ohmic contact layer is interposed between the semiconductor layer and the second source electrode S2 and the semiconductor layer and the second drain electrode D2 to lower the contact resistance therebetween.

A protective film 70 made of an insulating film is formed on the data lines DLj, DLj + 1, S1, S2, S3, D1, D2, and D3 and the semiconductor layer 40 exposed thereby. The protective film 70 is an inorganic material made of silicon nitride or silicon oxide, an organic material having excellent planarization characteristics and photosensitivity, or a-Si: C: O formed by plasma enhanced chemical vapor deposition (PECVD). and a low dielectric constant insulating material such as a-Si: O: F. In addition, the passivation layer 70 may have a double layer structure of the lower inorganic layer and the upper organic layer in order to protect the exposed portion of the semiconductor layer 40 while maintaining excellent characteristics of the organic layer.

In the passivation layer 70, the first contact hole H1, the second contact hole, and the third contact hole H3 exposing the first drain electrode D1, the second drain electrode D2, and the third drain electrode D3, respectively. ) Is formed.

On the passivation layer 70, a pixel electrode PE having a long, substantially rectangular shape in a substantially horizontal direction is formed along the shape of the pixel. The pixel electrode PE includes a first subpixel electrode Pa connected to the first drain electrode D1 through the first contact hole H1, a second contact hole H2, and a third contact hole H3. The second subpixel electrode Pb is connected to the second drain electrode D2 and the third drain electrode D3, respectively. Here, the first subpixel electrode Pa and the second subpixel electrode Pb may be made of a transparent conductor such as ITO or IZO or a reflective conductor such as aluminum.

The first subpixel electrode Pa and the second subpixel electrode Pb are respectively connected to the first drain electrode D1 and the second drain electrode D2 through the first contact hole H1 and the second contact hole H2. ) Is connected physically and electrically to receive a data voltage from the first drain electrode D1 and the second drain electrode D2. In the present exemplary embodiment, since the first source electrode S1 and the second source electrode S2 are respectively connected to the first drain electrode D1 and the second drain electrode D2, the first subpixel is connected. Substantially the same data voltage is applied to the electrode Pa and the second subpixel electrode Pb from the jth data line DLj.

The first subpixel electrode Pa and the second subpixel electrode Pb to which the data voltage is applied generate an electric field together with the common electrode of the upper panel, thereby forming the first subpixel electrode Pa and the second subpixel electrode between the common electrode and the second subpixel electrode. The arrangement of the liquid crystal molecules of the liquid crystal layer positioned between the pixel electrode Pb and the common electrode is determined.

The first subpixel electrode Pa and the second subpixel electrode Pb constituting one pixel area are separated from each other with a predetermined gap 83 therebetween, and the outer boundary thereof is substantially horizontal. It is a long rectangle. The first subpixel electrode Pa has a rotated V shape and is disposed in the center of the pixel area. The second subpixel electrode Pb is formed at a portion of the rectangular pixel area except for the second subpixel electrode Pb. Here, the gap 83 includes a portion that is substantially 45 degrees and a portion that is -45 degrees with the transmission axis or the gate lines GLi, GLi + 1, and GLi + 2 of the polarizing plate. Accordingly, edges of the first subpixel electrode Pa and the second subpixel electrode Pb adjacent to the gap 83 are substantially -45 with the transmission axis or gate lines GLi, GLi + 1, and GLi + 2 of the polarizer. Degrees or 45 degrees (hereinafter referred to as an oblique direction). The first subpixel electrode Pa and the second subpixel electrode Pb may have first domain division means (not shown) such as a plurality of cutouts or protrusions in an oblique direction. The display area of the pixel electrode PE is divided into a plurality of domains according to the direction in which the main directors of the liquid crystal molecules included in the liquid crystal layer are arranged when an electric field is applied. The gap 83 and the first domain dividing means serve to divide the pixel electrode PE into many domains. In this case, the domain refers to an area formed of liquid crystal molecules in which the directors of the liquid crystal molecules are inclined in a specific direction by an electric field formed between the pixel electrode PE and the common electrode (see reference numeral 90 in FIG. 6).

As described above, when the on signal is transmitted to the i-th gate line GLi, the first subpixel electrode Pa and the second sub-pixel adjacent to the i-th gate line GLi are provided with the same data voltage from the j th data line DLj. It is applied to the pixel electrode Pb. Subsequently, when the on signal is transmitted to the i + 2 gate line GLi + 2, the data voltage stored in the second subpixel electrode Pb is distributed to the third drain electrode D3 through the third thin film transistor T3. . A charge distribution capacitor is formed between the third drain electrode D3 and the i + 1th storage line SLi + 1 disposed below it. Therefore, a relatively low data voltage is stored in the second subpixel electrode Pb, and a relatively high data voltage is stored in the first subpixel electrode Pa.

An alignment layer (not shown) may be coated on the first subpixel electrode Pa, the second subpixel electrode Pb, and the passivation layer 70 to align the liquid crystal layer.

Next, the upper panel and the liquid crystal display including the same will be described with reference to FIGS. 6 to 8. 6 is a layout view of an upper panel of the liquid crystal display according to an exemplary embodiment of the present invention. FIG. 7 is a layout view of a liquid crystal display including the lower panel of FIG. 4 and the upper panel of FIG. 6, and FIG. It is sectional drawing which cut | disconnected the liquid crystal display device with a VIII-VIII line.

A common electrode made of a black matrix 94 for preventing light leakage on the insulating substrate 96 made of transparent glass, a color filter 98 of red, green, and blue, and a transparent conductive material such as ITO or IZO. ) 90 is formed. Here, the black matrix 94 is a portion corresponding to the gate lines GLi, GLi + 1, and GLi + 2 and the data lines DLj and DLj + 1, and a portion corresponding to the thin film transistors T1, T2, and T3. Can be formed. In addition, the black matrix 94 may have various shapes to block light leakage near the first subpixel electrode Pa, the second subpixel electrode Pb, and the thin film transistors T1, T2, and T3.

The common electrode 90 faces the first subpixel electrode Pa and the second subpixel electrode Pb and has a plurality of second domain dividing means 92. The second domain dividing means 92 may consist of an incision or a protrusion. Here, the second domain dividing means 92 includes an oblique portion that is substantially -45 degrees or 45 degrees with the transmission axis or the gate lines GLi, GLi + 1, GLi + 2 of the polarizing plate. In the present embodiment, for convenience of description, the present invention will be described by using the second domain dividing means 92 having a cutout.

The oblique portions of the second domain dividing means 92 of the common electrode 90 are alternately arranged with the gap 83 between the first subpixel electrode Pa and the second subpixel electrode Pb.

An alignment layer (not shown) may be coated on the common electrode 90 to align the liquid crystal molecules of the liquid crystal layer 150.

When the lower display panel 100 and the upper display panel 200 having the above structure are aligned to each other and vertically aligned with a liquid crystal material interposed therebetween, a basic structure of the liquid crystal display device is provided. The liquid crystal display device is formed by disposing elements such as a polarizing plate and a backlight on the basic structure. In this case, one polarizing plate (not shown) is disposed on each side of the basic structure, and its transmission axis is arranged to be parallel to the gate lines GLi, GLi + 1, and GLi + 2, and the other one is perpendicular thereto. When the liquid crystal display device is formed as described above, when an electric field is applied to the liquid crystal, the liquid crystal in each domain is inclined in a direction perpendicular to the gap 83 or the second domain dividing means 92 for dividing the domain. . Therefore, the liquid crystal of each domain is inclined approximately 45 degrees or -45 degrees with respect to the transmission axis or gate lines GLi, GLi + 1, GLi + 2 of the polarizing plate. A lateral field formed between the gap 83 or the second domain dividing means 92 assists the liquid crystal alignment of each domain.

In the above embodiment, a case where the third thin film transistor T3 is connected to the i + 2 th gate line GLi + 2 has been described as an example, but the present invention is not limited thereto. That is, when the precharging method is not applied between the i-th gate line GLi and the i + 1 th gate line GLi + 1, the third thin film transistor T3 may include the i + 1 th gate line GLi + 1. ) May be connected.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, according to the liquid crystal display according to the present invention, a pixel electrode is divided into a pair of subpixel electrodes, and a difference occurs in the data voltage applied to each subpixel electrode through charge sharing. By this, side visibility can be improved. In addition, by arranging the long sides of the pixels in the horizontal direction, the number of data lines and the number of data driving chips can be significantly reduced, thereby lowering the manufacturing cost. In this case, when the gate voltage is applied to the gate line, the precharging method may reduce the driving time even if the number of gate lines increases.

Claims (7)

First and second gate lines arranged side by side in a first direction; A data line insulated from and intersecting the first gate line; A pixel electrode disposed in one pixel elongated in the first direction, the pixel electrode including first and second subpixel electrodes electrically separated from each other; A first thin film transistor connected to the first gate line, the data line, and the first subpixel electrode; A second thin film transistor connected to the first gate line, the data line, and the second subpixel electrode; And And a third thin film transistor connected to the second gate line, the second subpixel electrode, and a charge distribution capacitor for distributing a data voltage applied to the second subpixel electrode. According to claim 1, And a third gate line arranged side by side between the first gate line and the second gate line. The method of claim 2, And a gate on signal sequentially applied to the first gate line, the third gate line, and the second gate line. According to claim 1, Further comprising a storage line arranged in parallel with the gate line, The charge distribution capacitor is configured to overlap the drain electrode of the third thin film transistor and the storage line. According to claim 1, The same data voltage is applied to the first subpixel electrode and the second subpixel electrode from the data line. According to claim 1, The data voltage applied to the second subpixel electrode is distributed to the charge distribution capacitor through the third thin film transistor. The method of claim 6, And a data voltage stored at the first subpixel electrode is greater than a data voltage stored at the second subpixel electrode.

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