KR101435133B1 - Liquid crystal display - Google Patents

Abstract

A liquid crystal display device capable of improving display quality is provided. The liquid crystal display device includes a first insulating substrate, gate wirings formed on the first insulating substrate and extending in a first direction, data wirings intersecting and insulated from the gate wirings and extending in a second direction, A pixel electrode including first and second sub-pixel electrodes to which a voltage is applied, wherein at least a part of the second sub-pixel electrode includes a pixel electrode overlapping the data line.

LCD, coupling, capacitance, overlap

Description

[0001] Liquid crystal display [0002]

1 is a diagram schematically showing a pixel array of a liquid crystal display according to an embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of the liquid crystal display of FIG.

3A is a layout diagram of a lower panel including an A-type pixel of FIG. 1 according to an embodiment of the present invention.

FIG. 3B is a cross-sectional view of the lower panel of FIG. 3A taken along lines IIIb-IIIb '.

FIG. 3C is a cross-sectional view of the lower panel of FIG. 3A taken along lines IIIc-IIIc '.

Fig. 4 is a layout diagram of an upper panel coupled with the lower panel of Fig. 3a.

FIG. 5 is a layout diagram of a liquid crystal display including the lower panel of FIG. 3a and the upper panel of FIG.

6 is a layout diagram of a lower panel including the B-type pixel of FIG. 1 according to an embodiment of the present invention.

7A is a layout diagram of a lower panel including an A-type pixel of FIG. 1 according to another embodiment of the present invention.

7B is a cross-sectional view of the lower panel of FIG. 7A taken along lines VIIb-VIIb '.

8 is a layout diagram of a lower display panel including a B-type pixel of FIG. 1 according to another embodiment of the present invention.

FIG. 9A is a graph showing the difference in luminance between the first sub-pixel electrode Pa of the A-type pixel and the first sub-pixel electrode Pa of the B-type pixel in FIG. 1 as the gradation is changed.

FIG. 9B is a graph showing the difference in luminance between the second sub-pixel electrode Pb of the A-type pixel and the second sub-pixel electrode Pb of the B-type pixel in FIG. 1 as the gradation is changed.

DESCRIPTION OF THE REFERENCE NUMERALS (S)

10: insulating substrate 22: gate line

26a, 26b: gate electrode 27: storage electrode

28: Story line 29a, 29b: Additional storage electrode

30: gate insulating film 40a, 40b: semiconductor layer

55a, 56a: ohmic contact layers 62a, 62b: data lines

65a, 65b: source electrode 66a, 66b: drain electrode

70: protective film 76a, 76b: contact hole

82: pixel electrodes 82a and 82b:

83: gap 90: common electrode

92: Domain dividing means 94: Black matrix

The present invention relates to a display device, and more particularly, to a liquid crystal display device.

2. Description of the Related Art [0002] A liquid crystal display device is one of the most widely used flat panel display devices, and is composed of two display panels having field generating electrodes such as a pixel electrode and a common electrode, and a liquid crystal layer interposed therebetween, To generate an electric field in the liquid crystal layer, thereby determining the orientation of the liquid crystal molecules in the liquid crystal layer and controlling the polarization of the incident light to display an image.

Among them, the vertical alignment mode liquid crystal display device in which the main directors of the liquid crystal molecules are arranged perpendicular to the upper and lower display panels in the state where the electric field is not applied has a great contrast ratio and is easy to implement a wide reference viewing angle. In order to solve such a problem, a liquid crystal display device of the vertical alignment type has a problem in that the side visibility is inferior to that of the front view. To solve this problem, a pixel is divided into a pair of sub- A method of forming a switching element and applying a separate voltage to each sub-pixel has been proposed.

However, in the liquid crystal display device according to the related art, since the movement of the liquid crystal located above the data line can not be precisely controlled by the electric field caused by the pixel electrode, light leakage occurs and the display characteristic of the liquid crystal display device is deteriorated .

Also, in the liquid crystal display device having such a structure, when the coupling capacitance between the sub-pixel electrode to which a relatively high data voltage is applied and the pair of data lines located on both sides thereof is inconsistent, display characteristics are degraded. Therefore, it is necessary to reduce the coupling capacitance between the sub-pixel and the neighboring data line.

SUMMARY OF THE INVENTION The present invention provides a liquid crystal display device capable of improving display quality.

The technical objects of the present invention are not limited to the technical matters mentioned above, and other technical subjects not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a liquid crystal display device including a first insulating substrate, a gate wiring formed on the first insulating substrate and extending in a first direction, And a first sub-pixel electrode and a second sub-pixel electrode to which a data voltage is applied from the data line, wherein at least part of the second sub-pixel electrode is connected to the data line And a pixel electrode overlapping the pixel electrode.

According to another aspect of the present invention, there is provided a liquid crystal display including a first insulating substrate, a gate wiring and a storage line formed on the first insulating substrate and extending in a first direction, First and second data lines which are insulated from each other and extend in a second direction and are separated from each other and first and second sub-pixel electrodes to which different data voltages are applied from the first and second data lines, At least a part of the second sub-pixel electrode includes a pixel electrode overlapping the data line, and an additional storage electrode connected to the storage line and extending substantially parallel to the first and second data lines .

The details of other embodiments are included in the detailed description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The dimensions and relative sizes of layers and regions in the figures may be exaggerated for clarity of illustration.

It is to be understood that when an element or layer is referred to as being "on" or " on "of another element or layer, All included. On the other hand, a device being referred to as "directly on" or "directly above " indicates that no other device or layer is interposed in between. Like reference numerals refer to like elements throughout the specification. "And / or" include each and every combination of one or more of the mentioned items.

The terms spatially relative, "below", "beneath", "lower", "above", "upper" May be used to easily describe a component or elements of the device or components and other devices or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation.

Embodiments described herein will be described with reference to plan views and cross-sectional views, which are ideal schematics of the present invention. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

Hereinafter, a liquid crystal display according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a pixel array of a liquid crystal display according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display of FIG.

A liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly, a gate driver and a data driver coupled to the liquid crystal panel assembly, a gradation voltage generator connected to the data driver, and a signal controller .

The liquid crystal panel assembly includes a plurality of display signal lines and a plurality of pixels PX connected to the display signal lines and arranged substantially in the form of a matrix. Here, the liquid crystal panel assembly includes a lower display panel and an upper display panel facing each other, and a liquid crystal layer interposed therebetween.

1 and 2, a display signal line is provided in a lower panel, and includes a plurality of gate lines G for transmitting gate signals and data lines Da and Db for transmitting data signals. The gate lines G extend in a substantially row direction and are substantially parallel to each other, and the data lines Da and Db extend in a substantially column direction and are substantially parallel to each other.

Each pixel PX includes a pair of subpixels PXa and PXb and each of the subpixels PXa and PXb is connected to a corresponding one of the data lines Da and Db and one gate line G, Devices Qa and Qb and liquid crystal capacitors Clca and Clcb connected thereto and storage capacitors Csta and Cstb connected thereto. That is, two data lines Da and Db and one gate line G are allocated to the pair of subpixels PXa and PXb. The storage capacitors Csta and Cstb may be omitted as needed.

The switching elements Qa and Qb of the respective subpixels PXa and PXb are formed of a thin film transistor or the like provided on a lower panel and are connected to a control terminal connected to a gate line G to which a gate signal is applied (Hereafter referred to as a source electrode) connected to the data lines Da and Db and an output terminal connected to the liquid crystal capacitors Clca and Clcb and the storage capacitors Csta and Cstb Drain electrode).

The liquid crystal capacitors Clca and Clcb have a common electrode of the sub-pixel electrode of the lower panel and the upper panel, and the liquid crystal layer between the sub-pixel electrode and the common electrode functions as a dielectric. Each of the sub-pixel electrodes Pa and Pb is connected to each of the switching elements Qa and Qb and a common electrode is formed on the entire surface of the upper panel to receive the common voltage Vcom. Here, the common electrode may be provided on the lower panel, and at this time, at least one of the sub-pixel electrode and the common electrode may be made linear or rod-shaped.

The storage capacitors Csta and Cstb serving as auxiliary capacitors of the liquid crystal capacitors Clca and Clcb are formed by overlapping the storage wiring lines and the sub pixel electrodes provided on the lower panel with an insulator interposed therebetween, A predetermined voltage is applied. Here, the storage capacitors Csta and Cstb may be formed by overlapping the sub-pixel electrode with the immediately preceding gate line via an insulator.

In order to realize the color display, each pixel uniquely displays one of the primary colors (space division), or displays each pixel three-color in alternation with time (time division) so that the spatial and temporal sum of these three primary colors So that the desired color is recognized. Examples of primary colors are red, green and blue. As an example of the spatial division, each pixel may have a color filter which indicates one of the primary colors in the region of the upper panel. The color filter may be formed on or below the sub-pixel electrode of the lower panel.

The gate driver is connected to the gate line G and applies a gate signal composed of a combination of the gate-on voltage Von and the gate-off voltage Voff from the outside to the gate line G. [

The gray voltage generator may generate two sets of gray scale voltages (or reference gray scale voltage sets) related to the transmittance of the pixels and provide them to the data driver. That is, the two sets of gradation voltages can be independently provided to a pair of sub-pixels constituting one pixel. However, the present invention is not limited to this, and one set of gradation voltages may be generated instead of two sets of gradation voltages.

The data driver is connected to the pair of data lines Da and Db, respectively. The data driver transmits a data voltage to one of the pair of sub-pixels constituting one pixel through the data line Da, and supplies the data voltage to the pair of pixels constituting one pixel through the data line Db And transmits a separate data voltage to the other one of the sub-pixels.

The gate driving unit or the data driving unit may be mounted directly on the liquid crystal panel assembly in the form of a plurality of driving integrated circuit chips or may be mounted on a flexible printed circuit film to form a liquid crystal panel in the form of a tape carrier package. Or may be attached to the panel assembly. Alternatively, the gate driver or the data driver may be integrated in the liquid crystal panel assembly together with the display signal lines G, Da, and Db and the thin film transistor switching elements Qa and Qb.

The signal control unit controls operations of the gate driver and the data driver.

Referring again to FIG. 1, one pixel includes two switching elements and sub-pixel electrodes Pa and Pb connected to the respective switching elements. Here, it is assumed that a relatively high data voltage is applied to the first sub-pixel electrode Pa and a relatively low data voltage is applied to the second sub-pixel electrode Pb. Hereinafter, the data voltage of high and low means that the difference between the common voltage and the data voltage is high and low. A pixel to which a data voltage is applied to the first sub-pixel electrode Pa through the first data line Da is referred to as an A-type pixel and a first sub-pixel electrode Pa is connected to the first sub- A pixel to which a data voltage is applied is referred to as a B-type pixel.

By alternately arranging the A-type pixel and the B-type pixel in the horizontal direction and the vertical direction as shown in Fig. 1, it is possible to prevent the vertical stripe or the horizontal stripe from being visually recognized in the liquid crystal display device.

If a data voltage is applied to the first sub-pixel electrode Pa through the first data line Da for all the pixels, that is, if the pixel array is made up of all the A-type pixels, the liquid crystal display device displays a column inversion the vertical stripes moving in the horizontal direction can be visually recognized with respect to the inspection pattern moving in the horizontal direction by one pixel per frame.

If a data voltage is applied to the first sub-pixel electrode Pa through the first data line Da and a second data line Db is applied to the pixel that forms the next pixel row with respect to one pixel row, When the data voltage is applied to the first sub-pixel electrode Pa, that is, when the rows of the A-type pixels and the rows of the B-type pixels are alternately arranged, the aforementioned vertical stripe moving in the horizontal direction is visible Can be prevented. The first sub-pixel electrode Pa and the first and second data lines Da and Db are coupled to each other. The first sub-pixel electrode Pa and the first and second data lines Da, Since the coupling capacitances of the data lines Da and Db depend on the A-type pixel and the B-type pixel, the horizontal stripes can be visually recognized.

Therefore, by arranging the A-type pixels and the B-type pixels alternately in the horizontal direction and the vertical direction as in the liquid crystal display device according to the embodiment of the present invention shown in FIG. 1, the above-mentioned vertical stripe or horizontal stripe Can be prevented. However, when the liquid crystal display device having such a structure operates at a low gray scale, since the liquid crystal substantially operates only by the first sub-pixel electrode Pa to which a relatively high data voltage is applied, By reducing the coupling capacitance between the first sub-pixel electrode Pa and the first data line Da and the coupling capacitance between the first sub-pixel electrode Pa and the second data line Db for each pixel, Deterioration of display quality due to crosstalk can be reduced.

The first and second data lines Da and Db may be arranged so as to overlap the second sub-pixel electrode Pb and the second sub-pixel electrode Pb may overlap the first sub-pixel electrode Pb, as in the embodiment of the present invention. The vertical line pattern or the horizontal line pattern can be prevented from being recognized unless the A-type pixel and the B-type pixel are alternately arranged in the horizontal direction and the vertical direction. That is, the coupling capacitance between the first and second data lines Da and Db and the first sub-pixel electrode Pa can be minimized, thereby preventing the display characteristics from being degraded. This will be described in detail later.

Hereinafter, a liquid crystal display according to an embodiment of the present invention will be described in detail with reference to FIGS. 3A to 5. FIG. The liquid crystal display according to the present embodiment includes a lower display panel on which a thin film transistor array is formed, a facing upper display panel, and a liquid crystal layer interposed therebetween.

3A to 3C, a lower panel of a liquid crystal display according to an embodiment of the present invention will be described in detail. 3A is a layout diagram of a lower panel including the A-type pixels of FIG. 1 according to an embodiment of the present invention, FIG. 3B is a cross-sectional view of the lower panel of FIG. 3A taken along lines IIIb-IIIb ' Sectional view taken along line IIIc-IIIc of FIG.

A gate line 22 extending mainly in the transverse direction and transmitting a gate signal is formed on the insulating substrate 10 made of transparent glass or the like. One gate line 22 is allocated to one pixel. A pair of protruding first and second gate electrodes 26a and 26b are formed in the gate line 22. [ The gate line 22 and the first and second gate electrodes 26a and 26b are referred to as gate wirings.

A storage line 28 is formed on the insulating substrate 10 in a lateral direction extending substantially parallel to the gate line 22 across the pixel region and connected to the storage line 28 to form a wide A storage electrode 27 having a width is formed. The storage electrode 27 overlaps the pixel electrode 82 to form a storage capacitor for improving the charge storage ability of the pixel. The storage electrode 27 and the storage line 28 are referred to as a storage line. In the present embodiment, the storage wirings 27 and 28 are formed so as to overlap with the center of the pixel region, but the present invention is not limited thereto. The shape and arrangement of the storage wirings 27 and 28 can be modified into various forms. Furthermore, when the storage capacitance generated by overlapping the pixel electrode 82 and the gate line 22 is sufficient, the storage lines 27 and 28 may not be formed.

The gate wirings 22, 26a and 26b and the storage wirings 27 and 28 are made of a metal such as aluminum (Al) and an aluminum alloy such as an aluminum alloy, a metal such as silver (Ag) Alloys and molybdenum metals such as molybdenum (Mo) and molybdenum alloys, chromium (Cr), titanium (Ti), tantalum (Ta) and the like. The gate wirings 22, 26a, 26b and the storage wirings 27, 28 may have a multi-film structure including two conductive films (not shown) having different physical properties. One of the conductive films is made of a metal having a low resistivity such as an aluminum-based metal, a silver-based metal, or the like so as to reduce signal delays and voltage drop of the gate wirings 22, 26a, 26b and the storage wirings 27, , Copper-based metals, and the like. Alternatively, the other conductive film may be made of a material having excellent contact properties with other materials, particularly ITO (indium tin oxide) and IZO (indium zinc oxide), such as molybdenum metal, chromium, titanium, tantalum and the like. A good example of such a combination is a chromium bottom film, an aluminum top film, an aluminum bottom film and a molybdenum top film. However, the present invention is not limited thereto, and the gate wirings 22, 26a, 26b and the storage wirings 27, 28 may be made of various metals and conductors.

A gate insulating film 30 made of silicon nitride (SiNx) or the like is formed on the gate line 22 and the storage wirings 27 and 28.

A pair of semiconductor layers 40a and 40b made of hydrogenated amorphous silicon, polycrystalline silicon, or the like is formed on the gate insulating film 30. The semiconductor layers 40a and 40b may have various shapes such as an island shape and a linear shape. For example, the semiconductor layers 40a and 40b may be formed in an island shape as in the present embodiment.

Ohmic contact layers 55a and 56a made of a material such as silicide or n + hydrogenated amorphous silicon doped with a high concentration of n-type impurities are formed on the upper portions of the semiconductor layers 40a and 40b have. The ohmic contact layers 55a and 56a are placed on the semiconductor layers 40a and 40b in pairs.

A pair of first and second data lines 62a and 62b and a pair of first and second data lines 62a and 62b respectively corresponding to the first and second data lines 62a and 62b are formed on the ohmic contact layers 55a and 56a and the gate insulating film 30, The first and second drain electrodes 66a and 66b are formed.

The first and second data lines 62a and 62b extend mainly in the longitudinal direction and intersect the gate line 22 and the storage line 28 to transfer the data voltage. First and second source electrodes 65a and 65b extending toward the first and second drain electrodes 66a and 66b are formed on the first and second data lines 62a and 62b, respectively. As shown in FIG. 3A, one pixel is divided into a pair of sub-pixels, the first data line 62a carries a data signal to one sub-pixel, and the second data line 62b carries a data signal to another sub- And transmits a separate data signal to the data bus.

The first and second data lines 62a and 62b and the first and second source electrodes 65a and 65b and the first and second drain electrodes 66a and 66b are referred to as a data line.

The data lines 62a, 62b, 65a, 65b, 66a, and 66b are preferably made of a refractory metal such as chromium, molybdenum based metal, tantalum and titanium, and may be formed of a lower film (not shown) Layer structure composed of a resistive material upper film (not shown). Examples of the multilayer structure include a triple layer of a molybdenum film-aluminum film-molybdenum film in addition to the chromium lower film and the aluminum upper film or the aluminum lower film and the molybdenum upper film.

The first and second source electrodes 65a and 65b are at least partially overlapped with the semiconductor layers 40a and 40b and the first and second drain electrodes 66a and 66b are connected to the gate electrodes 26a and 26b, The semiconductor layers 40a and 40b and the first and second source electrodes 65a and 65b are overlapped with each other. The ohmic contact layers 55a and 56a are formed on the lower semiconductor layers 40a and 40b and the first and second source electrodes 65a and 65b and the first and second drain electrodes 66a, 66b and serves to lower the contact resistance.

A passivation layer 70 is formed on the data lines 62a, 62b, 65a, 65b, 66a, and 66b and the exposed semiconductor layers 40a and 40b. The protective layer 70 may be formed of a material selected from the group consisting of an inorganic material consisting of silicon nitride or silicon oxide, an organic material having excellent planarization property and photosensitivity, or an a-Si: C: O material formed by plasma enhanced chemical vapor deposition (PECVD) and a low dielectric constant insulating material such as a-Si: O: F. The protective layer 70 may have a bilayer structure of a lower inorganic layer and an upper organic layer to protect the exposed semiconductor layers 40a and 40b while making good use of the organic layer. Further, as the protective film 70, a color filter layer of red, green or blue may be used.

The passivation layer 70 is electrically connected to the first and second drain electrodes 66a and 66b through first and second contact holes 76a and 76b, And second sub-pixel electrodes 82a and 82b are formed. Here, the first and second sub-pixel electrodes 82a and 82b are made of a transparent conductor such as ITO or IZO or a reflective conductor such as aluminum.

The first and second sub-pixel electrodes 82a and 82b are physically and electrically connected to the first and second drain electrodes 66a and 66b through the first and second contact holes 76a and 76b, And the second drain electrodes 66a and 66b.

The first and second sub-pixel electrodes 82a and 82b to which the data voltage is applied generate an electric field together with the common electrode of the upper panel, thereby forming a liquid crystal molecule between the first and second sub-pixel electrodes 82a and 82b and the common electrode Lt; / RTI >

2 and 3A, each of the sub-pixel electrodes 82a and 82b and the common electrode constitutes a liquid crystal capacitor Clca and Clcb, so that even after the thin film transistors Qa and Qb are turned off, And the storage capacitors Csta and Cstb connected in parallel with the liquid crystal capacitors Clca and Clcb are connected to the first and second sub-pixel electrodes 82a and 82b or the first and second sub- And the second drain electrodes 66a and 66b and the storage wirings 27 and 28, respectively.

Referring again to FIGS. 3A to 3C, one pixel electrode 82 is electrically coupled to the first and second sub-pixel electrodes 82a and 82b via a predetermined gap 83, ). The first sub-pixel electrode 82a has a substantially V-shaped configuration and the second sub-pixel electrode 82b is formed in an area other than the first sub-pixel electrode 82a in the pixel. Specifically, the second sub-pixel electrode 82b is formed to surround the first sub-pixel electrode 82a.

The gap 83 includes a sloped portion forming approximately 45 degrees or -45 degrees with the gate line 22 and a vertical portion connecting between the sloped portions and arranged along the first and second data lines 62a and 62b do.

Although not shown, the first sub-pixel electrode 82a and the second sub-pixel electrode 82b may be provided with domain dividing means (not shown) forming an angle of about 45 degrees or -45 degrees with the gate line 22, for example, a cutout or a protrusion may be formed. The display region of the pixel electrode 82 is divided into a plurality of domains in accordance with the direction in which the main direction of the liquid crystal molecules included in the liquid crystal layer is arranged when the electric field is applied. The gap 83 and the domain dividing means serve to divide the pixel electrode 82 into many domains. Here, the term " domain " means a region consisting of liquid crystal molecules in which the director of the liquid crystal molecules is inclined in a specific direction by an electric field formed between the pixel electrode 82 and the common electrode (see reference numeral 90 in Fig. 4).

As described above, the first sub-pixel electrode 82a has a V-shape as a whole, and the second sub-pixel electrode 82b is formed to surround the first sub-pixel electrode 82a. Specifically, the second sub-pixel electrode 82b includes a main region adjacent to the shaded portion of the gap 83 and having an overall angle of about 45 degrees or -45 degrees with respect to the gate line 22 and controlling the movement of liquid crystal molecules, And a bridge region adjacent to the vertical portion of the first data line 83 and arranged along the first and second data lines 62a and 62b to connect the main regions.

As shown in FIGS. 3A and 3C, the first and second data lines 62a and 62b are formed to overlap at least part of the second sub-pixel electrode 82b. Preferably, the first and second data lines 62a and 62b are formed so as to completely overlap the second sub-pixel electrode 82b in the width direction. Specifically, the first and second data lines 62a and 62b overlap the bridge region of the second sub-pixel electrode 82b.

An alignment film (not shown) capable of aligning the liquid crystal layer can be applied on the first and second sub-pixel electrodes 82a and 82b and the protective film 70. [

Next, the upper panel and the liquid crystal display will be described with reference to FIGS. 4 and 5. FIG. FIG. 4 is a layout diagram of an upper panel coupled to the lower panel of FIG. 3a, and FIG. 5 is a layout diagram of a liquid crystal display including the lower panel of FIG. 3a and the upper panel of FIG.

A black matrix 94 for preventing light leakage and defining pixel regions is formed on an insulating substrate (not shown) made of transparent glass or the like. The black matrix 94 may be formed at portions corresponding to the gate lines 22 and the first and second data lines 62a and 62b and portions corresponding to the thin film transistors. In addition, the black matrix 94 may have various shapes to shield the first and second sub-pixel electrodes 82a and 82b and the light leakage in the vicinity of the thin film transistor. The black matrix 94 may be formed of a metal (metal oxide) such as chromium or chromium oxide, or an organic black resist.

And red, green, and blue color filters (not shown) may be sequentially arranged in the pixel region between the red, green, and blue matrices.

On the color filter, an overcoat layer (not shown) may be formed for planarizing the stepped portions.

On the overcoat layer, a common electrode 90 made of a transparent conductive material such as ITO or IZO is formed. The common electrode 90 faces the first and second sub-pixel electrodes 82a and 82b and includes a domain dividing means 92 which forms about 45 degrees or -45 degrees with respect to the gate line 22, Or protrusions.

On the common electrode 90, an alignment film (not shown) for aligning the liquid crystal molecules can be applied.

A liquid crystal display device according to an embodiment of the present invention is constructed by aligning and bonding a lower display panel and an upper display panel having such a structure and vertically aligning liquid crystal material therebetween.

The liquid crystal molecules included in the liquid crystal layer are oriented such that the director is perpendicular to the lower display panel and the upper display panel in a state in which no electric field is applied between the pixel electrode 82 and the common electrode 90, And has a negative dielectric constant anisotropy.

The liquid crystal display device is constituted by arranging elements such as a polarizing plate and a backlight in the basic structure. At this time, one polarizing plate is disposed on each side of the basic structure, and the transmission axis thereof is arranged such that one of the polarizing plates is parallel to the gate line 22 and the other is perpendicular thereto.

An electric field perpendicular to the two display panels is formed in most areas when the electric field is applied between the lower display panel and the upper display panel. However, in the vicinity of the domain dividing means 92 of the gap 83 and the common electrode 90 of the pixel electrode 82, An electric field is formed. These horizontal electric fields help to orient the liquid crystal molecules in each domain.

Since the liquid crystal molecules of this embodiment have negative dielectric anisotropy, when an electric field is applied to the liquid crystal molecules, the liquid crystal molecules in each domain are aligned in a direction perpendicular to the gap 83 or the domain dividing means 92, . The inclined direction of the liquid crystal molecules is reversed at both sides of the gap 83 or the domain dividing means 92 so that the shaded portion of the gap 83 or the shaded portion of the domain dividing means 92 is symmetrical The liquid crystal molecules are inclined in four directions substantially at 45 or -45 degrees with respect to the gate line 22. The optical characteristics are compensated for by the liquid crystal molecules inclined in the four directions as described above, thereby widening the viewing angle.

Hereinafter, the operation of the liquid crystal display device according to one embodiment of the present invention will be described in detail with reference to FIGS. 3A to 5. FIG.

A relatively high data voltage is applied to the first sub-pixel electrode 82a connected to the first data line 62a and a relatively low data voltage is applied to the second sub-pixel electrode 82b connected to the second data line 62b. The lateral visibility of the liquid crystal display device can be improved.

In particular, when the liquid crystal display device operates at a low gray level, the liquid crystal substantially operates only by the first sub-pixel electrode 82a to which a relatively high data voltage is applied and the voltage is not applied to the second sub-pixel electrode 82b Do not. In this case, since substantially the same voltage is applied to the second sub-pixel electrode 82b as the common electrode 90 of the upper display panel, the liquid crystal molecules disposed on the second sub-pixel electrode 82b are aligned with respect to the lower display panel And is oriented to be perpendicular. Therefore, the light emitted from the backlight is shielded without passing through the second sub-pixel electrode 82b.

When the liquid crystal display device operates in a high gradation, the overall luminance of the liquid crystal display device is high, so that light leakage phenomenon is not a big problem. Therefore, it is important to prevent the light leakage phenomenon when the liquid crystal display device operates at a low gradation. Generally, a light leakage phenomenon occurs around the first and second data lines 62a and 62b. However, in the case where the second sub-pixel electrode 82b is arranged to overlap with the first and second data lines 62a and 62b and the liquid crystal display device is operated at a low gray scale as in the embodiment of the present invention, Light passing through the pixel electrode 82b is shielded, so that light leakage occurring around the first and second data lines 62a and 62b can be prevented. In addition, since the light leakage phenomenon is prevented by using the second sub-pixel electrode 82b surrounding the first sub-pixel electrode 82a without enlarging the area of the black matrix 94 of the upper panel, the aperture can be increased.

The display characteristics of the liquid crystal display device may be degraded if the coupling capacitances of the first and second data lines 62a and 62b are different from each other in the first sub-pixel electrode 82a to which a relatively high voltage is applied. Accordingly, the first sub-pixel electrode 82a and the first and second data lines 62a and 62b are disposed so as not to overlap the first and second data lines 62a and 62b, It is possible to prevent such coupling capacitance from affecting the display characteristic of the liquid crystal display device.

Hereinafter, a lower panel of a liquid crystal display according to an embodiment of the present invention will be described in detail with reference to FIG. 6 is a layout diagram of a lower panel including the B-type pixel of FIG. 1 according to an embodiment of the present invention. For convenience of explanation, members having the same functions as the members shown in the drawings of the previous embodiment (Figs. 3A to 5) are denoted by the same reference numerals and description thereof is omitted, and the differences will be mainly described below.

6, the first drain electrode 66a is connected to the second sub-pixel electrode 82b through the first contact hole 76a, and the second drain electrode 66b is connected to the second contact hole 82b through the first contact hole 76a. And the first sub-pixel electrode 82a through the second sub-pixel electrode 76b. A relatively high data voltage is applied to the first sub-pixel electrode 82a connected to the second data line 62b and a relatively low data voltage is applied to the second sub-pixel electrode 82b connected to the first data line 62a. The lateral visibility of the liquid crystal display device can be improved.

In the case of the liquid crystal display device having such a structure, light leakage phenomenon occurring around the first and second data lines 62a and 62b can be prevented, and the aperture ratio of the liquid crystal display device can be increased. Also, by reducing the coupling capacitance between the first sub-pixel electrode 82a and the first and second data lines 62a and 62b, the display characteristics of the liquid crystal display device can be prevented from being degraded.

Hereinafter, a lower panel of a liquid crystal display according to another embodiment of the present invention will be described in detail with reference to FIGS. 7A and 7B. FIG. 7A is a layout view of a lower panel including the A-type pixel of FIG. 1 according to another embodiment of the present invention, and FIG. 7B is a cross-sectional view of the lower panel of FIG. 7A taken along lines VIIb-VIIb '. For convenience of explanation, members having the same functions as the members shown in the drawings of the previous embodiment (Figs. 3A to 5) are denoted by the same reference numerals and description thereof is omitted, and the differences will be mainly described below.

7A and 7B, in order to further reduce the coupling capacitance between the first sub-pixel electrode 82a and the first and second data lines 62a and 62b, First and second additional storage electrodes 29a and 29b extending in the longitudinal direction are formed substantially parallel to the first and second data lines 62a and 62b.

The first and second additional storage electrodes 29a and 29b may partially overlap the gap 83 that separates the first sub-pixel electrode 82a and the second sub-pixel electrode 82b. Here, the gap 83 includes a sloped portion forming approximately 45 degrees or -45 degrees with the gate line 22 and a vertical portion connecting between the sloped portions and arranged along the first and second data lines 62a and 62b do. Accordingly, it is preferable that the first and second additional storage electrodes 29a and 29b are partially overlapped with the vertical portions of the gap 83 adjacent to the first and second data lines 62a and 62b.

The first and second additional storage electrodes 29a and 29b and the first sub-pixel electrode 82a form storage capacitors so that the first sub-pixel electrode 82a is connected to the first and second data lines 82a and 82b, (62a, 62b).

Further, as shown in FIG. 7B, when at least a part of the first and second additional storage electrodes 29a and 29b overlap with the first sub-pixel electrode 82a, 1 and the second data lines 62a and 62b can be further reduced. The width L of overlapping the first and second additional storage electrodes 29a and 29b and the first sub-pixel electrode 82a may be, for example, about 1 to 3 mu m.

Hereinafter, a lower panel of a liquid crystal display according to another embodiment of the present invention will be described in detail with reference to FIG. Here, FIG. 8 is a layout diagram of a lower panel including the B-type pixel of FIG. 1 according to another embodiment of the present invention. For convenience of explanation, the members having the same functions as the members shown in the drawings of the previous embodiment (Figs. 7A to 7B) are denoted by the same reference numerals and the description thereof will be omitted, and the differences will be mainly described below.

8, the first drain electrode 66a is connected to the second sub-pixel electrode 82b through the first contact hole 76a, and the second drain electrode 66b is connected to the second contact hole 82b And the first sub-pixel electrode 82a through the second sub-pixel electrode 76b. A relatively high data voltage is applied to the first sub-pixel electrode 82a connected to the second data line 62b and a relatively low data voltage is applied to the second sub-pixel electrode 82b connected to the first data line 62a. The lateral visibility of the liquid crystal display device can be improved.

In the case of the liquid crystal display device having such a structure, light leakage phenomenon occurring around the first and second data lines 62a and 62b can be prevented, and the aperture ratio of the liquid crystal display device can be increased. Also, the coupling capacitance between the first sub-pixel electrode 82a and the first and second data lines 62a and 62b can be more effectively reduced, thereby preventing the display characteristics of the liquid crystal display device from being deteriorated.

Hereinafter, the coupling capacitors between the sub-pixel electrodes and the data lines in the liquid crystal display device according to the embodiments of the present invention will be described with reference to FIGS. 1, 9A, and 9B. It is desirable to increase the frequency of the input image signal and to increase the response speed of the liquid crystal molecules in order to improve the afterimage and the screen dragging phenomenon occurring when the moving image is reproduced in the liquid crystal display device. For example, in the case of a liquid crystal display device operating at a high frequency of 120 Hz or more, it is preferable to drive by column inversion rather than dot inversion in consideration of the response speed of liquid crystal molecules. Hereinafter, the coupling capacitance between the sub-pixel electrode and the data line will be described in detail with reference to a liquid crystal display device driven by column inversion. In the liquid crystal display according to the column inversion driving, in the first frame, the positive data voltage is applied to the first data line Da and the negative data voltage is applied to the second data line Db (here, Negative polarity refers to the polarity of the data voltage relative to the common voltage). In the second frame, a negative data voltage is applied to the first data line Da and a positive data voltage is applied to the second data line Db.

First, the coupling capacitance between the first sub-pixel electrode Pa and the data lines Da and Db to which a relatively high data voltage is applied will be described with reference to FIGS. 1 and 9A. FIG. 9A is a graph showing the difference in luminance between the first sub-pixel electrode Pa of the A-type pixel and the first sub-pixel electrode Pa of the B-type pixel in FIG. 1 as the gradation is changed. Since the first sub-pixel electrode Pa of the A-type and B-type pixels has a wider area adjacent to the first data line Da than the second data line Db, the first sub- And the coupling capacitance between the first data line (Da) and the first data line (Da) plays a major role in the luminance change of the liquid crystal display device. Further, since the first sub-pixel electrode Pa always has a high luminance at a high gradation, a change in the luminance difference occurs at a low gradation.

In the case of the A-type pixel, the positive data voltage is applied to the first sub-pixel electrode Pa through the first data line Da in the first frame. During the second frame, the first data line Da is supplied with the negative data voltage. Therefore, before the data voltage is applied to the first sub-pixel electrode Pa in the second frame, the first sub-pixel electrode Pa is coupled to the first data line Da, Lt; RTI ID = 0.0 > Pa. ≪ / RTI > Therefore, the brightness of the first sub-pixel electrode Pa is reduced.

In the case of the B type pixel, the negative data voltage is applied to the first sub-pixel electrode Pa through the second data line Db in the first frame. During the second frame, the first data line Da is supplied with the negative data voltage. Therefore, before the data voltage is applied to the first sub-pixel electrode Pa in the second frame, the first sub-pixel electrode Pa is coupled to the first data line Da, Pa is larger. Accordingly, the brightness of the first sub-pixel electrode Pa is increased.

The luminance difference data of FIG. 9A is obtained by subtracting the luminance RMS (root-mean-square) value of the first sub-pixel electrode Pa of the A-type pixel for the first and second frames from the luminance Represents the difference in the luminance RMS value of the pixel electrode Pa. As shown in FIG. 9A, although there is a luminance difference between the A-type and B-type pixels for the first sub-pixel electrode Pa at a low gradation level, the difference in luminance is small at about 1.5% or less. This indicates that the coupling capacitance between the first sub-pixel electrode Pa and the first and second data lines Pa and Pb is significantly reduced.

Next, the coupling capacitance between the second sub-pixel electrode Pb and the data lines Da and Db to which a relatively low data voltage is applied will be described with reference to FIGS. 1 and 9B. 9B is a graph showing the difference in luminance between the second sub-pixel electrode Pb of the A-type pixel and the second sub-pixel electrode Pb of the B-type pixel of FIG. 1 according to the change of the gradation. Since the second sub-pixel electrode Pb of the A-type and B-type pixels has a larger area overlapping the first data line Da than the second data line Db, the second sub-pixel electrode Pb And the coupling capacitance between the first data line Da and the first data line Da play a major role in the luminance change of the liquid crystal display device. In addition, the second sub-pixel electrode Pb does not operate at a low gray level but operates at a high gray level, so that a change in the brightness difference occurs at a high gray level.

In the case of the A-type pixel, the negative data voltage is applied to the second sub-pixel electrode Pb through the second data line Db in the first frame. During the second frame, the first data line Da is supplied with the negative data voltage. Accordingly, before the data voltage is applied to the second sub-pixel electrode Pb in the second frame, the second sub-pixel electrode Pb is coupled to the first data line Da, The magnitude of the data voltage stored in Pb becomes larger. Accordingly, the brightness of the second sub-pixel electrode Pb is increased.

In the case of the B-type pixel, the positive data voltage is applied to the second sub-pixel electrode Pb through the first data line Da in the first frame. During the second frame, the first data line Da is supplied with the negative data voltage. Accordingly, before the data voltage is applied to the second sub-pixel electrode Pb in the second frame, the second sub-pixel electrode Pb is coupled to the first data line Da, The magnitude of the data voltage stored in Pb becomes smaller. Accordingly, the brightness of the second sub-pixel electrode Pb is reduced.

The luminance difference data in FIG. 9B is obtained by subtracting the luminance RMS (root-mean-square) value of the second sub-pixel electrode Pb of the A-type pixel for the first and second frames from the second portion of the B- Represents the difference in the luminance RMS value of the pixel electrode Pb. As shown in Fig. 9B, although there is a luminance difference between the A-type and B-type pixels for the second sub-pixel electrode Pb at a high gradation level, the difference in luminance is not more than about 2.5%. This is because even if the second sub-pixel electrode Pb overlaps the first and second data lines Pa and Pb, the coupling capacitances of the second sub-pixel electrode Pb and the first and second data lines Pa and Pb Is small.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

As described above, according to the liquid crystal display device of the present invention, it is possible to prevent the light leakage phenomenon occurring around the data line and to increase the aperture ratio. Also, by reducing the coupling capacitance between the first sub-pixel electrode and the first and second data lines, it is possible to prevent the display characteristics of the liquid crystal display from being deteriorated.

Claims (26)

A first insulating substrate; A gate wiring formed on the first insulating substrate and extending in a first direction; A data line which is insulated from the gate line and extends in a second direction; And A pixel electrode including first and second sub-pixel electrodes; / RTI > At least a part of the second sub-pixel electrode overlaps with the data line, The first sub-pixel electrode does not overlap the data line, Wherein the data line includes first and second data lines for providing different data voltages to the first and second sub-pixel electrodes, respectively, A first type pixel to which a data voltage is applied to the first sub-pixel electrode from the first data line and a second type pixel to which a data voltage is applied from the second data line to the first sub- Direction and the second direction. The method according to claim 1, Wherein a relatively high data voltage is applied to the first sub-pixel electrode and a relatively low data voltage is applied to the second sub-pixel electrode. The method according to claim 1, And the data line completely overlaps with the second sub-pixel electrode in the width direction. The method according to claim 1, And the second sub-pixel electrode is configured to surround the first sub-pixel electrode. The method according to claim 1, The first sub-pixel electrode has a V-shape, and the second sub-pixel electrode is formed in a region other than the first sub-pixel electrode in the pixel. 5. The method of claim 4, Wherein the second sub-pixel electrode comprises a main region substantially at 45 degrees or -45 degrees to the gate line, and a bridge region arranged along the data line and connecting the main regions, And the data line overlaps with the bridge region. delete delete delete delete delete delete delete The method according to claim 1, A second insulating substrate facing the first insulating substrate; A common electrode formed on the second insulating substrate; And And a liquid crystal layer interposed between the first and second insulating substrates and made of liquid crystal molecules having a negative dielectric constant anisotropy. A first insulating substrate; Gate lines and storage lines formed on the first insulating substrate and extending in a first direction; First and second data lines which are insulated from and intersect with the gate lines and extend in a second direction; A pixel electrode including first and second sub-pixel electrodes; An additional storage electrode coupled to the storage line and extending substantially parallel to the first and second data lines; / RTI > At least a part of the second sub-pixel electrode overlaps with the first and second data lines, The first sub-pixel electrode does not overlap the first and second data lines, Wherein the first and second data lines provide different data voltages to the first and second sub-pixel electrodes, respectively, A first type pixel to which a data voltage is applied to the first sub-pixel electrode from the first data line and a second type pixel to which a data voltage is applied from the second data line to the first sub- Direction and the second direction. 16. The method of claim 15, Wherein a relatively high data voltage is applied to the first sub-pixel electrode and a relatively low data voltage is applied to the second sub-pixel electrode. 16. The method of claim 15, And the first and second data lines completely overlap the second sub-pixel electrode in the width direction. 16. The method of claim 15, And the second sub-pixel electrode is configured to surround the first sub-pixel electrode. 19. The method of claim 18, The first sub-pixel electrode has a V-shape, and the second sub-pixel electrode is formed in an area other than the first sub-pixel electrode in the pixel. 19. The method of claim 18, Wherein the second sub-pixel electrode comprises a main region substantially at 45 degrees or -45 degrees to the gate line, and a bridge region arranged along the first or second data line to connect the main regions, Wherein the first and second data lines overlap the bridge region. delete delete 16. The method of claim 15, Wherein the additional storage electrode partially overlaps a gap separating the first and second sub-pixel electrodes. 24. The method of claim 23, Wherein at least a portion of the additional storage electrode overlaps with the first sub-pixel electrode. 25. The method of claim 24, And the overlap width of the additional storage electrode and the first sub-pixel electrode is 1 to 3 占 퐉. 16. The method of claim 15, A second insulating substrate facing the first insulating substrate; A common electrode formed on the second insulating substrate; And And a liquid crystal layer interposed between the first and second insulating substrates and made of liquid crystal molecules having a negative dielectric constant anisotropy.

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