CN101109880B - LCD device and method thereof - Google Patents

Abstract

The invention provides a liquid crystal display (LCD) to increase the display quality, comprising: a first insulated base plate; grid layout formed above the first insulated base plate and extending along a first direction; data layout insulated and crossed with grid layout and extending along a second direction; and pixel electrode comprising a first and second sub pixel electrode from different data voltages wherein at least one part of the second pixel electrode overlaps with the data layout.

Description

Liquid crystal display and method thereof

Technical Field

The present invention relates to a Liquid Crystal Display (LCD) and a method thereof, and more particularly, to an LCD having improved display quality, and a method of improving the display quality of the LCD.

Background

A Liquid Crystal Display (LCD) has been widely used as one of flat panel displays. The LCD includes two display panels on which field generating electrodes (field generating electrodes) such as pixel electrodes and a common electrode are formed, with a liquid crystal layer interposed therebetween. In the LCD, a voltage is applied to the field generating electrodes to generate an electric field in the liquid crystal layer, and the arrangement of liquid crystal molecules of the liquid crystal layer is determined by the electric field. Accordingly, the polarization of incident light is controlled, thereby performing image display.

Among LCDs, a Vertical Alignment (VA) mode LCD, in which main directors (directors) of liquid crystal molecules are perpendicular to upper and lower display panels without applying an electric field, is spotlighted because it has a high contrast ratio and a wide viewing angle. However, the VA mode LCD has a problem in that side visibility is lower than front visibility. To solve this problem, a method has been proposed which: dividing a pixel into a pair of sub-pixels, forming switching elements in the individual sub-pixels, and applying different voltages to the sub-pixels.

However, in such an LCD according to the related art, since the movement of liquid crystal located above the data line cannot be precisely controlled due to an electric field between the pixel electrodes, light leakage occurs, which may result in a reduction in display performance of the LCD.

In addition, in the LCD having the above-described structure, when coupling capacitances between the sub-pixel electrode to which a higher data voltage is applied and a pair of data lines disposed on both sides of the sub-pixel are not identical to each other, display characteristics are degraded.

Disclosure of Invention

The present invention relates to a Liquid Crystal Display (LCD) capable of improving display quality. Display quality can be improved by reducing coupling capacitance between the data lines of the sub-pixels and the neighboring sub-pixels.

The invention also provides a method for improving the display quality of the LCD.

According to an exemplary embodiment of the present invention, an LCD includes: a first insulating substrate; a gate wiring formed on the first insulating substrate and extending in a first direction; a data wire insulated from and crossing the gate wire and extending in a second direction; and pixel electrodes each including first and second sub-pixel electrodes to which different data voltages are applied from the data wiring, wherein at least a portion of each of the second sub-pixel electrodes overlaps the data wiring.

According to other exemplary embodiments of the present invention, an LCD includes: gate and data wirings insulated from each other and crossing each other on the insulating substrate; a pair of first and second Thin Film Transistors (TFTs) connected to the gate wiring and the data wiring; a first subpixel electrode connected to the first TFT; a second subpixel electrode surrounding the first subpixel electrode, separated from the first subpixel electrode by a gap, and connected to the second TFT; a first storage line overlapping the first subpixel electrode and receiving a first storage voltage; and a second storage line overlapping the second sub-pixel electrode and receiving a second storage voltage different from the first storage voltage.

According to still other exemplary embodiments of the present invention, an LCD includes: a gate line; a pair of data lines insulated from and crossing the gate lines; and a pixel electrode electrically connected to the gate line and the pair of data lines. Here, each of the pixel electrodes includes a first sub-pixel electrode and a second sub-pixel electrode, the second sub-pixel electrode has a smaller area than the first sub-pixel electrode, and the first sub-pixel electrode overlaps the pair of data lines.

According to still further exemplary embodiments of the present invention, a method of improving display quality of an LCD having a matrix of pixel areas includes: forming a gate wiring on the insulating substrate, the gate wiring extending substantially in a first direction; forming a data wire insulated from the gate wire, the data wire extending substantially in a second direction, the second direction being substantially perpendicular to the first direction; forming first and second sub-pixel electrodes in each pixel region such that the second sub-pixel electrode overlaps an adjacent data wiring in each pixel region, the second sub-pixel electrode at least partially surrounding the first sub-pixel electrode and having an area larger than the first sub-pixel electrode; and applying a data voltage to the first subpixel electrode, the data voltage being greater than the data voltage applied to the second subpixel electrode.

Drawings

The above and other features and advantages of the present invention will become more apparent from the following detailed description of exemplary embodiments thereof, taken in conjunction with the accompanying drawings, in which:

fig. 1 is a schematic diagram illustrating an exemplary pixel array of an exemplary Liquid Crystal Display (LCD) according to a first exemplary embodiment of the present invention;

FIG. 2 is an equivalent circuit diagram of an exemplary pixel in the exemplary LCD of FIG. 1;

FIG. 3A is a layout diagram of an exemplary lower display panel including the exemplary A-type pixel of FIG. 1 according to a first exemplary embodiment of the present invention;

FIG. 3B is a cross-sectional view of the exemplary lower display panel taken along line IIIB-IIIB' of FIG. 3A;

FIG. 3C is a cross-sectional view of the exemplary lower display panel taken along line IIIC-IIIC' of FIG. 3A;

FIG. 4 is a layout view of an exemplary upper display panel coupled to the exemplary lower display panel of FIG. 3A;

FIG. 5 is a layout view of an exemplary LCD incorporating the exemplary lower display panel of FIG. 3A and the exemplary upper display panel of FIG. 4;

fig. 6 is a layout view of an exemplary lower display panel including the exemplary B-type pixel of fig. 1 according to a first exemplary embodiment of the present invention;

FIG. 7A is a layout diagram of an exemplary lower display panel including the exemplary A-type pixel of FIG. 1 according to a second exemplary embodiment of the present invention;

FIG. 7B is a cross-sectional view of the exemplary lower display panel taken along line VIIB-VIIB' of FIG. 7A;

fig. 8 is a layout view of an exemplary lower display panel including the exemplary B-type pixel of fig. 1 according to a second exemplary embodiment of the present invention;

fig. 9A is a graph illustrating a luminance difference between the first subpixel electrode Pa of the exemplary a-type pixel of fig. 1 and the first subpixel electrode Pa of the exemplary B-type pixel when a gray scale level is changed;

fig. 9B is a graph illustrating a luminance difference between the second sub-pixel electrode Pb of the exemplary a-type pixel of fig. 1 and the second sub-pixel electrode Pb of the exemplary B-type pixel when a gray level is changed;

fig. 10 is an equivalent circuit diagram of an exemplary pixel in an exemplary LCD according to a third exemplary embodiment of the present invention;

fig. 11A is a layout view of an exemplary lower display panel of an exemplary LCD according to a third exemplary embodiment of the present invention;

FIG. 11B is a cross-sectional view of the exemplary lower display panel taken along line XIB-XIB' of FIG. 11A;

FIG. 11C is a cross-sectional view of the exemplary lower display panel taken along line XIC-XIC' of FIG. 11A;

fig. 12A is a layout view of an exemplary lower display panel of an exemplary LCD according to a fourth exemplary embodiment of the present invention;

FIG. 12B is a cross-sectional view of the exemplary lower display panel taken along line XIIB-XIIB' of FIG. 12A;

fig. 13 is a view illustrating a portion of an exemplary lower display panel of an exemplary LCD according to a fifth exemplary embodiment of the present invention;

fig. 14 is a layout diagram showing in detail the structure of one exemplary pixel electrode PX shown in fig. 13;

fig. 15 is a block diagram illustrating an exemplary LCD to which the exemplary lower display panel illustrated in fig. 13 is applied; and

fig. 16 is a waveform diagram of data voltages applied to each exemplary pixel electrode to implement an image pattern including a white pattern and a gray pattern.

Detailed Description

Advantages and features of the present invention and methods of accomplishing the same may be understood more readily by reference to the following detailed description of preferred embodiments and the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art, and the present invention will only be defined by the appended claims. The dimensions of the layers or regions in the figures may be exaggerated for clarity of illustration.

It will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. Like numbers refer to like elements throughout. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed terms.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

Terms such as "below," "beneath," "above," and the like may be used to readily describe one element, component, other element, or the positional relationship between components as illustrated in the figures. It is to be understood that such terms are intended to encompass not only the orientation shown in the figures, but also other orientations of the elements during use or operation.

Preferred embodiments of the present invention will be described below with reference to plan and cross-sectional views as exemplary drawings of the present invention. The exemplary drawings may be modified by manufacturing techniques and/or tolerances. Accordingly, the preferred embodiments of the present invention are not limited to the specific structures shown in the drawings, but include modifications based on manufacturing processes. Thus, the regions illustrated in the drawings have schematic characteristics. In addition, the shapes of the regions illustrated in the drawings are merely illustrative of specific shapes of regions in a device and do not limit the present invention.

Hereinafter, a Liquid Crystal Display (LCD) according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 1 is a schematic diagram illustrating an exemplary pixel array of an exemplary LCD according to a first exemplary embodiment of the present invention. Fig. 2 is an equivalent circuit diagram illustrating one exemplary pixel in the exemplary LCD of fig. 1.

The LCD of fig. 1 and 2 includes: a liquid crystal panel assembly (assembly); a gate driver and a data driver connected to the liquid crystal panel assembly; a gray voltage generator connected to the data driver; and a signal controller for controlling them.

The liquid crystal panel assembly includes a plurality of display signal lines and a plurality of pixels PX connected to the display signal lines and arranged substantially in a matrix shape. Here, the liquid crystal panel assembly includes a lower display panel and an upper display panel facing each other and a liquid crystal layer interposed between the lower and upper display panels.

Referring to fig. 1 and 2, the display signal lines are disposed on the lower display panel and include a plurality of gate lines G transmitting gate signals and data lines Da, Db transmitting data signals. The gate lines G extend substantially parallel to each other in a row direction (first direction). The data lines Da and Db extend substantially parallel to each other in the column direction (second direction). Wherein the first direction is substantially perpendicular to the second direction.

Each pixel PX includes a pair of subpixels PXa and PXb. The sub-pixels PXa and PXb respectively include: switching elements Qa, Qb connected to the corresponding data lines Da, Db and one gate line G; liquid crystal capacitors Clca and Clcb connected to the switching elements Qa and Qb, respectively; and a pair of storage capacitors Csta, Cstb connected to the liquid crystal capacitors Clca, Clcb, respectively. That is, two data lines Da, Db and one gate line G are allocated to a pair of sub-pixels PXa, PXb. In an alternative embodiment, the storage capacitors Csta, Cstb may not be included, if necessary.

The switching elements Qa and Qb of the respective sub-pixels PXa and PXb have Thin Film Transistors (TFTs) disposed on the lower display panel. Each of the switching elements Qa and Qb is a three-terminal element including: a control terminal (hereinafter, referred to as a "gate electrode") connected to the gate line G to which the gate signal is applied; an input terminal (hereinafter, referred to as a "source electrode") connected to each of the respective data lines Da and Db; and an output terminal (hereinafter, referred to as "drain electrode") connected to each of the respective liquid crystal capacitors Clca and Clcb and each of the respective storage capacitors Csta and Cstb.

Each of the liquid crystal capacitors Clca and Clcb has two terminals including sub-pixel electrodes Pa and Pb of the lower display panel and a common electrode of the upper display panel, and a liquid crystal layer interposed between the sub-pixel electrodes Pa, Pb and the common electrode serves as a dielectric. The sub-pixel electrodes Pa and Pb are connected to the switching elements Qa and Qb, respectively. The common electrode is formed on the entire surface or substantially the entire surface of the upper display panel and is applied with a common voltage Vcom. Alternatively, the common electrode may be disposed on the lower display panel. In this case, at least one of the pixel electrode and the common electrode may be formed in a line shape or a bar shape.

The sub-pixel electrodes and the storage wiring lines disposed on the lower display panel may overlap each other with an insulating material interposed therebetween, thereby forming storage capacitors Csta, Cstb that assist the liquid crystal capacitors Clca, Clcb. A predetermined voltage such as the common voltage Vcom is applied to the storage wiring. Here, alternatively or additionally, the sub-pixel electrodes Pa, Pb and the previous gate line may overlap each other with an insulating material interposed therebetween, thereby forming the storage capacitors Csta, Cstb.

Meanwhile, in order to realize color display, each pixel PX uniquely displays one color of a set of primary colors (spatial division), or each pixel PX temporally and alternately displays the set of primary colors (temporal division). In this way, the primary colors are spatially and temporally synthesized, thereby obtaining a desired color. Examples of the primary colors include three colors of red, green, and blue. As an example of the spatial partition, each pixel PX may have one color filter that displays one of colors in a region of the upper display panel. In addition, the color filter may be formed above or below the sub-pixel electrodes Pa, Pb of the lower display panel.

As will be further described below with reference to fig. 15, the gate driver is connected to the gate lines G, and applies a gate signal, which is obtained by combining an on voltage Von from the outside with an off voltage Voff, to the gate lines G.

The gray voltage generator may generate two sets of gray voltages (or a set of reference gray voltages) related to the transmittance of the pixel and supply the generated sets of gray voltages to the data driver. That is, the two sets of gray voltages may be independently supplied to a pair of sub-pixels Pxa and PXb forming the pixel PX. However, the present invention is not limited thereto. For example, instead of two sets of gray voltages, only one set of gray voltages may be generated.

The data driver is connected to the pair of data lines Da, Db. The data driver transmits a data voltage to one of the pair of sub-pixels forming the pixel through the data line Da, and transmits a different data voltage to the other sub-pixel of the pair of sub-pixels forming the pixel through the data line Db.

The gate driver or the data driver may be directly mounted on the liquid crystal display panel assembly in the form of a plurality of driving Integrated Circuit (IC) chips or may be attached to the liquid crystal display panel assembly while being mounted on a flexible printed circuit film (not shown) by a Tape Carrier Package (TCP). Alternatively, the gate driver or the data driver may be integrated in the liquid crystal display panel assembly along with the display signal lines G, Da and Db, the TFT switching elements Qa and Qb, and the like.

The signal controller controls the operation of the gate driver, the data driver, and the like.

Returning to fig. 1, one pixel includes two switching elements Qa, Qb, and two sub-pixel electrodes Pa, Pb connected to the switching elements Qa, Qb, respectively. Here, it is assumed that a relatively high data voltage is applied to the first subpixel electrode Pa and a relatively low data voltage is applied to the second subpixel electrode Pb. Hereinafter, the low data voltage and the high data voltage represent a lower difference or a higher difference between the common voltage and the data voltage. In addition, a pixel having the first subpixel Pa to which the data voltage is applied through the first data line Da is referred to as an a-type pixel; a pixel having the first subpixel Pa to which the data voltage is applied through the second data line Db is referred to as a B-type pixel.

As shown in fig. 1, the a-type pixels and the B-type pixels are alternately arranged in the horizontal direction and the vertical direction (i.e., in the first and second directions), and thus vertical stripes or horizontal stripes may be prevented from being observed in the LCD.

If the data voltage is applied to the first sub-pixel electrodes Pa of all the pixels through the first data line Da, that is, if the pixel array includes only a-type pixels, and if the LCD is driven in a column inversion (column inversion) mode, a vertical stripe moving in a horizontal direction with respect to the inspection pattern, which is moved in a horizontal direction by one pixel per frame, is observed.

Further, if the data voltage is applied to the first sub-pixel electrode Pa of one pixel row through the first data line Da and the data voltage is applied to the first sub-pixel electrode Pa of the next pixel row through the second data line Db, that is, when the a-type pixel row and the B-type pixel row are alternately arranged, it is possible to prevent the above-mentioned vertical stripe moving in the horizontal direction from occurring. However, coupling occurs between each first subpixel electrode Pa and the first and second data lines Da, Db disposed at both sides of each first subpixel electrode Pa. Since the coupling capacitance between each first sub-pixel electrode Pa and the first and second data lines Da, Db varies according to the a-type and B-type pixels, horizontal stripes are observed.

Therefore, as in the LCD according to the first exemplary embodiment of the present invention shown in fig. 1, since the a-type pixels and the B-type pixels are alternately arranged in the horizontal direction and the vertical direction, it is possible to prevent the above-described vertical stripes or horizontal stripes moving in the horizontal direction. However, when the LCD having such a structure operates at a low gray scale level, the liquid crystal basically operates through the first sub-pixel electrode Pa to which a relatively high voltage is applied. Accordingly, a difference between the coupling capacitance between the first subpixel electrode Pa and the first data line Da and the coupling capacitance between the first subpixel electrode Pa and the second data line Db is reduced, thereby preventing a display quality from being lowered due to crosstalk.

In addition, as in the first exemplary embodiment of the present invention, since the first and second data lines Da and Db are disposed such that the second sub-pixel electrode Pb overlaps the first and second data lines Da and Db and the second sub-pixel electrode Pb surrounds the first sub-pixel electrode Pa, it is possible to prevent the occurrence of vertical stripes or horizontal stripes even when the a-type and B-type pixels are not alternately disposed in the horizontal and vertical directions. That is, by reducing the difference in coupling capacitance between the first and second data lines Da and Db and the first subpixel electrode Pa, it is possible to prevent the degradation of display quality. In this regard, further description is provided below.

Hereinafter, an exemplary LCD according to a first exemplary embodiment of the present invention will be further described with reference to fig. 3A to 5. The LCD according to this exemplary embodiment includes: a lower display panel on which a TFT array is formed, an upper display panel facing the lower display panel, and a liquid crystal layer interposed between the two display panels.

First, referring to fig. 3A to 3C, a lower display panel of an LCD according to a first exemplary embodiment is described. Here, fig. 3A is a layout view of an exemplary lower display panel including the exemplary a-type pixel of fig. 1 according to a first exemplary embodiment of the present invention. Fig. 3B is a cross-sectional view of the exemplary lower display panel taken along line IIIB-IIIB' of fig. 3A. Fig. 3C is a cross-sectional view of the exemplary lower display panel taken along line IIIC-IIIC of fig. 3A.

The gate line 22, which extends substantially in a horizontal or first direction and transmits a gate signal, is formed on an insulating substrate 10, which may be formed of transparent glass or the like. Each gate line 22 is assigned to a row of pixels. Further, a pair of first and second protruding gate electrodes 26a and 26b are formed on the gate line 22 for each pixel. The gate line 22 and the first and second gate electrodes 26a and 26b are referred to as a gate line.

Further, the storage line 28 is formed on the insulating substrate 10. The storage line 28 intersects the pixel region and extends substantially in the horizontal direction, and thus is at least substantially parallel to the gate line 22. The storage electrode 27 is connected to the storage line 28 and has a width greater than that of the storage line 28. The storage electrode 27 and the pixel electrode 82 overlap each other to form a storage capacitor that increases the charge capacity (charge capacity) of the pixel. The storage electrode 27 and the storage line 28 are referred to as a storage wiring. In this embodiment, the storage wirings 27, 28 overlap with the center of the pixel region, but the present invention is not limited thereto. In alternative embodiments, the shape and arrangement of the storage wires 27, 28 may be changed in various forms. Further, when a sufficient storage capacitance is generated by overlapping the pixel electrode 82 with the gate line 22, the storage wirings 27, 28 may not be required to be included.

The gate wirings 22, 26a, and 26b and the storage wirings 27 and 28 may be formed of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), titanium (Ti), or tantalum (Ta). In addition, each of the gate wirings 22, 26a, 26b and each of the storage wirings 27, 28 may have a multilayer structure including two conductive films (not shown) having different physical properties. In such a multilayer structure, one of the two conductive films may be made of a metal having a low resistivity (e.g., an aluminum-based metal, a silver-based metal, or a copper-based metal) to reduce signal delay or voltage drop in each of the gate wirings 22, 26a, 26b and each of the storage wirings 27, 28. The other conductive film in the multilayer structure is specifically formed of a material having good contact properties with respect to Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or other pixel electrode materials, and may be, for example, molybdenum-based metal, chromium, titanium, or tantalum. Examples of such a multilayer structure include a structure having a lower chromium film and an upper aluminum film, and a structure having a lower aluminum film and an upper molybdenum film. However, the present invention is not limited thereto, and each of the gate wirings 22, 26a, 26b and each of the storage wirings 27, 28 may be formed of various metal materials or conductors different from the above-described materials.

A gate insulating layer 30 formed of silicon nitride (SiNx) or the like is formed on the gate wiring 22 and the storage wirings 27, 28, and on the exposed surface of the insulating layer 10.

Semiconductor layers 40a, 40b formed of hydrogenated amorphous silicon (a-Si) or polysilicon are formed on the gate insulating layer 30. The semiconductor layers 40a, 40b may have various shapes such as an island shape or a stripe shape. For example, as shown, the semiconductor layers 40a, 40b may be formed to have an island shape. The semiconductor layers 40a, 40b are formed to overlap the gate electrodes 26a, 26 b.

The ohmic contact layers 55a, 56a are formed on the semiconductor layers 40a, 40b, and may be formed of silicide or n + hydrogenated a-Si doped with n-type impurities at a high concentration. A pair of ohmic contact layers 55a, 56a is positioned on each of the semiconductor layers 40a, 40 b.

A pair of first and second data lines 62a and 62b and a pair of first and second drain electrodes 66a and 66b corresponding to the first and second data lines 62a and 62b, respectively, are formed on the ohmic contact layers 55a and 56a and the insulating layer 30.

The first and second data lines 62a and 62b extend substantially in a vertical direction, pass through the gate line 22 and the storage line 28, and transmit data voltages. First and second source electrodes 65a and 65b extending toward the first and second drain electrodes 66a and 66b, respectively, protrude from the first and second data lines 62a and 62b, respectively. As shown in fig. 3A, one pixel is divided into a pair of sub-pixels, and the first data line 62a transmits a data signal to one sub-pixel, while the second data line 62b transmits a different data signal to the other sub-pixel, as will be further described below.

The first and second data lines 62a and 62b, the first and second source electrodes 65a and 65b, and the first and second drain electrodes 66a and 66b are referred to as data wirings.

Preferably, each of the data wirings 62a, 62b, 65a, 65b, 66a, and 66b may be formed of a refractory metal, such as chromium, molybdenum-based metal, tantalum, or titanium. In addition, each of the data wirings 62a, 62b, 65a, 65b, 66a, and 66b may have a multilayer structure in which an upper layer (not shown) composed of a low-resistance material is formed on a lower layer composed of a refractory metal or the like. Examples of the multi-layer structure may include a three-layer structure having a lower molybdenum layer, an intermediate aluminum layer, and an upper molybdenum layer, and the above-mentioned double-layer structure having a lower chromium layer and an upper aluminum layer or having a lower aluminum layer and an upper molybdenum layer. However, the present invention is not limited thereto, and each of the data wirings 62a, 62b, 65a, 65b, 66a, and 66b may be formed of a plurality of metal materials or conductors different from the above-described materials.

The semiconductor layers 40a, 40b are at least partially overlapped by the first and second source electrodes 65a, 65b, respectively. The first and second drain electrodes 66a, 66b face the first and second source electrodes 65a, 65b, respectively, with respect to the gate electrodes 26a, 26 b. The semiconductor layers 40a, 40b are at least partially overlapped by the first and second drain electrodes 66a, 66b, respectively. Here, the ohmic contact layers 55a and 56a described above may be present between the semiconductor layers 40a and 40b and the first and second source electrodes 65a and 65b and between the semiconductor layers 40a and 40b and the first and second drain electrodes 66a and 66b, thereby reducing contact resistance therebetween.

A passivation layer 70 is formed on the data wires 62a, 62b, 65a, 65b, 66a and 66b and the exposed semiconductor layers 40a and 40b, and on the exposed portions of the gate insulating layer 30. The passivation layer 70 is made of an inorganic material such as silicon nitride or silicon oxide, an organic material having good planar characteristics and photosensitivity, or an insulating material having a low dielectric constant such as a-Si: C: O or a-Si: O: F formed by Plasma Enhanced Chemical Vapor Deposition (PECVD). In addition, the passivation layer 70 may have a double-layered structure including a lower inorganic layer and an upper organic layer to improve the characteristics of the organic film and protect the exposed semiconductor layers 40a and 40 b. In addition, a red, green, or blue color filter layer may be used as the passivation layer 70.

The pixel electrode 82 formed on the passivation layer 70 includes first and second sub-pixel electrodes 82a and 82b separated from each other. Here, each of the first and second subpixel electrodes 82a and 82b may be made of a transparent electrical conductor (such as ITO or IZO) or a reflective electrical conductor (such as aluminum).

The first and second subpixel electrodes 82a and 82b are electrically connected to the first and second drain electrodes 66a and 66b through the first and second contact holes 76a and 76b, respectively, and are applied with different data voltages from the first and second drain electrodes 66a and 66 b.

The first and second sub-pixel electrodes 82a and 82b to which the data voltages are applied generate an electric field together with the common electrode on the upper display panel, thereby determining the arrangement of liquid crystal molecules in the liquid crystal layer between the first and second sub-pixel electrodes 82a and 82b and the common electrode.

Further, as described above, referring to fig. 2 and 3A, the sub-pixel electrodes 82a and 82b form liquid crystal capacitors Clca and Clcb with the common electrode, respectively, so that the applied voltage can be maintained even if the TFTs Qa and Qb are turned off. In order to increase the voltage sustaining capability, the storage capacitors Csta, Cstab connected in parallel with the liquid crystal capacitors Clca and Clcb may be formed in such a manner that the first and second sub-pixel electrodes 82a, 82b or the first and second drain electrodes 66a, 66b connected to the first and second sub-pixel electrodes 82a, 82b overlap the storage wirings 27 and 28.

Returning to fig. 3A to 3C, one pixel electrode 82 includes first and second sub-pixel electrodes 82a, 82b electrically isolated from each other by a gap 83. The first sub-pixel electrode 82a has a nearly horizontal V-shape (such as a rotated and truncated V-shape). The second subpixel electrode 82b is formed in a region of the pixel excluding the first subpixel electrode 82a and the gap 83. Specifically, the second subpixel electrode 82b is formed to surround the periphery of the first subpixel electrode 82 a.

The gap 83 includes inclined portions inclined at about 45 ° or-45 ° with respect to the gate lines 22, and vertical portions connected between the inclined portions and arranged along the first and second data lines 62a, 62 b.

Although not shown in the drawings, a domain dividing device (not shown), such as a cutout or a bump, inclined at about 45 ° or-45 ° with respect to the gate line 22 may be formed. The display region of the pixel electrode 82 is divided into a plurality of domains in a direction in which main directors of liquid crystal molecules contained in the liquid crystal layer are aligned when an electric field is applied when the electric field is applied. The gap 83 and the domain dividing means are used to divide the pixel electrode 82 into a plurality of domains. The domain refers to a region in which liquid crystal molecules are formed while the liquid crystal molecules are commonly tilted in a predetermined direction by an electric field formed between the pixel electrode 82 and the common electrode 90.

As described above, the entire first subpixel electrode 82a is V-shaped, and the second subpixel electrode 82b is formed to surround the first subpixel electrode 82 a. Specifically, the second sub-pixel electrode 82b includes a main region and a bridge region. The main regions are adjacent to the inclined portions of the gap 83, they are inclined at about 45 ° or-45 ° with respect to the gate lines 22, and control the movement of the liquid crystal molecules. The bridge region is adjacent to the vertical portion of the gap 83, is arranged along the first and second data lines 62a, 62b, and connects the main regions to each other.

As shown in fig. 3A and 3C, the first and second data lines 62a and 62b are formed such that the second subpixel electrode 82b at least partially overlaps the first and second data lines 62a and 62 b. Preferably, the first and second data lines 62a and 62b are formed such that the second subpixel electrode 82b completely overlaps the first and second data lines 62a and 62 b. Specifically, the bridge region of the second subpixel electrode 82b overlaps the first and second data lines 62a and 62 b.

An alignment layer (not shown) may cover the first and second subpixel electrodes 82a and 82b and the passivation layer 70.

Next, referring to fig. 4 and 5, an exemplary upper display panel and an exemplary LCD will be described. Here, fig. 4 is a layout view of an exemplary upper display panel connected to the exemplary lower display panel of fig. 3A. Fig. 5 is a layout view of an exemplary LCD including the exemplary lower display panel of fig. 3A and the exemplary upper display panel of fig. 4.

The black matrix 94, which prevents light from leaking and defines a pixel region, is formed on an insulating substrate (not shown) made of transparent glass or the like. The black matrix 94 may be formed on portions corresponding to the gate line 22 and the first and second data lines 62a and 62b, and portions corresponding to the TFTs. In addition, the black matrix 94 may have a different shape to block light leakage around the first and second sub-pixel electrodes 82a and 82b and the TFT. The black matrix 94 may be made of metal (metal oxide) such as chrome or chrome oxide, or organic black resist.

In the black matrix 94, red, green, and blue color filters (not shown) may be sequentially arranged in the pixel region.

An overcoat layer (not shown) may be formed on the color filters to remove a step (step) between the color filters.

A common electrode 90 formed of a transparent conductive material such as ITO or IZO is formed on the capping layer. The common electrode 90 may include a domain dividing means 92 facing the first and second sub-pixel electrodes 82a and 82b and inclined at about 45 ° or-45 ° with respect to the gate wire 22, and may include cutouts or protrusions.

An alignment layer (not shown) for aligning liquid crystal molecules may be formed on the common electrode 90.

The lower display panel and the upper display panel having the above-described structure are aligned and connected to each other, and a liquid crystal material is injected between the upper and lower display panels and vertically aligned. Thus, the basic structure of the LCD according to the first exemplary embodiment is formed.

In the case where no electric field is applied to the pixel electrode 82 and the common electrode 90, liquid crystal molecules contained in the liquid crystal layer are aligned such that the director thereof is perpendicular to the lower display panel and the upper display panel. In addition, the liquid crystal molecules have negative dielectric anisotropy.

In addition to the above basic structure, the LCD may further include components such as a polarizer and a backlight. Here, the polarizers may be respectively disposed on both sides of the basic structure such that one emission axis of the polarizer is parallel to the gate line 22 and the other emission axis is perpendicular to the gate line 22.

When an electric field is applied between the lower display panel and the upper display panel, an electric field perpendicular to the upper and lower display panels is generated in almost all regions. However, the horizontal electric field is generated around the gap 83 of the pixel electrode 82 and the domain dividing means 92 of the common electrode 90. The horizontal electric field assists in aligning the liquid crystal molecules in each domain.

Since the liquid crystal molecules of this embodiment have negative dielectric anisotropy, when an electric field is applied to the liquid crystal molecules, the liquid crystal molecules in the respective domains are tilted to be perpendicular to the gap 83 or the domain dividing means 92 dividing the domains. Accordingly, the liquid crystal molecules are inclined in different directions on both sides of the gap 83 or the domain dividing means 92, and the inclined portion of the gap 83 or the inclined portion of the domain dividing means 92 is symmetrical with respect to each pixel center. Thus, the liquid crystal molecules are inclined by substantially 45 ° or-45 ° in four directions with respect to the gate line 22. Since the optical characteristics are complemented by the liquid crystal molecules tilted in four directions, the viewing angle increases.

Next, with reference to fig. 3A to 5, the operation of the exemplary LCD according to the first exemplary embodiment of the present invention will be described.

In the a-type pixel, a relatively high data voltage is applied to the first subpixel electrode 82a connected to the first data line 62a, and a relatively low data voltage is applied to the second subpixel electrode 82b connected to the second data line 62 b. Accordingly, it is possible to improve side visibility of the LCD.

Specifically, when the LCD operates at a low gray scale level, the liquid crystal basically operates through the first subpixel electrode 82a to which a higher data voltage is applied, without applying a voltage to the second subpixel electrode 82 b. In this case, since the second sub-pixel electrode 82b is applied with substantially the same voltage as the common electrode 90 on the upper display panel, the liquid crystal molecules disposed above the second sub-pixel electrode 82b are aligned such that the director thereof is perpendicular to the lower display panel. Therefore, light emitted from the backlight cannot pass through the second sub-pixel electrode 82b, but is blocked.

When the LCD is operated at a high gray scale level, light leakage does not matter since the overall brightness of the LCD is high. In view of this, it is more important to prevent light leakage when the LCD is operated at a low gray scale level. Generally, light leakage occurs around the first and second data lines 62a, 62 b. However, as in the first exemplary embodiment of the present invention, when the second subpixel electrode 82b overlaps the first and second data lines 62a and 62b and the LCD operates at a low gray scale level, light passing through the second subpixel electrode 82b is blocked by the second subpixel electrode 82b and light leakage around the first and second data lines 62a and 62b can be prevented. Further, light leakage can be prevented by using the second sub-pixel electrode 82b surrounding the first sub-pixel electrode 82a without increasing the area of the black matrix 94, thereby improving the aperture ratio.

When the coupling capacitances between the first subpixel electrode 82a to which a higher voltage is applied and the first and second data lines 62a and 62b are not identical to each other, the display performance of the LCD may be degraded. For this, the first subpixel electrode 82a is disposed such that the first subpixel electrode 82a does not overlap the first and second data lines 62a and 62b to reduce the coupling capacitance between the first subpixel electrode 82a and the first and second data lines 62a and 62 b. This prevents the coupling capacitance from affecting the display performance of the LCD.

Next, referring to fig. 6, another portion of an exemplary lower display panel of an exemplary LCD according to a first exemplary embodiment of the present invention will be described. Fig. 6 is a layout view of an exemplary lower display panel including the exemplary B-type pixel of fig. 1 according to a first exemplary embodiment of the present invention. For convenience of explanation, components having the same functions as those in fig. 3A to 5 are denoted by the same reference numerals, and thus descriptions thereof are omitted. Only the differences are described below.

As shown in fig. 6, unlike the a-type pixel, the B-type pixel includes: the first drain electrode 66a connected to the second subpixel electrode 82b through the first contact hole 76a, and the second drain electrode 66b connected to the first subpixel electrode 82a through the second contact hole 76 b. A relatively high voltage is applied to the first subpixel electrode 82a connected to the second data line 62b, and a relatively low voltage is applied to the second subpixel electrode 82b connected to the first data line 62 a. Accordingly, the side visibility of the LCD may be improved.

In the case of the LCD having the above-described structure, it is possible to prevent light leakage around the first and second data lines 62a and 62b and to improve the aperture ratio of the LCD. In addition, the coupling capacitance between the first subpixel electrode 82a and the first and second data lines 62a and 62b is reduced, thereby preventing the display performance of the LCD from being degraded.

Next, an exemplary lower display panel of an exemplary LCD according to a second exemplary embodiment of the present invention will be described in detail with reference to fig. 7A and 7B. Fig. 7A is a layout view of an exemplary lower display panel including the a-type pixel of fig. 1 according to a second exemplary embodiment of the present invention. Fig. 7B is a cross-sectional view illustrating an exemplary lower display panel taken along line VIIB-VIIB' of fig. 7A. For convenience of explanation, components having the same functions as those in the above-described embodiment (fig. 1 to 6) are denoted by the same reference numerals, and thus descriptions thereof are omitted. Only the differences are described below.

As shown in fig. 7A and 73, in order to further reduce the coupling capacitance between the first subpixel electrode 82a and the first and second data lines 62a and 62b, first and second auxiliary storage electrodes 29a and 29b connected to the storage line 28 and extending substantially in the vertical direction and parallel to the first and second data lines 62a and 62b are formed.

Here, the first and second auxiliary storage electrodes 29a and 29b may be formed such that the gap 83 separating the first and second sub-pixel electrodes 82a and 82b from each other partially overlaps the first and second auxiliary storage electrodes 29a and 29 b. Here, the gap 83 includes inclined portions and vertical portions, wherein the inclined portions are inclined at about 45 ° or-45 ° with respect to the gate lines 22, and the vertical portions are connected between the inclined portions and arranged along the first and second data lines 62a, 62 b. Therefore, it is preferable that the first and second auxiliary storage electrodes 29a and 29b partially overlap the vertical portion of the gap 83 adjacent to the first and second data lines 62a and 62 b. The first and second auxiliary storage electrodes 29a and 29b may protrude from edges of the storage electrode 27.

The first and second auxiliary storage electrodes 29a and 29b and the first subpixel electrode 82a form a storage capacitor, so that coupling between the first subpixel electrode 82a and the first and second data lines 62a and 62b may be prevented.

In addition, as shown in fig. 7B, when the first subpixel electrode 82a partially overlaps the first and second auxiliary storage electrodes 29a and 29B, the coupling capacitance between the first subpixel electrode 82a and the first and second data lines 62a and 62B may be further reduced. The overlapping width between the first subpixel electrode 82a and each of the first and second auxiliary storage electrodes 29a and 29b is L, and the size may be, for example, about 1 to about 3 μm.

Next, another portion of an exemplary lower display panel of an exemplary LCD according to a second exemplary embodiment of the present invention will be described with reference to fig. 8. Fig. 8 is a layout view of an exemplary lower display panel including the exemplary B-type pixel of fig. 1 according to a second exemplary embodiment of the present invention. For convenience of description, components having the same functions as those in fig. 7A and 7B are denoted by the same reference numerals, and thus description thereof is omitted. Only the differences are described below.

As shown in fig. 8, in the B-type pixel, the first drain electrode 66a is connected to the second sub-pixel electrode 82B through the first contact hole 76a, and the second drain electrode 66B is connected to the first sub-pixel electrode 82a through the second contact hole 76B. A relatively high voltage is applied to the first subpixel electrode 82a connected to the second data line 62b, and a relatively low voltage is applied to the second subpixel electrode 82b connected to the first data line 62 a. Accordingly, the side visibility of the LCD may be improved.

As described above for the a-type pixel shown in fig. 7A and 7B, the B-type pixel shown in fig. 8 includes the first and second auxiliary storage electrodes 29a and 29B.

In the case of the LCD having the above-described structure, as in the first exemplary embodiment, it is possible to prevent light leakage around the first and second data lines 62a and 62b and improve the aperture ratio of the LCD. In addition, the coupling capacitance between the first subpixel electrode 82a and the first and second data lines 62a and 62b is further effectively reduced by the first and second auxiliary storage electrodes 29a and 29b, thereby preventing the display performance of the LCD from being lowered.

Next, referring to fig. 1, 9A and 9B, coupling capacitances between sub-pixel electrodes and data lines in an LCD according to an exemplary embodiment of the present invention will be described. Preferably, when a dynamic image is displayed in the LCD, the frequency of an input image signal is increased and the response speed of liquid crystal molecules is increased to prevent a residual image from blurring with an image to be generated. For example, in an LCD operating at a frequency of 120Hz or higher, it is preferable that the LCD be driven in a column inversion mode rather than a dot inversion mode in consideration of the response speed of liquid crystal molecules. Hereinafter, the coupling capacitance between the subpixel electrode and the data line will be described in detail according to the LCD driven by the column inversion mode as an example. In the LCD driven in the column inversion mode, during a first frame, a positive polarity data voltage is applied to the first data lines Da, and a negative polarity data voltage is applied to the second data lines Db (here, the positive and negative polarities refer to the polarities of the data voltages with respect to the common voltage, as will be described in detail below with reference to fig. 16). During the second frame period, a negative polarity data voltage is applied to the first data line Da, and a positive polarity data voltage is applied to the second data line Db.

First, referring to fig. 1 and 9A, a coupling capacitance between the first subpixel electrode Pa to which a higher data voltage is applied and the data line Da, Db will be described. Fig. 9A is a graph illustrating a luminance difference between an exemplary first sub-pixel electrode Pa of the exemplary a-type pixel and an exemplary first sub-pixel electrode Pa of the exemplary B-type pixel of fig. 1 when a gray scale level is changed. Here, since the first subpixel electrode Pa of the a-type and B-type pixels has an area adjacent to the first data line Da larger than an area adjacent to the second data line Db, the coupling capacitance between the first subpixel electrode Pa and the first data line Da mainly affects the luminance variation of the LCD. In addition, the first subpixel electrode Pa always has high luminance at a high gray scale level, but luminance variation occurs at a low gray scale level.

In the case of the a-type pixel, during the first frame, the positive polarity data voltage is applied to the first subpixel electrode Pa through the first data line Da. During the second frame, the negative polarity data voltage is applied to the first data line Da. Thus, before the data voltage is applied to the first subpixel electrode Pa during the second frame, coupling occurs between the first subpixel electrode Pa and the first data line Da, and the data voltage stored in the first subpixel electrode Pa during the first frame is reduced. Therefore, the luminance of the first subpixel electrode Pa is also decreased.

In the case of the B-type pixel, during the first frame, a negative polarity data voltage is applied to the first sub-pixel electrode Pa through the second data line Db. During the second frame, the negative polarity data voltage is applied to the first data line Da. Thus, coupling occurs between the first subpixel electrode Pa and the first data line Da before the data voltage is applied to the first subpixel electrode Pa through the second data line Db during the second frame, and thus the data voltage stored in the first subpixel electrode Pa is further increased during the first frame. Therefore, the luminance of the first subpixel electrode Pa is also enhanced.

In fig. 9A, the luminance difference data refers to: the difference between the Root Mean Square (RMS) value of the luminance of the first subpixel electrode Pa of the a-type pixel with respect to the first and second frames and the RMS value of the luminance of the first subpixel electrode Pa of the B-type pixel with respect to the first and second frames. As shown in fig. 9A, even though there is a luminance difference between the first sub-pixel electrodes Pa of the a-type pixel and the B-type pixel at the low gray scale level, the difference is only about 1.5% or less. This means that the coupling capacitance between the first subpixel electrode Pa and the first and second data lines Da and Db is also greatly reduced.

Referring to fig. 1 and 9B, a coupling capacitance between the second sub-pixel electrode Pb to which a lower data voltage is applied and the data lines Da, Db will be described. Fig. 9B is a graph illustrating a luminance difference between an exemplary second sub-pixel electrode Pb of the exemplary a-type pixel of fig. 1 and an exemplary second sub-pixel electrode Pb of the exemplary B-type pixel of fig. 1 when a gray scale level is changed. Here, since the overlapping area between the second sub-pixel electrode Pb of the a-type and B-type pixels and the first data line Da is larger than the overlapping area between the second sub-pixel electrode Pb and the second data line Db, the coupling capacitance between the second sub-pixel electrode Pb and the first data line Da mainly affects the luminance variation of the LCD. In addition, since the second subpixel Pb does not operate at the low gray level but operates only at the high gray level, a variation in the luminance difference occurs at the high gray level.

In the case of the a-type pixel, during the first frame, a negative polarity data voltage is applied to the second sub-pixel electrode Pb through the second data line Db. During the second frame, the negative polarity data voltage is applied to the first data line Da. Thus, during the second frame, before the data voltage is applied to the second subpixel electrode Pb through the second data line Db, coupling occurs between the second subpixel electrode Pb and the first data line Da, and the data voltage stored in the second subpixel electrode Pb increases during the first frame. Therefore, the luminance of the second subpixel electrode Pb is also enhanced.

In the case of the B-type pixel, during the first frame, the positive polarity data voltage is applied to the second subpixel electrode Pb through the first data line Da. During the second frame, the negative polarity data voltage is applied to the first data line Da. Thus, during the second frame, before the data voltage is applied to the second subpixel electrode Pb through the first data line Da, coupling occurs between the second subpixel electrode Pb and the first data line Da, and the data voltage stored in the second subpixel electrode Pb during the first frame decreases. Therefore, the luminance of the second subpixel electrode Pa is also decreased.

In fig. 9B, the luminance difference data refers to: the difference between the luminance RMS values of the second sub-pixel electrodes Pb of the a-type pixels with respect to the first and second frames and the luminance RMS values of the second sub-pixel electrodes Pb of the B-type pixels with respect to the first and second frames. As shown in fig. 9B, even if there is a luminance difference between the second sub-pixels Pb of the a-type and B-type pixels at a high gray scale level, the luminance difference is only about 2.5% or less. This means that even when the second sub-pixel electrode Pb overlaps the first and second data lines Da and Db, there is only a small coupling capacitance between the second sub-pixel electrode Pb and the first and second data lines Da and Db. Next, referring to fig. 10 to 11C, an exemplary LCD according to a third exemplary embodiment of the present invention will be described. For convenience of description, components having the same functions as those of the above-described embodiments are denoted by the same reference numerals, and thus, descriptions thereof are omitted. Only the differences are described below.

First, fig. 10 shows an equivalent circuit diagram of an exemplary display signal line and an exemplary pixel. Fig. 10 is an equivalent circuit diagram of an exemplary pixel in an exemplary LCD according to a third exemplary embodiment of the present invention.

As shown in FIG. 10, the display signal line includes a gate line G_LData line D_LAnd first and second storage lines SL₁、SL₂. First and second storage lines SL₁、SL₂Is substantially parallel to the gate line G_LEtc. extend in the same direction.

In addition, each pixel PX includes, for example, first and second sub-pixels P_H、P_L. Here, the first and second sub-pixels P_H、P_LThe method comprises the following steps: switching elements Q1 and Q2 connected to the gate line G_LAnd a data line D_L(ii) a Liquid crystal capacitors Clca and Clcb connected to the switching elements Q1 and Q2, respectively; and storage capacitors Csta, Cstb connected to the switching elements Q1, Q2 and the storage line SL, respectively₁、SL₂。

Specifically, the first sub-pixel P_HThe method comprises the following steps: a first switching element Q1 connected to the gate line G_LAnd a data line D_L(ii) a A first liquid crystal capacitor Clca connected to the first switching element Q1; and a first storage capacitor Csta connected to the first switching element Q1 and the first storage line SL₁. In addition, the second sub-pixel P_LThe method comprises the following steps: a second switching element Q2 connected to the gate line G_LAnd a data line D_L(ii) a A second liquid crystal capacitor Clcb connected to the second switching element Q2; and a second storage capacitor Cstb connected to the second switching element Q2 and the second storage line SL₂。。

Corresponding first and second sub-pixels P_H、P_LFirst and second switching elements Q1, Q2 from the same gate line G_LBranched, and may include TFTs, etc. Here, each of the first and second switching elements Q1 and Q2 may be a three-terminal element including: a gate electrode as a control terminal connected to the gate line G_L(ii) a A source electrode as an input terminal connected to the data line D_L(ii) a And a drain electrode as an output terminal connected to each of the liquid crystal capacitors Clca and Clcb and each of the first and second storage capacitors Csta and Cstb.

Each of the liquid crystal capacitors Clca and Clcb has both terminals of the first and second sub-pixel electrodes of the lower display panel and the common electrode of the upper display panel, and the liquid crystal layer interposed between the first and second sub-pixel electrodes Pa and Pb and the common electrode serves as an insulator. The first and second sub-pixel electrodes are connected to switching elements Q1 and Q2, respectively. The common electrode is formed on the entire surface or almost the entire surface of the upper display panel and is applied with a common voltage Vcom.

The first and second storage capacitors Csta and Cstb, which respectively assist the first and second liquid crystal capacitors Clca and Clcb, have first and second storage lines SL₁、SL₂And first and second sub-pixel electrodes overlapping each other and provided on the lower display panel with an insulating material interposed therebetween. The first and second storage voltages may be applied to the first and second storage lines SL, respectively₁、SL₂The above. The first and second storage voltages may have different values, such as a common voltage Vcom in a phase opposite to each other.

Here, in the first sub-pixel P_HFirst sub-pixel electrode and second sub-pixel P_LMay have different data voltages formed therein.

Specifically, the slave data line D is connected to the first and second switching elements Q1 and Q2_LWherein the same data voltage is applied to the first subpixel electrode and the second subpixel electrode. Here, since the first subpixel electrode is connected to the first storage line SL₁A data voltage applied to the first subpixel electrode and a first storage line SL₁The first storage voltage is coupled so that the value of the data voltage changes. In the same manner, since the second subpixel electrode is connected to the second storage line SL₂A data voltage applied to the second subpixel electrode and a second storage line SL₂Is stored inThe voltages are coupled so that the value of the data voltage changes. As described above, when the first and second storage voltages have voltages different from each other, as a result, the data voltages formed in the first and second sub-pixel electrodes also have voltages different from each other.

For example, the data voltage formed in the first subpixel electrode may have a larger value than the data voltage formed in the second subpixel electrode. In this case, the first subpixel P_HOperation can be started at a low gray level while the second sub-pixel P_LIt is possible to operate at medium or higher gray scale levels.

Next, referring to fig. 11A to 11C, an exemplary lower display panel of an exemplary LCD according to a third exemplary embodiment of the present invention will be described in detail. Here, fig. 11A is a layout view of an exemplary lower display panel of an exemplary LCD according to a third exemplary embodiment of the present invention. Fig. 11B is a layout view of an exemplary lower display panel taken along line XIB-XIB' of fig. 11A. Fig. 11C is a cross-sectional view of the exemplary lower display panel taken along line XIC-XIC' of fig. 11A.

The gate line 122 and the first and second storage lines 128a and 128b are formed on an insulating substrate 10 made of, for example, transparent glass or the like.

The plurality of gate lines 122 extend in a first direction (e.g., a horizontal direction), are separated from each other, and are electrically isolated from each other. The gate line 122 transmits a gate signal. Further, in the pixel row, a gate electrode 126 formed in a protrusion shape is formed on each gate line 122 corresponding to each pixel. The gate line 122 and the gate electrode 126 are collectively referred to as a gate wiring.

The first and second storage lines 128a, 128b extend substantially in the same direction as the gate line 122, and have storage electrodes 129a, 129b, respectively. The storage electrode has a width greater than the storage lines 128a, 128 b. Here, a pixel electrode 182 (described in detail below) overlaps the first and second storage electrodes 129a and 129b to form a storage capacitor, which increases the charge capacity of the pixel. The first and second storage lines 128a and 128b and the first and second storage electrodes 129a and 129b are collectively referred to as a storage wiring. In alternative embodiments, the shapes and arrangements of the first and second storage lines 128a, 128b and the first and second storage electrodes 129a, 129b may be variously changed. First and second storage voltages supplied from the outside, such as a common voltage Vcom, which are inverted with respect to each other, may be applied to the first and second storage lines 128a and 128 b.

The gate wirings 122, 126 and the storage wirings 128a, 128b, 129a, 129b may be made of substantially the same material as the gate wirings 22, 26a, 26b previously described with reference to fig. 3A.

A gate insulating layer 30 made of silicon nitride or the like is formed on the gate wirings 122, 126 and the storage wirings 128a, 128b, 129a, 129b, and on the exposed surface of the insulating substrate 10.

A semiconductor layer 140 made of hydrogenated amorphous silicon or polycrystalline silicon is formed on the gate insulating layer 30. The semiconductor layer 140 may have various shapes such as an island shape or a stripe shape. For example, as shown in fig. 11A, the semiconductor layer 140 has an island shape and is formed to overlap with a region occupied by the gate electrode 126.

Ohmic contact layers 155, 156 made of silicide or n + hydrogenated a-Si doped with n-type impurities at high concentration are formed on the semiconductor layer 140.

The data line 162, the source electrode 165, and the first and second drain electrodes 166a and 166b are formed on the ohmic contact layers 155 and 156 and the gate insulating layer 30.

The data line 162 extends in a second direction (e.g., a vertical direction), crosses the gate line 122 and the storage lines 128a and 128b, and transmits a data voltage. The source electrode 165 extends from each gate line 162 and extends toward the first and second drain electrodes 166a, 166 b. As shown in fig. 11A, a data voltage applied from the data line 162 to the source electrode 165 is transferred to each of the first and second sub-pixel electrodes 182a and 182b through each of the first and second drain electrodes 166a and 166 b.

The data line 162, the source electrode 165, and the first and second drain electrodes 166a and 166b are collectively referred to as a data line. The data wirings 162, 165, 166a, 166b may be made of substantially the same material as the data wirings 62a, 62b, 65a, 65b, 66a, 66b previously described with reference to fig. 3A.

The semiconductor layer 140 partially overlaps the source electrode 165, which is branched from the data line 162 in a branched shape. The semiconductor layer 140 is at least partially overlapped by the first and second drain electrodes 166a, 166b facing the source electrode 165 with respect to the gate electrode 126. Here, the above-mentioned ohmic contact layers 155, 156 may be present between the semiconductor layer 140 and the source electrode 165 and between the semiconductor layer 140 and the first and second drain electrodes 166a, 166b to reduce contact resistance.

Each of the first and second drain electrodes 166a, 166b includes: a bar-shaped pattern overlapping the semiconductor layer 140 adjacent to the source electrode 165, and a drain electrode extension portion extending from the bar-shaped pattern and having a large overlapping area with the storage electrodes 129a, 129 b. First and second contact holes 176a and 176b are located on each drain electrode extension. The drain electrode extension portion overlaps the pixel electrode 182 or the first and second storage electrodes 129a and 129b to form a storage capacitor.

The passivation layer 70 is formed on the data wire 162, 165, 166a, 166b and the exposed semiconductor layer 140, and on the exposed portion of the gate insulating layer 30. The first and second contact holes 176a and 176b are formed through the passivation layer 70 to expose large-area portions of the drain electrode extensions of the first and second drain electrodes 166a and 166 b.

The pixel electrode 182 formed on the passivation layer 70 includes first and second sub-pixel electrodes 182a and 182b, which are separated from each other by a gap 183. Here, each sub-pixel 182a, 182b may be made of a transparent electrical conductor (such as ITO or IZO) or a reflective electrical conductor (such as aluminum).

The first and second subpixel electrodes 182a and 182b are electrically connected to the first and second drain electrodes 166a and 166b through the first and second contact holes 176a and 176b, respectively, and supplied with data voltages from the first and second drain electrodes 166a and 166 b.

The first and second sub-pixel electrodes 182a and 182b to which the data voltages are applied generate an electric field in common with the common electrode on the upper display panel, thereby determining the arrangement of the liquid crystal molecules between the first and second sub-pixel electrodes 182a and 182b and the common electrode.

Further, referring to fig. 10 and 11A, the sub-pixel electrodes 182a, 182b form liquid crystal capacitors Clca, Clcb with the common electrode, and the applied voltage can be maintained even after the TFTs Q1, Q2 are turned off. In order to increase the voltage sustaining capability, the storage capacitors Csta, Cstb connected in parallel with the liquid crystal capacitors Clca and Clcb may be formed in such a manner that the storage wirings 128a, 128b are overlapped by the first and second sub-pixel electrodes 182a, 182b or by the first and second drain electrodes 166a, 166b connected to the first and second sub-pixel electrodes 182a, 182 b.

First and second storage voltages having different values from each other may be applied to the first and second storage lines 128a and 128b, respectively. For example, the first and second storage voltages can be the common voltage Vcom in opposite phase.

Since the first and second subpixel electrodes 182a and 182b are connected to the first and second storage lines 128a and 128b, respectively, the data voltage applied to the first subpixel 182a and the data voltage applied to the second subpixel 182b are also coupled to the first and second storage voltages, respectively, and thus their values are changed.

For example, the first and second storage voltages may be voltages that are inverted with respect to each other. Therefore, the first and second sub-pixel electrodes 182a and 182b have a predetermined voltage value deviation therebetween. For example, even if the data voltage is received from the same data line 162, the data voltage formed in the first subpixel electrode 182a may be higher than the data voltage formed in the second subpixel electrode 182 b. In an exemplary embodiment, the first subpixel electrode 182a may operate at a low gray level, and the second subpixel electrode 182b may operate at a middle gray level or higher.

Returning to fig. 11A to 11C, one pixel electrode 182 includes first and second sub-pixel electrodes 182a, 182b that are separated by a gap 183 and are electrically isolated from each other.

Preferably, the first sub-pixel electrode 182a is formed in the pixel region so as not to overlap the data line 162. For example, the first sub-pixel electrode 182a may have a rectangular shape as shown, but the present invention is not limited thereto.

The second subpixel electrode 182b is formed in a region of the pixel excluding the first subpixel electrode 182 a. More specifically, the second sub-pixel electrode 182b surrounds the outer edge or periphery of the first sub-pixel electrode 182a, i.e., surrounds the upper/lower/left/right of the first sub-pixel electrode 182 a. Preferably, at least a portion of the second subpixel electrode 182b overlaps the data line 162. The second sub-pixel electrode 182b may overlap the data line 162 by a predetermined width d2, and the overlap width d2 may be in the range of about 2 to 3 μm. The second subpixel electrode 182b may overlap the data line 162 from which the second subpixel electrode 182b receives the data voltage, and the second subpixel electrode 182b may also overlap the adjacent data line 162. Here, the second subpixel electrode 182b overlaps the data line 162 to increase an aperture ratio of the LCD.

The width of the gap 183 separating the first and second sub-pixel electrodes 182a, 182b from each other may be d1, and the size of d1 may be, for example, about 5 to 6 μm.

Initially, the same data voltage is applied to the first and second subpixel electrodes 182a and 182b through the data line 162. However, due to the connection between the first and second storage lines 128a and 128b and the first and second sub-pixel electrodes 182a and 182b, a higher data voltage is formed in the first sub-pixel electrode 182a and a lower data voltage is formed in the second sub-pixel electrode 182 b. Thus, the side visibility of the LCD is improved.

In addition, the first subpixel electrode 182a does not overlap the data line 162, but the second subpixel electrode 182b is disposed between the first subpixel electrode 182a and the data line 162 to prevent coupling therebetween. In this way, crosstalk in the vertical direction can be effectively prevented.

In particular, when the LCD operates at a low gray scale level, since the liquid crystal is substantially operated through the first sub-pixel electrode 182a to which a lower voltage is applied, it is possible to effectively prevent crosstalk in the vertical direction by preventing coupling between the first sub-pixel electrode 182a and the data line 162.

Alignment layers (not shown) for aligning the liquid crystal layer may be applied to the first and second subpixel electrodes 182a and 182b and the passivation layer 70.

Next, with reference to fig. 12A, 12B, an exemplary lower display panel for an exemplary LCD according to a fourth exemplary embodiment of the present invention will be described. Here, fig. 12A is a layout view of an exemplary lower display panel of an exemplary LCD according to a fourth exemplary embodiment of the present invention. Fig. 12B is a cross-sectional view of the exemplary lower display panel taken along line XIIB-XIIB' of fig. 12A. For convenience of description, components having the same functions as those of the above-described embodiments are denoted by the same reference numerals, and thus, descriptions thereof are omitted. Only the differences are described below.

The first storage wiring 127, 128a, 129a connected to the first subpixel electrode 182a includes: a first storage line 128a extending in substantially the same direction as the gate line 122; a first storage electrode 129a protruding from the first storage line 128a, having a large width, and forming a storage capacitor by overlapping the first drain electrode 166 a; and an auxiliary storage electrode 127 branched from the first storage line 128a and extending along the gap 183. In the illustrated embodiment, a first portion of the auxiliary storage electrode 127 extends along a portion of the gap 183 adjacent to the data line 162 from which the pixel electrode 182 receives the data voltage, and a second portion of the auxiliary storage electrode 127 extends along a portion of the gap 183 adjacent to the data line 162 of the adjacent pixel in the row direction.

The first and second sub-pixel electrodes 182a and 182b may be spaced apart from each other by the width of the gap 183, for example, by a width of about 5 to 6 μm. In order to prevent light leakage from occurring through the gap 183, the auxiliary storage electrode 127 branched from the first storage line 128a overlaps the gap 183, so that the circumference of the gap 183 is blocked, thereby preventing light leakage.

The auxiliary storage electrode 127 may be branched from the first storage line 128a and extend substantially parallel to the data line 162.

Hereinafter, with reference to fig. 13 to 16, an exemplary LCD according to a fifth exemplary embodiment of the present invention will be described.

Fig. 13 is a view illustrating a portion of an exemplary lower display panel of an exemplary LCD according to a fifth exemplary embodiment of the present invention.

Referring to fig. 13, the lower display panel 210 includes: the display device includes a base plate 212, a plurality of gate lines GL1 to GLn (GL 3-GL6 are exemplarily shown in the drawing), a plurality of data line pairs DL1/DL2, DL3/DL4, DL5/DL6 to DLm-1/DLm (DL 3/DL4-DL7/DL8 are exemplarily shown in the drawing), and a plurality of pixels PX. The lower display panel 210 according to the fifth exemplary embodiment of the present invention further includes a first switching element T1 and a second switching element T2 (as described in more detail in fig. 14) that supply two different polarity data voltages to each pixel.

The base plate 212 is a transparent insulating substrate and includes a plurality of pixel regions PA arranged in a matrix form. The plurality of gate lines GL 1-GLn and the plurality of data line pairs DL1/DL2, DL3/DL4 and DL5/DL 6-DLm-1/DLm are formed and laid on the substrate 212. The plurality of gate lines GL1 to GLn extend in the second direction D2. The plurality of data line pairs DL1/DL2, DL3/DL4, DL5/DL6 to DLm-1/DLm extend substantially in the first direction D1 such that the plurality of data line pairs are insulated from and cross the plurality of gate lines GL1 to GLn.

Here, the data line pairs DL1/DL2, DL3/DL4, DL5/DL6 to DLm-1/DLm are formed by grouping every two adjacent data lines, and one pixel area PA overlaps each data line pair. Each data line pair has a zigzag shape in which the shape of the data line pair is repeated in the second direction D2 to have an "M" shape in each pixel area PA.

A plurality of pixel electrodes PX, such as PX1, PX2, which are arranged in a matrix shape, are formed on the plurality of pixel areas PA, respectively. Each pixel electrode PX includes a first sub-pixel electrode (e.g., PXa of the pixel electrode PX1, PXc of the pixel electrode PX 2), and a second sub-pixel electrode (e.g., PXb of the pixel electrode PX1, PXd of the pixel electrode PX 2), which are sequentially formed in the second direction D2. In addition, the first and second thin film transistors T1 and T2 are formed on the pixel area PA in addition to the pixel electrode PX.

Fig. 14 is a diagram illustrating in detail the structure of one exemplary pixel electrode PX1 shown in fig. 13.

Referring to fig. 14, the pixel electrode PX1 includes a first sub-pixel electrode PXa and a second sub-pixel electrode PXb. The pixel electrode PX1 has a center that is bent in the left direction parallel to the gate line GL3, and the pixel electrode PX1 is symmetrical with respect to the bent center. Thus, both ends of the pixel electrode PX1 are bent in the right direction, which is opposite to the direction in which the center of the pixel electrode PX1 is bent.

The data line DL4 corresponding to the pixel electrode PX1 and another data line DL3 of the data line pair DL3/DL4 are adjacent to each other and formed substantially along the first direction D1. Thus, the pixel electrode PX1 overlaps the data line pair DL3/DL 4. The data lines DL3 and DL4 may be applied with data voltages different from each other, and the data line DL4 transmits the data voltages to the pixel electrode PX 1.

The first thin film transistor T1 is formed of a gate line GL3 and a data line DL4, and the first subpixel electrode PXa is electrically connected to the first thin film transistor T1. The first thin film transistor T1 includes: a first gate electrode G1 branched from the gate line GL 3; a first source electrode S1 branched from the data line DL 4; and a first drain electrode D1 separated from the first source electrode S1 and electrically connected to the first subpixel electrode PXa through the first contact hole H1.

The second thin film transistor T2 is formed by the gate line GL3 and the data line DL5, and the second sub-pixel electrode PXb is electrically connected to the second thin film transistor T2. Here, it is noted that the data line DL5 is formed to correspond to the adjacent pixel electrode PX2, that is, to overlap the adjacent pixel electrode PX 2.

The second thin film transistor T2 includes: a second gate electrode G2 branched from the gate line GL 3; a second source electrode S2 branched from the data line DL5 and disposed corresponding to the adjacent pixel electrode PX 2; and a second drain electrode D2 separated from the second source electrode S2 and electrically connected to the second subpixel electrode PXb through the second contact hole H2.

Different data voltages are applied to the first subpixel electrode PXa and the second subpixel electrode PXb through the first and second thin film transistors T1 and T2.

The first and second subpixel electrodes PXa and PXb of the pixel electrode PX1 belong to the same pixel area PA. Different data voltages corresponding to and complementary to the same image information are applied to the first and second subpixel electrodes PXa and PXb so as to display a high quality image. For example, the variation width of the voltage level (based on the common voltage Vcom) of the data voltage applied to the first subpixel electrode PXa may be larger or smaller than the variation width of the voltage level (based on the common voltage Vcom) of the data voltage applied to the second subpixel electrode PXb. Also, the data voltage applied to the first subpixel electrode PXa and the data voltage applied to the second subpixel electrode PXb may have opposite phase differences from each other. Fig. 14 shows an example in which the area of the first subpixel electrode PXa is designed to be larger than that of the second subpixel electrode PXb.

When the area of the second subpixel electrode PXb to which the higher data voltage is applied is smaller than that of the first subpixel electrode PXa, the side gamma bend may be made closer to the front gamma bend. In more detail, when the area ratio between the first subpixel electrode PXa and the second subpixel electrode PXb is about 2: 1 to 3: 1, the side gamma bend is closer to the front gamma bend, thereby improving the side visibility.

Therefore, different optical characteristics appear in the region where the first and second sub-pixel electrodes PXa and PXb are formed, and the visible light characteristics are complementary, so that the display quality can be further improved.

Meanwhile, as shown in fig. 14, the pixel electrode PX1 including the first and second sub-pixel electrodes PXa and PXb is formed to have an M shape in the pixel area PA, which is symmetrical in the longitudinal direction of the gate line GL 3. In addition, the adjacent data lines DL3, DL4 have a shape corresponding to the pixel electrode PX1, and the first sub-pixel electrode PXa overlaps the data lines DL3, DL 4. Preferably, the first subpixel electrode PXa completely overlaps the adjacent data lines DL3 and DL4 of the data line pair DL3/DL 4.

Generally, a unit pixel region is defined by a gate line and a data line. At this time, the data line overlaps with or is formed on an edge of the pixel region. In this case, it is difficult to maintain a predetermined interval between the pixel region and the data line in the process of forming the pattern.

Accordingly, in the lower display panel according to an exemplary embodiment of the present invention, the pixel electrode completely overlaps the data line, and thus a coupling error due to irregular intervals between the data line pair and the pixel electrode can be eliminated.

Fig. 15 is a block diagram illustrating an exemplary LCD to which the exemplary lower display panel illustrated in fig. 13 is applied. For simplicity, the data line pair connected to each pixel electrode PX is shown as a straight line. However, as shown in fig. 13 and 14, each data line pair is laid in a zigzag shape, and each pixel electrode PX overlaps the data line pair.

The LCD300 shown in fig. 15 includes a liquid crystal panel 310, a timing control mechanism 320, a gray voltage generator 330, a data driver 340, and a gate driver 350. Although the liquid crystal panel 310 is applied to the LCD300 shown in fig. 15, other elements of the LCD300 are also suitable for use in combination with a liquid crystal panel including the lower display panel of any of the foregoing embodiments.

The liquid crystal panel 310 may include the lower display panel 210 of fig. 13 and an upper display panel (not shown) facing the lower display panel 210.

The timing control mechanism 320 controls the image data signal R, G, B according to the time required by the data driver 340 and the gate driver 350, and outputs a controlled image data signal R, G, B. In addition, the timing control mechanism 320 outputs first and second control signals CNTL1 and CNTL2 for controlling the data driver 340 and the gate driver 350. Examples of the first control signal CNTL1 may include a horizontal synchronization start signal STH, a data output signal TP, and the like. And examples of the second control signal CNTL2 may include a scan start signal STV, a gate clock signal CPV, an enable output signal OE, and the like.

The gray voltage generator 330 generates a number of gray voltages related to the transfer of the pixel electrodes PX and supplies the generated gray voltages to the data driver 340 described below.

The data driver 340 drives the pair of data lines DL1/DL2, DL3/DL4 to DLm-1/DLm of the liquid crystal panel 310 in response to the first control signal CNTL1 supplied from the timing controller 320 and the gray voltages applied from the gray voltage generator 330.

The data driver 340 receives the first control signal CNTL1 and the image signal DAT for one pixel row from the timing control mechanism 320, and selects a gray voltage corresponding to each digital signal DAT among the gray voltages generated by the gray voltage generator 330. Thereafter, after the data driver 340 converts the selected gray voltages into corresponding data voltages, the data driver 340 supplies the data voltages to the corresponding pairs of data lines DL1/DL2, DL3/DL4 to DLm-1/DLm. As described above, the data voltages having opposite phase differences from each other and the voltages of different levels are applied to the data line pair.

The gate driver 350 drives the gate lines GL1 to GLn of the liquid crystal panel 310 in response to the second control signal CNTL2 input from the timing mechanism 320 and the on-voltage VON and off-voltage VOFF output from the driving voltage generator (not shown). The gate driver 350 supplies a gate voltage to the pixel electrodes PX through the gate lines GL1 to GLn, respectively, and turns "on or off" the first and second thin film transistors (T1, T2 shown in fig. 14) connected to each pixel electrode PX.

Fig. 16 is a waveform diagram of data voltages applied to each exemplary pixel electrode to perform an image pattern including a white pattern and a gray pattern.

Referring to fig. 16, the voltage waveform of the data line DL3 is a voltage waveform applied from the data driver 340 to the first subpixel electrode (PXa shown in fig. 13), and the voltage waveform of the data line DL4 is a voltage waveform applied from the data driver 340 to the second subpixel electrode (PXb shown in fig. 13).

As shown in fig. 13 and 16, it is preferable that the voltage waveforms of the data lines DL3, DL4 have opposite and varying phases to each other, so that the adjacent data line pair DL3/DL4 compensates for the coupling effect on the pixel electrodes PX 1. Thus, the coupling between each pixel electrode PX and the data line pairs DL1/DL2, DL3/DL4 to DLm-1/DLm can be completely eliminated.

Accordingly, each pixel electrode (particularly, the first sub-pixel electrode) completely overlaps the respective data line pair DL1/DL2, DL3/DL4 to DLm-1/DLm, thereby eliminating a coupling error between the data line pair and the pixel electrode PX. In addition, the data line pairs are respectively applied with data voltages, which fluctuate in directions to cancel each other out. Therefore, the coupling between the data line pair and the pixel electrode is eliminated.

As described above, according to the LCD according to the exemplary embodiments of the present invention, light leakage around the data line may be prevented and the aperture ratio may be increased. In addition, coupling capacitance between the sub-pixel electrode and the first and second data lines is reduced, thereby preventing degradation of display characteristics of the LCD. This prevents vertical crosstalk that may occur at low gray level levels.

In addition, a gap between the first and second subpixel electrodes may be blocked by the storage electrode to prevent light leakage.

In addition, the visibility of the LCD can be increased and a high aperture ratio can be obtained.

Although the present invention has been described in connection with the exemplary embodiments of the present invention, it will be understood by those skilled in the art that various modifications and changes may be made thereto without departing from the scope and spirit of the invention. Therefore, it should be understood that the above exemplary embodiments are not restrictive but illustrative in all aspects.

Claims (28)

1. A liquid crystal display, comprising:

a first insulating substrate;

a gate wiring formed on the first insulating substrate and extending in a first direction;

a data wire insulated from and crossing the gate wire, the data wire extending in a second direction;

pixel electrodes each including first and second sub-pixel electrodes to which different data voltages are applied from the data wiring; and

two switching elements, the first and second sub-pixel electrodes being connected to the switching elements, respectively,

wherein,

the first subpixel electrode does not overlap the data wiring,

the liquid crystal display further includes a common electrode facing the pixel electrodes and applied with a common voltage,

wherein, for each pixel electrode, a difference between a common voltage and a data voltage applied to the first subpixel electrode is higher than a difference between a common voltage and a data voltage applied to the second subpixel electrode,

wherein, for each pixel electrode, the second sub-pixel electrode completely overlaps the corresponding data wiring in a width direction of the data wiring.

2. The liquid crystal display according to claim 1, wherein, for each pixel electrode, the data voltage applied to the first subpixel electrode is higher than the data voltage applied to the second subpixel electrode.

3. The liquid crystal display according to claim 1, wherein the first sub-pixel electrode comprises a V-shape for each pixel electrode, and the second sub-pixel electrode is formed in a region of the pixel other than the first sub-pixel electrode.

4. The liquid crystal display according to claim 1, wherein the second sub-pixel electrode is formed to surround the first sub-pixel electrode for each pixel electrode.

5. The liquid crystal display of claim 4, wherein, for each pixel electrode:

the second sub-pixel electrode includes a main region substantially inclined by about 45 ° or about-45 ° toward the data wiring and a bridge region disposed along and overlapping the data wiring, and the bridge region is connected to the main region.

6. The liquid crystal display according to claim 1, wherein the data wiring includes, for each pixel electrode, first and second data lines that supply different data voltages to the first and second sub-pixel electrodes, respectively.

7. The liquid crystal display of claim 6, wherein first type pixels each having a first sub-pixel electrode supplied with a data voltage from a first data line and second type pixels each having a first sub-pixel electrode supplied with a data voltage from a second data line are alternately arranged in first and second directions.

8. The liquid crystal display of claim 1, further comprising:

a storage line and a storage electrode formed on the first insulating substrate and extending substantially parallel to the gate wiring;

and an auxiliary storage electrode connected to the storage line and extending substantially parallel to the data wiring.

9. The liquid crystal display of claim 8, wherein a gap separating the first and second sub-pixel electrodes from each other in each pixel electrode partially overlaps the auxiliary storage electrode.

10. The liquid crystal display of claim 9, wherein, for each pixel electrode, the first sub-pixel electrode overlaps at least a portion of the auxiliary storage electrode.

11. The liquid crystal display according to claim 10, wherein the auxiliary storage electrode and the first subpixel electrode overlap each other by a width in a range of about 1 μm to about 3 μm.

12. The liquid crystal display of claim 1, further comprising:

a second insulating substrate facing the first insulating substrate;

a common electrode formed on the second insulating substrate; and

a liquid crystal layer interposed between the first and second insulating substrates, and the liquid crystal layer includes liquid crystal molecules.

13. The liquid crystal display according to claim 1, further comprising a passivation layer formed of an organic material, and interposed between the data wiring and the pixel electrode.

14. A liquid crystal display, comprising:

gate and data wirings insulated from each other on the insulating substrate and crossing each other;

a pair of first and second thin film transistors connected to the gate wiring and the data wiring;

pixel electrodes each including a first sub-pixel electrode connected to the first thin film transistor; and a second sub-pixel electrode surrounding the first sub-pixel electrode, spaced apart from the first sub-pixel electrode by a gap, and connected to the second thin film transistor;

a first storage line overlapping the first subpixel electrode and receiving a first storage voltage; and

a second storage line overlapping the second sub-pixel electrode and receiving a second storage voltage different from the first storage voltage,

wherein

The first subpixel electrode does not overlap the data wiring,

the liquid crystal display further includes a common electrode facing the pixel electrodes and applied with a common voltage,

wherein, for each pixel electrode, a difference between a common voltage and a data voltage applied to the first subpixel electrode is higher than a difference between a common voltage and a data voltage applied to the second subpixel electrode,

wherein, for each pixel electrode, the second sub-pixel electrode completely overlaps the corresponding data wiring in a width direction of the data wiring.

15. The liquid crystal display of claim 14, wherein the second storage voltage is inverted from the first storage voltage.

16. The liquid crystal display according to claim 14, wherein the same data voltage applied from the data wiring to the first and second sub-pixel electrodes becomes different from each other due to coupling between the same data voltage and the first and second storage voltages.

17. The liquid crystal display of claim 14, further comprising:

a storage electrode branched from the first storage line and overlapping the gap.

18. The liquid crystal display according to claim 17, wherein the storage electrode extends substantially parallel to the data wiring.

19. The liquid crystal display according to claim 14, further comprising a passivation layer formed of an organic material, and interposed between the data wiring and the first and second sub-pixel electrodes.

20. A liquid crystal display, comprising:

a gate line;

a pair of data lines insulated from and crossing the gate lines;

a pixel electrode which is provided on the substrate,

wherein each of the pixel electrodes includes a first sub-pixel electrode and a second sub-pixel electrode having an area larger than that of the first sub-pixel electrode,

wherein the two switching elements, the first and second sub-pixel electrodes are connected to the switching elements respectively,

the first subpixel electrode does not overlap the data line pair,

the liquid crystal display further includes a common electrode facing the pixel electrodes and applied with a common voltage,

wherein, for each pixel electrode, a difference between a common voltage and a data voltage applied to the first subpixel electrode is higher than a difference between a common voltage and a data voltage applied to the second subpixel electrode,

wherein, for each pixel electrode, the second sub-pixel electrode completely overlaps the corresponding data line pair in a width direction of the data line pair.

21. The liquid crystal display of claim 20, wherein:

each of the pixel electrodes has a bending center bent in a first direction parallel to the gate line, and each of the pixel electrodes is symmetrical with respect to the bending center, and

both ends of each pixel electrode are bent in a second direction opposite to the first direction based on the bending center.

22. The liquid crystal display of claim 21, wherein each of the data line pairs has a shape corresponding to a shape of each of the pixel electrodes.

23. The liquid crystal display of claim 21, wherein each of the data line pairs is formed in a zigzag shape.

24. The liquid crystal display of claim 20, the two switching elements being:

and first and second thin film transistors for respectively supplying two data voltages from the data line pair to the first and second sub-pixel electrodes.

25. The liquid crystal display of claim 24, wherein the two data voltages have opposite phases to each other.

26. The liquid crystal display of claim 24, wherein the two data voltages have different voltage levels.

27. The liquid crystal display of claim 20, further comprising a passivation layer formed of an organic material, and the passivation layer is interposed between the pair of data lines and the pixel electrode.

28. A method for improving display quality of a liquid crystal display having a matrix of pixel regions, the method comprising:

forming a gate wiring on an insulating substrate, the gate wiring extending substantially in a first direction;

forming a data wire insulated from the gate wire, the data wire extending substantially in a second direction, the second direction being substantially perpendicular to the first direction;

forming first and second sub-pixel electrodes and two switching elements connected to the first and second sub-pixel electrodes, respectively, within each pixel region, the second sub-pixel electrode at least partially surrounding the first sub-pixel electrode and having a larger area than the first sub-pixel electrode; and

applying a data voltage to the first subpixel electrode, the data voltage being greater than a data voltage applied to the second subpixel electrode,

wherein the first subpixel electrode does not overlap the data wiring,

the liquid crystal display further includes a common electrode facing the pixel electrodes and applied with a common voltage,

wherein, for each pixel electrode, a difference between a common voltage and a data voltage applied to the first subpixel electrode is higher than a difference between a common voltage and a data voltage applied to the second subpixel electrode,

wherein, for each pixel electrode, the second sub-pixel electrode completely overlaps the corresponding data wiring in a width direction of the data wiring.

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