KR101288998B1 - Display substrate - Google Patents

Abstract

In the display substrate, the display substrate includes a plurality of gate lines, a plurality of data line pairs, and a plurality of pixel electrodes. The data line pairs have a shape corresponding to the pixel electrode. Each pixel electrode includes a first subpixel electrode and a second subpixel electrode. The data line pairs are formed to overlap the first subpixel electrode.

Numerical aperture, coupling

Description

 Display board {DISPLAY SUBSTRATE}

BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the drawings used in the detailed description of the present invention, a brief description of each drawing is provided.

1 illustrates a portion of a display substrate according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating in detail the structure of one pixel electrode PX shown in FIG. 1.

3 is a diagram illustrating an example of a liquid crystal display device to which the display substrate illustrated in FIG. 1 is applied.

4 is a waveform of a data voltage applied to each pixel electrode to implement an image pattern consisting of a white pattern and a gray pattern.

The present invention relates to a display substrate, and more particularly, to a display substrate having a structure capable of improving display quality.

A liquid crystal display device is a display device using a liquid crystal having an intermediate state property of a liquid and a solid. The liquid crystal display device is provided with two transparent substrates, and the liquid crystal is arranged between the two transparent substrates. The liquid crystal has dielectric anisotropy and the arrangement of the liquid crystal is changed when an electric field is applied. The liquid crystal also has refractive index anisotropy, and transmittance with respect to light varies depending on the arrangement state.

The liquid crystal display applies an appropriate electric field to the liquid crystal so that the liquid crystal has a transmittance corresponding to the image information, and when the arrangement of the liquid crystal is changed according to the electric field, light is provided to the liquid crystal to display a corresponding image.

For the above operation, various conductive film patterns are formed on the two transparent substrates. Some of the conductive layer patterns are made of a component that blocks the transmission of light.

Due to the conductive layer patterns, the aperture ratio of the liquid crystal display is lowered and the area in which an image can be displayed in the liquid crystal display is reduced. Therefore, the display quality of the liquid crystal display device is lowered.

In addition, a coupling deviation occurs between the data line and the pixel electrode formed on the transparent substrate, thereby lowering the display quality of the liquid crystal display.

Accordingly, it is an object of the present invention to provide a display substrate which reduces the aperture ratio and reduces the coupling deviation between the data line and the pixel electrode.

In order to achieve the above technical problem, the display substrate of the present invention includes a plurality of gate lines, a plurality of data line pairs, and a plurality of pixel electrodes electrically connected to the plurality of gate lines and the plurality of data line pairs. Include. The semiconductor device may further include a first thin film transistor and a second thin film transistor that electrically connect each pixel electrode and one data line pair. The data line pairs electrically insulate and cross the plurality of gate lines. Each of the plurality of pixel electrodes includes a first subpixel electrode and a second subpixel electrode. The second subpixel electrode has an area smaller than that of the first subpixel electrode. Two adjacent data lines of the data lines overlap the first subpixel electrode.

In order to fully understand the present invention, operational advantages of the present invention, and objects achieved by the practice of the present invention, reference should be made to the accompanying drawings and the accompanying drawings which illustrate preferred embodiments of the present invention. In understanding each of the figures, it should be noted that like parts are denoted by the same reference numerals whenever possible. In addition, in the following description, numerous specific details such as specific processing flows are described to provide a more general understanding of the present invention. Further, detailed descriptions of known functions and configurations that may be unnecessarily obscured by the gist of the present invention are omitted.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings.

1 illustrates a portion of a display substrate according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a display substrate 10 according to an exemplary embodiment of the present invention may include a base substrate 12, a plurality of gate lines GL1,... GLn, and a plurality of data line pairs DL1 / DL2, DL3 /. DL4, DL5 / DL6, ... DLm-1 / DLm), and a plurality of pixel electrodes PX. In addition, the display substrate 10 of the present invention further includes a first switching element T1 and a second switching element T2 that provide two data voltages having different polarities to each pixel electrode.

The base substrate 10 is a transparent insulating substrate and includes a plurality of pixel areas PA arranged in a matrix form. A plurality of gate lines GL1, .., GLn and a plurality of data line pairs DL1 / DL2, DL3 / DL4, DL5 / DL6, DLm-1 / DLm are formed on the base substrate 12. Are wired. The plurality of gate lines GL1 to GLn extend in a first direction D1 and are formed in a second direction D2. The plurality of data lines DL1 / DL2, DL3 / DL4, DL5 / DL6, ... DLm-1 / DLm are insulated from and intersected with the gate lines GL1,. D2) is formed in the first direction D1.

The data line pairs DL1 / DL2, DL3 / DL4, DL5 / DL6, ... DLm-1 / DLm form groups of two adjacent data lines and overlap one pixel area PA. To have a zigzag shape repeated in the second direction D2 to have a 'M' shape.

Each of the plurality of pixel electrodes PX is disposed on a plurality of pixel areas PA arranged in a matrix, and each pixel electrode PX is sequentially formed in a second direction D2. PXa) and second subpixel electrode PXb. In addition, a first thin film transistor T1 and a second thin film transistor T2 are further included in the pixel area together with the pixel electrode.

FIG. 2 is a diagram illustrating in detail the structure of one pixel electrode PX shown in FIG. 1.

Referring to FIG. 2, the pixel electrode PX includes a first subpixel electrode PXa and a second subpixel electrode PXb. The pixel electrode PX has a center bent in a left direction parallel to the gate line GL3, and is symmetrical with respect to the bent center, and both ends of the pixel electrode with respect to the bent center are disposed at the pixel electrode. The centers of the are respectively bent in the right direction opposite to the bent direction.

Two data lines DL3 and DL4 adjacent to the pixel electrode are wired in the first direction D1. Therefore, the data line pairs DL3 and DL4 are wired to overlap each pixel electrode PX. The data lines DL3 and DL4 receive different data voltages and are applied to the pixel electrode PX.

The first thin film transistor T1 is formed from the gate line GL3 and the data line DL4, and the first subpixel electrode PXa is connected to the first thin film transistor T1. The first thin film transistor T1 is spaced apart from the first gate electrode G1 branched from the gate line GL3, the first source electrode S1 branched from the data line DL4, and the first source electrode S1. The first drain electrode D1 is electrically connected to the first subpixel electrode PXa through the first contact hole H1.

In the second thin film transistor T2, a second thin film transistor T2 is formed from the gate line GL3 and the data line DL5. Here, it should be noted that the data line DL5 is a data line DL5 wired corresponding to an adjacent pixel electrode ('PX2' illustrated in FIG. 1). The second subpixel electrode PXb is electrically connected to the second thin film transistor T2.

The second thin film transistor T2 is the second gate electrode G2 branched from the gate line GL3 and the second source electrode S2 branched from the data line DL5 wired corresponding to the adjacent pixel electrode PX2. And a second drain electrode D2 spaced apart from the second source electrode S2 and electrically connected to the second subpixel electrode PXb through the second contact hole H2.

Different data voltages are applied to the first subpixel electrode PXa and the second subpixel electrode PXb through the first and second thin film transistors T1 and T2.

The first and second subpixel electrodes PXa and PXb belong to the same pixel region, and different voltages are applied to the electrodes PXa and PXb to correspond to the same image information, but are complemented with each other to display a high quality image. do. For example, the swing width of the voltage level (based on the common voltage) of the data voltage applied to the first subpixel electrode PXa is based on the level of the data voltage applied to the second subpixel electrode PXb (based on the common voltage). Is greater than or less than the swing width. In addition, they have opposite phase differences. 2 illustrates an example in which the area of the first subpixel electrode PXa is designed to be larger than the area of the second subpixel electrode PXa.

When the area of the first subpixel electrode PXa to which a high voltage is applied is smaller than the area of the second subpixel electrode PXb, the side gamma curve may be closer to the front gamma curve. In particular, when the area ratios of the first and second subpixel electrodes PXa and PXb are approximately 1: 2 to 1: 3, the side gamma curve becomes closer to the front gamma curve, thereby improving side visibility.

Thus, different optical characteristics are exhibited in the region where the first subpixel electrode and the second subpixel electrode PXa and PXb are formed, and these are compensated to provide more improved display quality.

Meanwhile, as illustrated in FIG. 2, the pixel electrode including the first subpixel electrode and the second subpixel electrode is formed in an M shape that is symmetrical with respect to the longitudinal direction of the gate line GL3. Adjacent data lines DL3 and DL4 have a shape corresponding to the pixel electrode PX and overlap the first subpixel electrode PXa. Preferably, the adjacent data lines are formed to completely overlap the first subpixel electrode PXa.

In general, a unit pixel area is defined by a gate line and a data line. In this case, the data lines may be formed to overlap the edge of the pixel electrode, or may be formed outside the edge of the pixel area. In this case, it is difficult to maintain a constant gap between the pixel electrode and the data line in the pattern formation process.

Therefore, in the display substrate according to the present invention, by completely overlapping the data lines on the pixel electrode, the coupling deviation caused by the nonuniform spacing between the pair of data lines and the pixel electrode can be eliminated.

3 is a diagram illustrating an example of a liquid crystal display device to which the display substrate illustrated in FIG. 1 is applied. For the sake of simplicity, the data line pairs connected to each pixel electrode PX are shown as straight lines, but each data line pair is wired in a zigzag shape as shown in FIGS. 1 and 2, and overlaps each pixel electrode. It is formed to be.

The liquid crystal display 100 shown in FIG. 3 includes a liquid crystal display panel 110, a timing controller 120, a gray voltage generator 130, a data driver 140, and a gate driver 150.

The liquid crystal display panel 100 includes the display substrate 10 described above, and may further include a color filter substrate facing the display substrate.

The timing controller 120 adjusts and outputs the image data signals R, G, and B to match the timing required by the data driver 140 and the gate driver 150. In addition, the timing controller 200 outputs first and second control signals CNTL1 and CNTL2 for controlling the data driver 400 and the gate driver 500. The first control signal CNTL1 includes a horizontal synchronization start signal STH, a data output signal TP, and the like. The second control signal CNTL2 includes a scan start signal STV, a gate clock signal CPV, an output enable signal OE, and the like.

The gray voltage generator 130 generates a plurality of gray voltages related to the transmittance of the pixel electrode PX and provides them to the data driver 140 described below.

The data driver 400 responds to the first control signal CNTL1 applied from the timing controller 200 and the gray voltage applied from the gray voltage generator 300 to pair the data line of the liquid crystal display panel 100. Drives DL1 / DL2, DL3 / DL4, ... DLm-1 / DLm.

The data driver 140 receives the first control signal CNTL1 and the image signal DAT for one pixel row from the timing controller 200, and outputs each image signal among the gray voltages generated by the gray voltage generator 300. Select the gradation voltage corresponding to (DAT). Subsequently, the data driver 140 converts the selected gray voltage into a corresponding data voltage and then applies it to the corresponding data line pairs D1 / D2, D2 / D3, ..., Dm-1 / Dm. . As described above, data voltages having opposite phase differences and voltage levels having different magnitudes are applied to each data line pair.

The gate driver 150 responds to the second control signal CNTL2 input from the timing controller 120 and the gate on voltage VON and the gate off voltage VOFF output from the driving voltage generator (not shown). The gate lines G1 to Gn of the liquid crystal display panel 100 are driven. The gate driver 150 applies gate voltages to the pixel electrodes PX through the gate lines G1 to Gn, so that the first and second thin film transistors connected to the pixel electrodes PX are illustrated in FIG. 2. T1, T2) 'turns on' or 'turns off'.

4 is a waveform of a data voltage applied to each pixel electrode to implement an image pattern consisting of a white pattern and a gray pattern.

Referring to FIG. 4, the voltage waveform of DL3 is a voltage waveform applied from the data driver 140 to the first subpixel electrode (PXa of FIG. 1), and the voltage waveform of DL4 is a second waveform from the data driver 140. It is the voltage waveform applied to the electrode (PXb of FIG. 1).

As shown in FIG. 4, the voltage waveforms of DL3 and DL4 swing in a direction that exactly cancels the coupling with the pixel electrode PX1. Therefore, the generated coupling between the pixel electrode and the data line pair can be completely eliminated.

As a result, each pair of data lines DL1 / DL2, DL3 / DL4, DL5 / DL6, ... DLm-1 / DLm completely overlaps each pixel electrode (specifically, the first subpixel electrode), whereby the data line Coupling deviation between the pair and the pixel electrode PX is eliminated. Each overlapped pair of data lines receives a data voltage swinging in a direction canceling each other. Therefore, the coupling between the data line pair and the pixel electrode is eliminated.

The display substrate of the present invention as described above includes a plurality of pixel electrodes having a 'M' shape which is symmetrical with respect to the longitudinal direction of the gate line. Each data line pair is formed in a zigzag shape so as to completely overlap each pixel electrode.

Therefore, the display substrate of the present invention completely eliminates the aperture ratio and the coupling deviation between the pixel electrode and the data line.

As described above, an optimal embodiment has been disclosed in the drawings and specification. Although specific terms have been employed herein, they are used for purposes of illustration only and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (7)

A pair of data lines insulated from and intersecting the gate line and the gate line; And A pixel electrode electrically connected to the gate line and the data line pair, respectively; The pixel electrode, A first subpixel electrode; And A second subpixel electrode having an area smaller than that of the first subpixel electrode, wherein the pair of data lines are formed to overlap the first subpixel electrode, The data line pair has a shape corresponding to the pixel electrode and completely overlaps the first subpixel electrode. The method of claim 1, The center of the pixel electrode is bent in a first direction parallel to the direction in which the gate line extends, and both end portions of the pixel electrode are symmetrical with respect to the center of the pixel electrode, and both end portions of the pixel electrode The display substrate of claim 1, wherein the display substrate is bent in a second direction opposite to the first direction and parallel to a direction in which the gate line extends. delete The method of claim 2, The data line pair is formed in a zigzag shape and completely overlaps the first subpixel electrode. The method of claim 1, And a first thin film transistor and a second thin film transistor which respectively provide two data voltages from the pair of data lines to the first subpixel electrode and the second subpixel electrode. 6. The method of claim 5, And the two data voltages have opposite phases to each other. 6. The method of claim 5, And the two data voltages are voltage levels of different magnitudes.

Images