KR20190141510A - Display device having a intermediate supply line disposed adjacent to a pixel area, and Method for fabricating the same - Google Patents

Abstract

The present invention relates to a display device in which an intermediate supply line is located on a wiring region adjacent to a pixel region. The intermediate supply line may supply a specific voltage, for example, a common voltage, to pixels positioned in the pixel region. The intermediate supply line may have a lower reflectance than a gate electrode of a thin film transistor positioned in the pixel region. Accordingly, in the display device according to an embodiment of the present invention, the reflectance of the intermediate supply line may be reduced. Therefore, in the display device according to an embodiment of the present invention, the deterioration of an image implemented by the light reflected from the wiring region may be minimized.

Description

Display device having a intermediate supply line disposed adjacent to a pixel area, and Method for fabricating the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device in which an intermediate supply wiring for supplying a specific voltage to each pixel located in the pixel region is located on a wiring region adjacent to the pixel region, and a manufacturing method thereof.

In general, electronic devices such as a monitor, a TV, a notebook, a digital camera, and the like include a display device for implementing an image. For example, the display device may include a liquid crystal display and / or an organic light emitting display.

The display device may include a plurality of pixels to implement an image according to a user's request. Each pixel may include a thin film transistor and a pixel electrode electrically connected to the thin film transistor. The display device may further include at least one driving driver for generating a signal for controlling each pixel, for example, controlling the thin film transistor.

The driving driver may be located outside the pixel area in which the plurality of pixels are located. A wiring area may be disposed between the driving driver and the pixel area in which wirings for transmitting a signal for controlling each pixel are formed. For example, an intermediate supply wiring for supplying a specific voltage, such as a common voltage, to each pixel may be positioned on the wiring area.

The intermediate supply wiring may include a material having high conductivity. The intermediate supply wiring may be formed using a process of forming the thin film transistor. For example, the intermediate supply wiring may include the same metal as the gate electrode of the thin film transistor. However, in the display device, as the intermediate supply line has a high reflectance, light incident on the wiring area may be reflected by the intermediate supply line, thereby degrading an image quality. For example, in a liquid crystal display device in which light is supplied from a backlight unit to a liquid crystal panel, light reflected from the wiring area of the liquid crystal panel may be reflected back by the optical sheet of the backlight unit, thereby preventing reflection of the intermediate supply wiring. As a result, bright lines may be generated at edges of the pixel area.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device and a method of manufacturing the same, which can minimize the deterioration of the quality of an image implemented by reflection of a wiring area.

The problem to be solved by the present invention is not limited to the above-mentioned problem. Tasks not mentioned here will be apparent to those skilled in the art from the following description.

The display device according to the spirit of the present invention for achieving the above object includes an array substrate. The array substrate includes a pixel region and a wiring region. The wiring area is located adjacent to the pixel area. A plurality of pixels are positioned on the pixel area of the array substrate. Each pixel includes a thin film transistor and a pixel electrode. The pixel electrode of each pixel is electrically connected to the thin film transistor of the pixel. The intermediate supply wiring and the dummy electrode pattern are positioned on the wiring area of the array substrate. The intermediate supply wiring delivers a specific voltage or signal to each pixel. The dummy electrode pattern is located on the same layer as the pixel electrode. The intermediate wiring has higher conductivity than the dummy electrode pattern and lower reflectance than the gate electrode of the thin film transistor.

The intermediate supply wiring may include a region overlapping the dummy electrode pattern.

The bottom surface of the pixel electrode facing the array substrate may be coplanar with the bottom surface of the gate electrode facing the array substrate.

The gate electrode may have a stacked structure of a first electrode layer and a second electrode layer. The first electrode layer of the gate electrode may include the same material as the pixel electrode. The second electrode layer of the gate electrode may have a higher conductivity than the first electrode layer of the gate electrode.

The source electrode of the thin film transistor may have a lower reflectance than the gate electrode of the thin film transistor. The intermediate supply wiring may have the same structure as the source electrode of the thin film transistor.

The source electrode of the thin film transistor may have a stacked structure of a first electrode layer and a second electrode layer. The second electrode layer of the source electrode may have a higher conductivity than the first electrode layer of the source electrode.

Each pixel may further include a common electrode including at least one slit overlapping the corresponding pixel electrode. The common electrode may be connected with the intermediate supply wiring.

Each pixel may further include a planarization layer positioned between the pixel electrode and the common electrode. The gate insulating film of the thin film transistor may extend between the pixel electrode and the planarization film.

Each pixel may further include pixel connection wirings connecting the thin film transistor and the pixel electrode. The pixel connection line may include the same material as the common electrode.

The common voltage supply wiring and the intermediate connection wiring may be positioned on the wiring area of the array substrate. The intermediate connection wiring may connect the intermediate supply wiring with the common voltage supply wiring. The common voltage supply wiring may have the same structure as the gate electrode of the thin film transistor.

The dummy semiconductor pattern may be positioned between the dummy electrode pattern and the intermediate supply wiring.

The dummy semiconductor pattern may include the same material as the semiconductor pattern of the thin film transistor.

In the display device and the method of manufacturing the same according to the spirit of the present invention, the intermediate supply wiring located on the wiring area adjacent to the pixel area may have a lower reflectance than the gate electrode of the thin film transistor located in the pixel area. Accordingly, in the display device and the manufacturing method thereof according to the spirit of the present invention, it is possible to minimize the re-introduction of light supplied to the wiring area from the backlight unit or the outside into the pixel area. Therefore, in the display device and the method of manufacturing the same according to the spirit of the present invention, the quality of the image to be implemented may be improved.

1 is a view schematically illustrating a display device according to an exemplary embodiment of the present invention.
FIG. 2 is an enlarged view of region P of FIG. 1.
3 is a view taken along the line II ′ of FIG. 2.
4 and 5 are views showing a display device according to another embodiment of the present invention, respectively.
6 to 11 are views sequentially showing a method of manufacturing a display device according to an embodiment of the present invention.

Details of the above objects, technical configurations, and effects according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing embodiments of the present invention. Here, since the embodiments of the present invention are provided to sufficiently convey the technical spirit of the present invention to those skilled in the art, the present invention may be embodied in other forms so as not to be limited to the embodiments described below.

In addition, parts denoted by the same reference numerals throughout the specification means the same components, in the drawings the length and thickness of the layer or region may be exaggerated for convenience. In addition, when the first component is described as being "on" a second component, the first component is located above and in direct contact with the second component, as well as the first component and the It also includes the case where the third component is located between the second components.

Here, the terms "first" and "second" are used to describe various components, and are used for the purpose of distinguishing one component from other components. However, the first component and the second component may be arbitrarily named for convenience of those skilled in the art without departing from the technical spirit of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. For example, a component expressed in the singular includes a plural component unless the context clearly indicates the singular. Also, in the context of the present invention, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof described on the specification, or one or It should be understood that no other features or numbers, steps, actions, components, parts, or combinations thereof are excluded in advance.

In addition, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and, unless expressly defined in the specification of the present invention, in ideal or excessively formal meanings. Not interpreted.

(Example)

1 is a view schematically illustrating a display device according to an exemplary embodiment of the present invention. FIG. 2 is an enlarged view of region P of FIG. 1. 3 is a view taken along the line II ′ of FIG. 2.

1, 2, and 3, a display device according to an embodiment of the present invention may include an array substrate 110. The array substrate 110 may include an insulating material. The array substrate 110 may include a transparent material. For example, the array substrate 110 may include plastic or glass.

The array substrate 110 may include a display area AA. The display area AA may implement an image according to a user's request. At least one driving driver 10, 20, 30 for generating a signal for realizing an image may be located outside the display area AA. For example, a data driver 10 generating a data signal, a gate driver 20 generating a gate signal, and a common voltage supply source 30 generating a common voltage may be located outside the display area AA. have.

The display area AA may include a pixel area PA and a wiring area LA. A gate line GL transferring the gate signal and a data line DL transferring the data signal may be located in the pixel area PA. The data line DL may cross the gate line GL. For example, a plurality of pixels defined by the gate line GL and the data line DL may be located in the pixel area PA.

Each pixel may include a driving thin film transistor TR. The driving thin film transistor TR may be controlled by the gate signal and the data signal. For example, the driving thin film transistor TR may include a driving gate electrode 210, a driving gate insulating layer 220, a driving semiconductor pattern 230, a driving source electrode 240, and a driving drain electrode 250. have.

The driving gate electrode 210 may be located close to the array substrate 110. For example, the driving gate electrode 210 may directly contact the array substrate 110. The driving gate electrode 210 may include a conductive material. The driving gate electrode 210 may have a multilayer structure. For example, the driving gate electrode 210 may have a stacked structure of the transparent gate electrode layer 211 and the high conductivity gate electrode layer 212.

The transparent gate electrode layer 211 may have a higher transmittance than the high conductivity gate electrode layer 212. For example, the transparent gate electrode layer 211 may include ITO or IZO. The high conductivity gate electrode layer 212 may have a higher conductivity than the transparent gate electrode layer 211. For example, the high conductivity gate electrode layer 212 may include a metal such as aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W).

The driving gate electrode 210 may be electrically connected to the gate line GL. The gate line GL may have the same structure as the driving gate electrode 210. For example, the driving gate electrode 210 may have a shape protruding from the gate line GL extending in one direction.

The driving gate insulating layer 220 may be located on the driving gate electrode 210. The driving gate insulating layer 220 may extend in an outward direction of the driving gate electrode 210. For example, the side surface of the driving gate electrode 210 may be covered by the driving gate insulating layer 220.

The driving gate insulating layer 220 may include an insulating material. For example, the driving gate insulating layer 220 may include silicon oxide and / or silicon nitride. The driving gate insulating layer 220 may include a high-k material. For example, the driving gate insulating layer 220 may include hafnium oxide (HfO) or titanium oxide (TiO).

The driving semiconductor pattern 230 may be located on the driving gate insulating layer 220. The driving semiconductor pattern 230 may overlap the driving gate electrode 210. For example, the driving semiconductor pattern 230 may be insulated from the driving gate electrode 210 by the driving gate insulating layer 220.

The driving semiconductor pattern 230 may include a semiconductor material. For example, the driving semiconductor pattern 230 may include amorphous silicon or polycrystalline silicon. The driving semiconductor pattern 230 may be an oxide semiconductor. For example, the driving semiconductor pattern 230 may include IGZO.

The driving semiconductor pattern 230 may include a source region, a drain region, and a channel region. The channel region may be located between the source region and the drain region. The channel region may have a lower conductivity than the source region and the drain region. For example, the source region and the drain region may include conductive impurities.

The driving source electrode 240 may be electrically connected to the source region of the driving semiconductor pattern 230. For example, the driving source electrode 240 may directly contact the source region of the driving semiconductor pattern 230.

The driving source electrode 240 may include a conductive material. For example, the driving source electrode 240 may include metals such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). The driving source electrode 240 may have a lower reflectance than the driving gate electrode 210. For example, the driving source electrode 240 may have a stacked structure of the low reflection source electrode layer 241 and the high conductivity source electrode layer 242.

The low reflection source electrode layer 241 may be located close to the driving gate insulating layer 220. For example, the low reflection source electrode layer 241 may be located between the driving gate insulating layer 220 and the high conductivity source electrode layer 242. The low reflection source electrode layer 241 may have a lower reflectance than the high conductivity source electrode layer 242. The high conductivity source electrode layer 242 may have a higher conductivity than the low reflection source electrode layer 241.

The driving source electrode 240 may be electrically connected to the data line DL. The data line DL may include the same material as the driving source electrode 240. For example, the driving source electrode 240 may have a shape protruding from the data line DL extending in one direction.

The driving drain electrode 250 may be electrically connected to the drain region of the driving semiconductor pattern 230. For example, the driving drain electrode 250 may directly contact the drain region of the driving semiconductor pattern 230. The driving drain electrode 250 may be spaced apart from the driving source electrode 240. For example, the driving source electrode 240 and the driving drain electrode 250 may expose the channel region of the driving semiconductor pattern 230.

In the display device according to an exemplary embodiment, a portion of the driving semiconductor pattern 230 is exposed by the driving source electrode 240 and the driving drain electrode 250. However, the display device according to another exemplary embodiment may include an etch stopper disposed on the driving semiconductor pattern 230. The etch stopper may prevent damage to the driving semiconductor pattern 230 by a manufacturing process. For example, in the display device according to another exemplary embodiment, a portion of the etch stopper may be exposed by the driving source electrode 240 and the driving drain electrode 250.

The driving drain electrode 250 may include a conductive material. For example, the driving drain electrode 250 may include metals such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), and tungsten (W). The driving drain electrode 250 may have the same structure as the driving source electrode 240. For example, the driving drain electrode 250 may have a stacked structure of the low reflection drain electrode layer 251 and the high conductivity drain electrode layer 252. The low reflection drain electrode layer 251 may include the same material as the low reflection source electrode layer 241. The high conductivity drain electrode layer 252 may include the same material as the high conductivity source electrode layer 242. For example, the driving drain electrode 250 may have the same reflectance as the driving source electrode 240.

The planarization layer 120 may be positioned on the driving thin film transistor TR. The step by the driving thin film transistor TR may be removed by the planarization layer 120. For example, an upper surface of the planarization layer 120 facing the array substrate 110 may be a flat plane. The planarization layer 120 may include an insulating material. For example, the planarization layer 120 may include an organic insulating material.

Each pixel may further include a pixel electrode 300 electrically connected to the driving thin film transistor TR. For example, the pixel electrode 300 may be electrically connected to the driving drain electrode 250 of the driving thin film transistor TR. The pixel electrode 300 may be located close to the array substrate 110. For example, the pixel electrode 300 may be positioned between the array substrate 110 and the planarization layer 120. The planarization layer 120 may include at least one contact hole exposing a portion of the driving drain electrode 250 and a portion of the pixel electrode 300.

The pixel electrode 300 may not overlap the driving gate electrode 210, the driving semiconductor pattern 230, the driving source electrode 240, and the driving drain electrode 250. have. The pixel electrode 300 may be spaced apart from the driving gate electrode 210, the driving semiconductor pattern 230, the driving source electrode 240, and the driving drain electrode 250. For example, the pixel electrode 300 may be positioned outside the driving gate electrode 210, the driving semiconductor pattern 230, the driving source electrode 240, and the driving drain electrode 250.

The lower surface of the pixel electrode 300 facing the array substrate 110 may be coplanar with the lower surface of the gate electrode 210 facing the array substrate 110. For example, the pixel electrode 300 may directly contact the array substrate 110. The driving gate insulating layer 220 may extend between the pixel electrode 300 and the planarization layer 120. The driving gate insulating layer 220 may include at least one contact hole exposing a portion of the pixel electrode 300 positioned in the contact hole of the planarization layer 120.

The pixel electrode 300 may include a conductive material. The pixel electrode 300 may include a transparent material. For example, the pixel electrode 300 may include ITO or IZO. The pixel electrode 300 may include the same material as the transparent gate electrode layer 211 of the driving gate electrode 210.

The common electrode 400 may be positioned on the planarization layer 120. The common electrode 400 may form a horizontal electric field with the pixel electrode 300. For example, in the display device according to the exemplary embodiment, an IPS in which an array substrate 110 on which a driving thin film transistor TR, a pixel electrode 300, and a common electrode 400 are formed is disposed between a backlight unit and a liquid crystal layer. It may be a liquid crystal display device of the type. The common electrode 400 may include at least one slit overlapping the pixel electrode 300.

The common electrode 400 may include a conductive material. The common electrode 400 may include a transparent material. For example, the common electrode 400 may include ITO or IZO.

The common electrodes 400 of pixels adjacent to one side may be connected to each other. For example, the common electrode 400 may extend in a direction parallel to the gate line GL. The driving thin film transistor TR may be located outside the common electrode 400. For example, the thin film transistor TR of each pixel may not overlap the common electrode 400.

The pixel connection line 500 may be positioned on the planarization layer 120. The pixel connection wire 500 may electrically connect between the driving thin film transistor TR and the pixel electrode 300 through a contact hole of the planarization layer 120 and a contact hole of the driving gate insulating layer 220. have.

The pixel connection line 500 may include a conductive material. The pixel connection line 500 may include the same material as the common electrode 400. For example, the pixel connection line 500 may include ITO or IZO. The pixel connection line 500 may be insulated from the common electrode 400. For example, the pixel connection line 500 may be spaced apart from the common electrode 400.

The wiring area LA of the array substrate 110 may be located outside the pixel area PA of the array substrate 110. The wiring area LA may be positioned adjacent to the pixel area PA. The pixel area PA may be surrounded by the wiring area LA. For example, the pixel area PA may be defined by the wiring area LA.

The dummy electrode pattern 350 may be located in the wiring area LA. The dummy electrode pattern 350 may be positioned on the same layer as the pixel electrode 300. For example, the dummy electrode pattern 350 may be located between the array substrate 110 and the driving gate insulating layer 220. The dummy electrode pattern 350 may directly contact the array substrate 110. The dummy electrode pattern 350 may be parallel to the pixel electrode 300. Accordingly, in the display device according to the exemplary embodiment of the present disclosure, damage of the pixel electrode 300 due to the difference in density during the forming process may be prevented by the dummy electrode pattern 350. The dummy electrode pattern 350 may include the same material as the pixel electrode 300. For example, the dummy electrode pattern 350 may include ITO or IZO.

An intermediate supply wiring 700 for transmitting a specific voltage or signal to each pixel may be located in the wiring area LA. For example, the intermediate supply line 700 may be connected to the common voltage supply line 600 by the first intermediate connection line 810. The common voltage supply wiring 600 may be electrically connected to the common voltage supply source 30. For example, each pixel may be supplied with a common voltage through the intermediate supply line 700. The common electrode 400 of each pixel may be connected to the intermediate supply line 700. For example, the intermediate supply wiring 700 may extend in a direction parallel to the data line DL.

The intermediate supply wiring 700 may be located on the driving gate insulating layer 220. The intermediate supply wiring 700 may include a region overlapping the dummy electrode pattern 350. The intermediate supply wiring 700 may include a conductive material. The intermediate supply wiring 700 may have a transmittance lower than that of the dummy electrode pattern 350. For example, the intermediate supply wiring 700 may include metals such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), and tungsten (W). Accordingly, in the display device according to the exemplary embodiment, light passing through the dummy electrode pattern 350 may be blocked by the intermediate supply line 700. For example, when the display device according to the exemplary embodiment of the present invention is a liquid crystal display device, light supplied from the backlight unit may not pass through the wiring area LA of the array substrate 110. Therefore, in the display device according to the embodiment of the present invention, the sharpness may be improved.

The intermediate supply wiring 700 may have a reflectance lower than that of the driving gate electrode 210 of the driving thin film transistor TR. The intermediate supply wiring 700 may have a multilayer structure. The intermediate supply wiring 700 may have the same structure as the driving source electrode 240. For example, the intermediate supply wiring 700 may have a stacked structure of the low reflection intermediate electrode layer 701 and the high conductivity intermediate electrode layer 702.

The low reflection intermediate electrode layer 701 may be located between the driving gate insulating layer 220 and the high conductivity intermediate electrode layer 702. The low reflection intermediate electrode layer 701 may be located on the same layer as the low reflection source electrode layer 241. For example, the low reflection intermediate electrode layer 701 may directly contact the driving gate insulating layer 220. The low reflection intermediate electrode layer 701 may include the same material as the low reflection source electrode layer 241. The high conductivity intermediate electrode layer 702 may be located on the same layer as the high conductivity source electrode layer 242. The high conductivity intermediate electrode layer 702 may include the same material as the high conductivity source electrode layer 242. Accordingly, in the display device according to the exemplary embodiment, the reflection by the intermediate supply line 700 may be reduced. That is, in the display device according to the exemplary embodiment, the light L2 reflected by the intermediate supply wiring 700 may be reduced than the light L1 supplied to the wiring area LA. For example, if the display device according to the exemplary embodiment of the present invention is a liquid crystal display device, the light supplied from the backlight unit to the wiring area LA is reflected by the intermediate supply wiring 700 and the optical sheet of the backlight unit. Since it may not be re-introduced into the pixel area PA, generation of bright lines at the edge of the pixel area PA may be minimized.

The dummy semiconductor pattern 235 may be positioned between the driving gate insulating layer 220 and the intermediate supply wiring 700. The dummy semiconductor pattern 235 may include a semiconductor material. For example, the dummy semiconductor pattern 235 may include the same material as the driving semiconductor pattern 230. That is, in the display device according to the exemplary embodiment of the present invention, the light traveling toward the intermediate supply wiring 700 and the light reflected by the intermediate supply wiring 700 may pass through the dummy semiconductor pattern 235. . Accordingly, in the display device according to the exemplary embodiment, the reflection by the intermediate supply line 700 may be effectively reduced.

The display device according to the embodiment of the present invention is described as lowering the reflectance of the intermediate supply wiring 700 through the properties of the low reflection intermediate electrode layer 701. However, in the display device according to another exemplary embodiment, the reflectance of the intermediate supply line 700 may be lowered through a structural method. For example, in the display device according to another exemplary embodiment, the light reflected from the lower surface of the low reflection intermediate electrode layer 701 facing the array substrate 110 may have the low reflection intermediate electrode layer 701 and the high conductivity intermediate electrode layer. The thickness of the low reflection intermediate electrode layer 701 may be adjusted so as to cancel light reflected from the interface between 702. Accordingly, in the display device according to another exemplary embodiment, the degree of freedom of the material of the intermediate supply line 700 may be improved. In addition, in the display device according to another exemplary embodiment, the thickness ratio of the low reflection source electrode layer 241 and the high conductivity source electrode layer 242 and the thickness ratio of the low reflection drain electrode layer 251 and the high conductivity drain electrode layer 252 are described. The low reflection intermediate electrode layer 701 and the high conductivity intermediate electrode layer 702 may have the same thickness ratio. Accordingly, the display device according to another exemplary embodiment may optimize the characteristics of the driving source electrode 240 and the driving drain electrode 250 and reduce the reflectance of the intermediate supply wiring 700.

The common voltage supply wiring 600 may include a conductive material. The common voltage supply wiring 600 may have the same structure as the driving gate electrode 210. For example, the common voltage supply wiring 600 may have a stacked structure of the transparent supply electrode layer 601 and the high conductivity supply electrode layer 602. The transparent supply electrode layer 601 may be positioned on the same layer as the transparent gate electrode layer 211. For example, the transparent supply electrode layer 601 may include the same material as the transparent gate electrode layer 211. The high conductivity supply electrode layer 602 may be positioned on the same layer as the high conductivity gate electrode layer 212. For example, the high conductivity supply electrode layer 602 may include the same material as the high conductivity gate electrode layer 212.

The intermediate supply wiring 700 may be located closer to the pixel area PA than the common voltage supply wiring 600. For example, the common voltage supply wiring 600 may be located outside the intermediate supply wiring 700. Accordingly, the display device according to the embodiment of the present invention can minimize the influence of the reflectance of the common voltage supply wiring 600 on the quality of the image to be implemented. Therefore, in the display device according to the exemplary embodiment of the present invention, the degree of freedom of the structure and / or the material of the common voltage supply wiring 600 may be improved.

The planarization layer 120 may extend on the common voltage supply wiring 600 and the intermediate supply wiring 700. For example, the first intermediate connection line 810 may be located on the planarization layer 120. The planarization layer 120 may include at least one contact hole exposing a portion of the common voltage supply wiring 600 and at least one contact hole exposing a portion of the intermediate supply wiring 700. . The driving gate insulating layer 220 may include a contact hole exposing a portion of the common voltage supply wiring 600 positioned in the contact hole of the planarization layer 120. The first intermediate connection line 810 is disposed between the common voltage supply line 600 and the intermediate supply line 700 through contact holes of the planarization layer 120 and contact holes of the driving gate insulating layer 120. Can be electrically connected.

The first intermediate connection wire 810 may include a conductive material. The first intermediate connection wire 810 may include the same material as the common electrode 400. For example, the first intermediate connection line 810 may include ITO or IZO. The first intermediate connection wire 810 may be spaced apart from the common electrode 400.

As a result, in the display device according to the exemplary embodiment, the intermediate supply wiring 700 positioned in the wiring area LA adjacent to the pixel area PA and supplying a specific voltage or signal to each pixel has a relatively low reflectance. Accordingly, the deterioration of the image implemented by the intermediate supply wiring 700 may be minimized.

In the display device according to the exemplary embodiment, the common voltage supply wiring 600 has the same structure as the driving gate electrode 210 of the thin film transistor TR. However, in the display device according to another exemplary embodiment, the common voltage supply wiring 600 may have the same structure as the intermediate supply wiring 700. For example, in the display device according to another exemplary embodiment, the common voltage supply wiring 600 may have the same reflectance as the driving source electrode 240 of the thin film transistor TR. In the display device according to another exemplary embodiment, the intermediate supply wiring 700 may directly contact the common voltage supply wiring 600. Accordingly, in the display device according to another exemplary embodiment, the reflection of the wiring area LA may be effectively reduced.

The display device according to an embodiment of the present invention may further include a common voltage transfer wiring 900 and a second connection wiring 820 positioned in the wiring area LA. The common voltage transfer wiring 900 may supply a common voltage to the data driver 10 and / or the gate driver 20. The second connection wire 820 may connect the common voltage transfer wiring 900 with the common voltage supply wiring 600. The common voltage transfer wiring 900 may be located in parallel with the intermediate supply wiring 700. For example, the common voltage transfer wiring 900 may be located between the gate driver 20 and the intermediate supply wiring 700. The common voltage transfer wiring 900 may have the same structure as the intermediate supply wiring 700. For example, the reflectance of the common voltage transfer wiring 900 may be the same as the reflectance of the intermediate supply wiring 700. Accordingly, in the display device according to the exemplary embodiment of the present disclosure, the quality of an image to be implemented may be effectively improved.

In the display device according to an exemplary embodiment, the dummy semiconductor pattern 235 is positioned between the driving gate insulating layer 220 and the intermediate supply wiring 700. However, as shown in FIG. 4, the display device according to another exemplary embodiment of the present invention may include an intermediate supply line 700 directly contacting the driving gate insulating layer 220. Accordingly, in the display device according to another exemplary embodiment, the degree of freedom of the material and the forming process of the driving semiconductor pattern 230 may be improved. Therefore, in the display device according to another exemplary embodiment of the present disclosure, process efficiency may be improved, and deterioration of the image quality due to light reflected from the wiring area may be effectively prevented.

In the display device according to the exemplary embodiment, the intermediate supply wiring 700 has the same structure as the driving source electrode 240. However, the display device according to another embodiment of the present invention may include an intermediate supply wiring of a single layer structure. For example, as illustrated in FIG. 5, in the display device according to another exemplary embodiment, the low reflection supply electrode layer 701 positioned between the dummy semiconductor pattern 235 and the planarization layer 120 may be formed of each pixel. The common electrode 400 and the first intermediate connection wire 810 may be in direct contact with each other. Accordingly, in the display device according to another exemplary embodiment, reflection of the wiring area may be effectively minimized.

6 to 11 are views sequentially showing a method of forming a display device according to an embodiment of the present invention.

A method of forming a display device according to an embodiment of the present invention will be described with reference to FIGS. 3 and 6 to 11. First, as shown in FIG. 6, in the method of forming the display device according to the embodiment of the present invention, forming the transparent conductive material layer 211a on the array substrate 110, and the transparent conductive material layer 211a. The method may include forming the high conductivity gate material layer 212a on the first mask pattern and forming the first mask pattern MP on the high conductivity gate material layer 212a.

The transparent conductive material layer 211a may be formed of a conductive material. The transparent conductive material layer 211a may be formed of a transparent material. For example, forming the transparent conductive material layer 211a may include forming a layer made of ITO or IZO on the array substrate 110.

The high conductivity gate material layer 212a may be formed of a conductive material. The high conductivity gate material layer 212a may be formed of a material having a higher conductivity than the transparent conductive material layer 211a. For example, the forming of the high conductivity gate material layer 212a may include aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (on the transparent conductive material layer 211a). Forming a layer of metal such as W).

The first mask pattern MP may cover a region where a driving gate electrode, a pixel electrode, a data line, a dummy electrode pattern, and a common voltage supply wiring are formed through a subsequent process. The first mask pattern MP may include a first mask region MP1 and a second mask region MP2 having a thickness thinner than that of the first mask region MP1. For example, a region where the driving gate electrode, the data line, and the common voltage supply wiring are formed by a subsequent process may be covered by the first mask region MP1. The region where the dummy electrode pattern and the pixel electrode are formed by a subsequent process may be covered by the second mask region MP2. For example, forming the first mask pattern MP may include forming a mask material layer on the high conductivity gate material layer 212a and patterning the mask material layer using a halftone mask. It may include.

As shown in FIGS. 7 and 8, a method of forming a display device according to an exemplary embodiment of the present invention may include a driving gate electrode 210, a data line DL, a pixel electrode 300, and the like on the array substrate 110. The method may include forming the dummy electrode pattern 350 and the common voltage supply wiring 600.

The driving gate electrode 210, the data line DL, and the common voltage supply wiring 600 may be formed in a double layer structure. For example, the driving gate electrode 210 is a stacked structure of the transparent gate electrode layer 211 and the high conductivity gate electrode layer 212, and the data line DL is a stacked structure of the transparent data electrode layer and the high conductivity data electrode layer. The common voltage supply wiring 600 may have a stacked structure of a transparent supply electrode layer 601 and a high conductivity supply electrode layer 602. The pixel electrode 300 and the dummy electrode pattern 350 may be formed in a single layer structure. For example, the pixel electrode 300 and the dummy electrode pattern 350 may be a single layer including the same material as the transparent conductive material layer 211a.

Forming the driving gate electrode 210, the data line DL, the pixel electrode 300, the dummy electrode pattern 350, and the common voltage supply wiring 600 is performed without additional mask pattern formation. Can be. For example, forming the driving gate electrode 210, the data line DL, the pixel electrode 300, the dummy electrode pattern 350, and the common voltage supply wiring 600 is illustrated in FIG. 7. As illustrated, etching the transparent conductive material layer 211a and the high conductivity gate material layer 212a using the first mask pattern MP, and ashing of the first mask pattern MP. forming a second mask pattern MP3 from which the second mask region MP2 has been removed through an ashing process, and as shown in FIG. 8, the gate exposed by the second mask pattern MP3. And removing the material pattern 212p.

As illustrated in FIG. 9, a method of forming a display device according to an exemplary embodiment may include the driving gate electrode 210, the data line DL, the pixel electrode 300, and the dummy electrode pattern 350. And forming a driving gate insulating layer 220 on the array substrate 110 on which the common voltage supply wiring 600 is formed.

The driving gate insulating layer 220 may be formed of an insulating material. For example, the driving gate insulating layer 220 may be formed of silicon oxide and / or silicon nitride. The driving gate insulating layer 220 may be formed of a high-k material such as hafnium oxide (HfO) and titanium oxide (TiO).

As shown in FIG. 10, a method of forming a display device according to an exemplary embodiment of the present invention may include a driving thin film transistor (TR), a dummy semiconductor pattern 235, and an array substrate 100 on which the driving gate insulating layer 220 is formed. Forming the intermediate supply wiring 700 may include.

The forming of the driving thin film transistor TR may include forming a driving semiconductor pattern 230 on the driving gate insulating layer 220, a driving source electrode 240 connected to the driving semiconductor pattern 230, and a driving drain. Forming an electrode 250 may include.

The forming of the driving semiconductor pattern 230 may include forming a semiconductor material layer on the driving gate insulating layer 220 and patterning the semiconductor material layer. The semiconductor material layer may be formed of a semiconductor material. For example, the semiconductor material layer may be formed of silicon oxide and / or silicon nitride. The semiconductor material layer may be formed of a semiconductor oxide such as IGZO.

The driving source electrode 240 and the driving drain electrode 250 may be formed in a double layer structure. For example, the driving source electrode 240 is a laminated structure of the low reflection source electrode layer 241 and the high conductivity source electrode layer 242, and the driving drain electrode 250 is the low reflection drain electrode layer 251 and the high conductivity. The drain electrode layer 252 may have a stacked structure. The driving drain electrode 250 may be formed at the same time as the driving source electrode 240. For example, the forming of the driving source electrode 240 and the driving drain electrode 250 may include forming a low reflection material layer on the array substrate 110 on which the driving semiconductor pattern 230 is formed. The method may include forming a high conductivity material layer on the low reflection material layer and sequentially patterning the low reflection material layer and the high conductivity material layer.

The low reflection material layer and the high conductivity material layer may be formed of a conductive material. For example, the low reflection material layer and the high conductivity material layer are formed of metals such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). Can be. The low reflection material layer may be formed of a material having a lower reflectance than the high conductivity material layer. The high conductivity material layer may be formed of a material having a higher conductivity than the low reflection material layer.

The dummy semiconductor pattern 235 may be formed of the same material as the driving semiconductor pattern 230. For example, the forming of the dummy semiconductor pattern 235 may be performed at the same time as the forming of the driving semiconductor pattern 230.

The dummy semiconductor pattern 235 may be formed to overlap the dummy electrode pattern 350. That is, in the method of forming the display device according to an exemplary embodiment of the present disclosure, the dummy semiconductor pattern 235 may be formed in an area where light passing through the dummy electrode pattern 350 may be incident.

The intermediate supply wiring 700 may have the same structure as the driving source electrode 240. For example, the intermediate supply wiring 700 may have a stacked structure of the low reflection intermediate electrode layer 701 and the high conductivity intermediate electrode layer 702. The intermediate supply wiring 700 may be formed at the same time as the intermediate source electrode 240.

The intermediate supply wiring 700 may be formed on an upper surface of the dummy semiconductor pattern 235 facing the array substrate 110. For example, the intermediate supply wiring 700 may be formed to overlap the dummy electrode pattern 350. That is, in the method of forming the display device according to an exemplary embodiment of the present invention, the intermediate supply wiring 700 may be formed in an area capable of blocking light passing through the dummy electrode pattern 350 and the dummy semiconductor pattern 235. Can be.

As illustrated in FIG. 11, a method of forming a display apparatus according to an exemplary embodiment of the present invention may include forming the array substrate on which the driving source electrode 240, the driving drain electrode 250, and the intermediate supply wiring 700 are formed. Forming a planarization layer 120 on the portion 110, a portion of the driving drain electrode 250, a portion of the pixel electrode 300, a portion of the common voltage supply wiring 600, and the intermediate supply The method may include exposing a portion of the wiring 700.

The forming of the planarization layer 120 may include applying an insulating material on the array substrate 110 on which the driving source electrode 240, the driving drain electrode 250, and the intermediate supply wiring 700 are formed. It may include. For example, the planarization layer 120 may be formed of an organic insulating material. Steps of the array substrate 110 on which the driving source electrode 240, the driving drain electrode 250, and the intermediate supply wiring 700 are formed may be removed by a process of forming the planarization layer 120.

Exposing a portion of the driving drain electrode 250, a portion of the pixel electrode 300, a portion of the common voltage supply wiring 600, and a portion of the intermediate supply wiring 700 may be performed by the planarization. The method may include forming contact holes in the film 120 and forming contact holes in the driving gate insulating layer 220.

Contact holes formed in the driving gate insulating layer 220 may be located in the contact holes formed in the planarization layer 120. For example, forming contact holes in the planarization layer 120 may include removing the planarization layer 120 formed on an area exposed by the contact hole of the driving gate insulating layer 220. have.

As shown in FIG. 3, in the method of forming the display device according to the exemplary embodiment, the common electrode 400, the pixel connection line 500, and the first intermediate connection line 810 are formed on the planarization layer 120. It may include forming a.

The common electrode 400 may be formed to have at least one slit overlapping the pixel electrode 300. The pixel connection line 500 may be formed to electrically connect the driving drain electrode 250 and the pixel electrode 300. The first intermediate connection line may be formed to connect the intermediate supply line 700 with the common voltage supply line 600.

The common electrode 400, the pixel connection line 500, and the first intermediate connection line 810 may be formed at the same time. For example, the forming of the common electrode 400, the pixel connection line 500, and the first intermediate connection line 810 may include forming a transparent conductive layer on the planarization layer 120 where contact holes are formed. And patterning the transparent conductive layer. The transparent conductive layer may be formed of a transparent conductive material. For example, the transparent conductive layer may be formed of ITO or IZO.

As a result, the method of forming the display device according to the embodiment of the present invention provides a relatively low reflectance for the intermediate supply wiring 700 overlapping the dummy electrode pattern 350 to prevent damage to the pixel electrode 300 due to the difference in density. By forming at the same time as the drive source electrode 240 having a, it is possible to reduce the reflection by the intermediate supply wiring 700 without additional processing. Accordingly, in the method of forming the display device according to the exemplary embodiment of the present invention, the quality of the implemented image can be effectively improved without degrading process efficiency.

110: array substrate TR: driving thin film transistor
210: driving gate electrode 230: driving semiconductor pattern
235: dummy semiconductor pattern 240: driving source electrode
250: driving drain electrode 300: pixel electrode
350: dummy electrode pattern 400: common electrode
500: pixel connection electrode 600: common voltage supply wiring
700: intermediate supply wiring 701: low reflection intermediate electrode layer
810: intermediate connection wiring

Claims (20)

An array substrate including a pixel region and a wiring region positioned adjacent to the pixel region;
Pixels on the pixel area of the array substrate, the pixels including a thin film transistor and a pixel electrode electrically connected to the thin film transistor;
Intermediate supply wiring located on the wiring area of the array substrate and transferring a specific voltage or signal to each pixel; And
A dummy electrode pattern positioned on the wiring area of the array substrate and positioned on the same layer as the pixel electrode,
And the intermediate supply wiring has a higher conductivity than the dummy electrode pattern and a lower reflectance than the gate electrode of the thin film transistor. The method of claim 1,
And the intermediate supply line includes a region overlapping the dummy electrode pattern. The method of claim 1,
And a lower surface of the pixel electrode facing the array substrate is coplanar with a lower surface of the gate electrode facing the array substrate. The method of claim 3, wherein
The gate electrode is a stacked structure of a transparent gate electrode layer including the same material as the pixel electrode and a high conductivity gate electrode layer having a higher conductivity than the transparent gate electrode layer. The method of claim 3, wherein
The source electrode of the thin film transistor has a lower reflectance than the gate electrode,
And the intermediate supply wiring has the same structure as the source electrode of the thin film transistor. The method of claim 5,
The source electrode is a laminated structure of a low reflection source electrode layer and a high conductivity source electrode layer,
And a reflectance of the low reflection source electrode layer is lower than that of the high conductivity source electrode layer. The method of claim 1,
Each pixel further includes a common electrode including at least one slit overlapping the corresponding pixel electrode.
The common electrode is connected to the intermediate supply wiring. The method of claim 7, wherein
Each pixel further includes a planarization layer positioned between the pixel electrode and the common electrode.
And a gate insulating film of the thin film transistor extends between the pixel electrode and the planarization film. The method of claim 7, wherein
Each pixel further includes a pixel connection line connecting the thin film transistor and the pixel electrode.
The pixel connection line includes the same material as the common electrode. The method of claim 9,
A common voltage supply wiring located on the wiring area of the array substrate; And
Further comprising an intermediate connection wiring connecting the intermediate supply wiring with the common voltage supply wiring,
And the common voltage supply wiring has the same structure as the gate electrode of the thin film transistor. The method of claim 1,
And a dummy semiconductor pattern positioned between the dummy electrode pattern and the intermediate supply wiring. The method of claim 11,
The dummy semiconductor pattern includes the same material as the semiconductor pattern of the thin film transistor. Providing an array substrate comprising a pixel region and a wiring region adjacent the pixel region;
Forming a gate electrode and a pixel electrode on the pixel region of the array substrate, and forming a dummy electrode pattern on the wiring region of the array substrate;
Forming a gate insulating layer on the array substrate to cover the gate electrode, the pixel electrode, and the dummy electrode pattern;
Forming a driving thin film transistor including the gate electrode and the gate insulating layer on the pixel area of the array substrate;
Forming intermediate supply wiring on the wiring area of the array substrate, the intermediate supply wiring overlapping the dummy electrode pattern;
Forming a planarization film on the array substrate to cover the driving thin film transistor and the intermediate supply wiring; And
Forming a pixel connection line connecting the driving thin film transistor and the pixel electrode on the planarization layer,
And the intermediate supply wiring is formed to have a lower reflectance than the gate electrode of the driving thin film transistor. The method of claim 13,
The dummy electrode pattern is formed on the same layer as the pixel electrode. The method of claim 13,
Forming the gate electrode, the pixel electrode, and the dummy electrode pattern may include:
Forming a transparent conductive material layer on the array substrate;
Forming a high conductivity gate material layer on the transparent conductive material layer;
Forming a first mask pattern on the high conductivity gate material layer, the first mask pattern including a first mask region and a second mask region having a thickness thinner than the first mask region;
The transparent conductive material layer and the high conductivity gate material layer are sequentially etched by the first mask pattern to be positioned on the gate electrode, the pixel electrode, the dummy electrode pattern, and the pixel electrode and the dummy electrode pattern. Forming a gate material pattern;
Ashing the first mask pattern to form a second mask pattern from which the second mask region is removed;
Removing the gate material pattern using the second mask pattern;
The first mask area corresponds to the gate electrode, and the second mask area corresponds to the pixel electrode and the dummy electrode pattern. The method of claim 13,
Forming the driving thin film transistor is.
Forming a semiconductor pattern overlapping the gate electrode on the gate insulating layer;
Forming a source electrode connected to the source region of the semiconductor pattern on the gate insulating layer; And
Forming a drain electrode on the gate insulating layer, the drain electrode being connected to the drain region of the semiconductor pattern;
And the intermediate supply wiring is formed simultaneously with the source electrode. The method of claim 16,
The method may further include forming a dummy semiconductor pattern between the dummy electrode pattern and the intermediate supply wiring.
The dummy semiconductor pattern is formed simultaneously with the semiconductor pattern. The method of claim 16,
Forming the source electrode and the intermediate supply wiring,
Forming a low reflection material layer on the array substrate on which the semiconductor pattern is formed;
Forming a high conductivity material layer on the low reflection material layer; And
And sequentially patterning the low reflection material layer and the high conductivity material layer. The method of claim 18,
The low reflection material layer is formed of a material having a lower reflectance than the high conductivity material layer. The method of claim 13,
Forming a common voltage supply wiring on the wiring area of the array substrate; And
Forming an intermediate connection wiring on the planarization layer to connect the intermediate supply wiring to the common voltage supply wiring;
The common voltage supply wiring is formed simultaneously with the gate electrode,
And the intermediate connection line is formed simultaneously with the pixel connection line.

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