TWI553835B - Active substrate and display panel - Google Patents

Description

Active substrate and display panel

The invention relates to an active substrate and a display panel, in particular to an active substrate and a display panel with low power and narrow bezel.

Since the liquid crystal display panel has the characteristics of being thin and light in appearance, low in power consumption, and free from radiation pollution, it has become a mainstream product of current displays, and is widely used in various electronic devices. A conventional liquid crystal display panel is composed of an active substrate, a color filter substrate, and a liquid crystal layer. Wherein, the active substrate is composed of a plurality of thin film transistors arranged in an array and corresponding pixel electrodes, and the thin film transistor is used as a switching element of the pixel unit, and in order to control the individual pixel units, the active substrate is configured to scan. Lines and data lines to transmit switches and voltage signals to display the desired picture.

In the conventional liquid crystal display panel, the thin film transistor is made of amorphous germanium as its channel layer, so that the thin film transistor can have a switching function. However, the concentration of the amorphous germanium carrier and the mobility are low, and when the size of the thin film transistor is reduced, the driving speed of the thin film transistor is likely to be poor. For this reason, a channel layer using an oxide semiconductor material as a thin film transistor has been developed so far that the mobility of the oxide semiconductor material is higher than that of the amorphous germanium.

In conventional oxide transistors, the material of the gate insulating layer is yttrium oxide (SiOx), and tantalum nitride (SiNx) is used as the gate insulating layer compared to the thin film transistor, since yttrium oxide has a lower The dielectric constant can reduce the parasitic capacitance in the active substrate, thereby reducing the driving load of the liquid crystal display panel and eliminating unnecessary coupling capacitance. However, the peripheral circuit of the active substrate contains a capacitor, and a part of the dielectric layer of the capacitor is designed as a gate insulating layer, so when the peripheral circuit When the design of the capacitance value is maintained, the area of the capacitor needs to be increased, so that the width of the frame of the liquid crystal display panel is widened. In addition, when the area of the capacitor is reduced by increasing the dielectric constant of the gate insulating layer, the parasitic capacitance of the oxide transistor is increased, thereby increasing the driving load of the liquid crystal display panel and unnecessary coupling capacitance. It can be seen that the design of the conventional active substrate cannot simultaneously reduce the width of the frame and reduce the driving load.

The main object of the present invention is to provide an active substrate and a display panel to reduce the width of the frame and reduce the driving load.

To achieve the above object, the present invention provides an active substrate including a substrate, a lower electrode, a first insulating layer, a passivation layer, and an upper electrode. The lower electrode is disposed on the substrate. The first insulating layer is disposed on the lower electrode, and the first insulating layer has a recess. The passivation layer is disposed on the first insulating layer, and the passivation layer has a first through hole corresponding to the recess. The upper electrode is disposed on the passivation layer and extends through the first through hole to the bottom of the recess, wherein the lower electrode, the first insulating layer, the passivation layer and the upper electrode constitute a storage capacitor.

To achieve the above objective, the present invention further provides an active substrate including a substrate, a lower electrode, a first insulating layer, a first semiconductor layer, a passivation layer, and an upper electrode. The lower electrode is disposed on the substrate, and the first insulating layer is disposed on the lower electrode. The first semiconductor layer is disposed on the first insulating layer. The passivation layer is disposed on the first insulating layer and the first semiconductor layer, and the passivation layer has a first via to expose the first semiconductor layer. The upper electrode is disposed on the passivation layer and electrically connected to the first semiconductor layer through the first through hole, wherein the lower electrode, the first insulating layer, the passivation layer and the upper electrode form a storage capacitor.

In the active substrate of the present invention, the storage capacitor can reduce the area by reducing the distance between the bottom of the recess and the lower surface of the first insulating layer without changing the capacitance value, so that the active substrate can simultaneously have low power consumption. And the advantage of low storage capacitor area, which can reduce the width of the display panel.

100, 200, 300‧‧‧ active substrates

102‧‧‧Base

104‧‧‧First metal pattern layer

104a‧‧‧ lower electrode

104b‧‧‧first mat

104c‧‧‧ gate

106‧‧‧First insulation

106a‧‧‧fourth perforation

106b‧‧‧ dent

108‧‧‧Semiconductor layer

110‧‧‧ Passivation layer

110a‧‧‧ third perforation

110b‧‧‧second perforation

110c‧‧‧first perforation

112‧‧‧Second insulation

112a‧‧‧ fifth perforation

114‧‧‧Second metal pattern layer

114a‧‧‧Upper electrode

114b‧‧‧second mat

114c‧‧‧ source

114d‧‧‧Bungee

202‧‧‧Semiconductor pattern layer

202a‧‧‧First semiconductor layer

202b‧‧‧Second semiconductor layer

300a‧‧‧ display area

300b‧‧‧ surrounding area

302‧‧‧Shift register

304‧‧‧Electric displacement transducer

306‧‧‧ pixel structure

308‧‧‧ pixel electrodes

400‧‧‧ display panel

402‧‧‧Active substrate

404‧‧‧Display media layer

406‧‧‧Upper substrate

C1, C2‧‧‧ storage capacitor

Cst1‧‧‧first storage capacitor

Cst2‧‧‧Second storage capacitor

Cst3‧‧‧ third storage capacitor

D‧‧‧Deep

T1‧‧‧Maximum thickness

T2, T3, T4‧‧‧ thickness

Tr‧‧‧thin film transistor

Tr1‧‧‧first thin film transistor

Tr2‧‧‧Second thin film transistor

Tr3‧‧‧ third thin film transistor

W‧‧‧Width

G‧‧‧ spacing

1 to 4 are schematic views showing a method of fabricating an active substrate according to a first embodiment of the present invention.

5 to 8 are schematic views showing a method of fabricating an active substrate according to a second embodiment of the present invention.

Figure 9 is a top plan view of a active substrate in accordance with a third embodiment of the present invention.

Figure 10 is a cross-sectional view showing a display panel in accordance with an embodiment of the present invention.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

Referring to FIG. 1 to FIG. 4 , FIG. 1 to FIG. 4 are schematic diagrams showing a method of fabricating an active substrate according to a first embodiment of the present invention, and FIG. 4 is a schematic structural view of the active substrate according to the first embodiment of the present invention. In order to clearly show the method for fabricating the active substrate of the present embodiment, only a single thin film transistor, a single storage capacitor, and a single pad structure are formed, but the invention is not limited thereto, and other thin films of the present invention are The same fabrication method can be used for the crystal, storage capacitor and pad structure. As shown in Fig. 1, the substrate 102 is first provided. Next, a first metal pattern layer 104 is formed on the substrate 102, wherein the first metal pattern layer 104 includes a lower electrode 104a, a first pad 104b, and a gate 104c. Then, a first insulating layer 106, a semiconductor layer 108, and a passivation layer 110 are formed on the first metal pattern layer 104, wherein the first insulating layer 106 covers the first metal pattern layer 104 and the substrate 102, and the semiconductor layer 108 is disposed corresponding to the gate 104c and directly above the gate 104c, and the passivation layer 110 covers the semiconductor layer 108 and the first insulating layer 106. In this embodiment, the step of forming the first metal pattern layer 104 and the step of forming the first insulating layer 106 may selectively form the second insulating layer 112 between the first metal pattern layer 104 and the first insulating layer 106. And the second insulating layer 112 covers the first metal pattern layer 104 and the substrate 102. And, the maximum thickness T1 of the first insulating layer 106, that is, the thickness when not etched, and the thickness T2 of the second insulating layer 112 It is larger than the thickness T3 of the passivation layer 110, and the maximum thickness T1 of the first insulating layer 106 is greater than the thickness T2 of the second insulating layer 112. For example, the first insulating layer 106 may have a maximum thickness T1 of 1500 angstroms to 6000 angstroms, preferably 2500 angstroms to 4500 angstroms, and the second insulating layer 112 may have a thickness T2 of 100 angstroms to 3,000 angstroms, preferably 300 Å. The thickness of the passivation layer 110 may be from 100 angstroms to 3,000 angstroms, and the thickness of the semiconductor layer 108 may be from 50 angstroms to 2,000 angstroms, preferably from 200 angstroms to 600 angstroms, but not limited to the above. Furthermore, the dielectric constant of the first insulating layer 106 is smaller than the dielectric constant of the second insulating layer 112. For example, the material of the first insulating layer 106 may include yttrium oxide (SiOx), yttrium oxynitride (SiNxOy) or aluminum oxide (AlOx), and the material of the second insulating layer 112 may include tantalum nitride (SiNx), nitrogen. Cerium oxide (SiNxOy), alumina (AlOx), yttrium oxide (HfOx) or zirconia (ZrOx). The material of the passivation layer 110 may include hafnium oxide or hafnium oxynitride (SiNxOy), and the material of the semiconductor layer 108 may include an oxide semiconductor, and the oxide semiconductor may be an oxide containing indium, zinc, tin, gallium or a combination of the above elements. Or an oxynitride such as indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO) or zinc oxynitride (ZnOxNy). In order to clarify the manufacturing method of the active substrate 100 of the present embodiment, the step after the formation of the passivation layer 110 is described by the structure having the second insulating layer 112, but the present invention is not limited thereto. In other embodiments, the second insulating layer may not be provided between the first metal pattern layer and the first insulating layer.

Subsequently, as shown in FIG. 2, a first lithography and etching process is performed on the passivation layer 110 to form a third via 110a in the passivation layer 110 on the first pad 104b, and passivation on the semiconductor layer 108. Two second vias 110b are formed in the layer 110, wherein the third vias 110a are for example exposed to a portion of the upper surface of the first insulating layer 106, and each of the second vias 110b is for example exposed to a portion of the upper surface of the semiconductor layer 108.

Then, as shown in FIG. 3, a second lithography and etching process is performed to form a fourth via 106a in the first insulating layer 106 exposed by the third via 110a, and exposed in the fourth via 106a. A fifth via 112a is formed in the second insulating layer 112, so that the first pad 104b is exposed, and the passivation layer 110 on the lower electrode 104a and the first insulating layer 106 are simultaneously etched, thereby being respectively applied to the passivation layer 110. Forming a first through hole 110c and a recess 106b in the first insulating layer 106, The first through hole 110c and the recess 106b are disposed corresponding to the lower electrode 104a. Since the sum of the maximum thickness T1 of the first insulating layer 106 and the thickness T2 of the second insulating layer 112 is greater than the thickness T3 of the passivation layer 110, after the passivation layer 110 is etched through, the first insulating layer 106 on the lower electrode 104a is The second insulating layer 112 has not been etched through. Therefore, in the step of forming the fourth via 106a and the fifth via 112a, the first insulating layer 106 continues to be etched until the first insulating layer 106 and the second insulating layer 112 corresponding to the first pad 104b are etched. Stopping, so the first perforation 110c can be disposed corresponding to the recess 106b. In this embodiment, the thickness of the first insulating layer 106 corresponding to the first via 110c, that is, the vertical spacing G between the bottom of the recess 106b and the lower surface of the first insulating layer 106, and the thickness of the second insulating layer. The sum of T2 may be between 50% and 150% of the thickness of the passivation layer 110, for example, between 500% and 3500 angstroms, preferably between 10,000 angstroms and 2,500 angstroms, between 70% and 130%. Also, the sum of the depth D of the recess 106b and the thickness T3 of the passivation layer 110 may be between 50% and 150% of the sum of the maximum thickness T1 of the first insulating layer 106 and the thickness T2 of the second insulating layer 112, for example: 1500 angstroms to 5,000 angstroms. The present invention is not limited to the above, and the depth D of the recess 106b of the present invention or the thickness of the remaining first insulating layer 106 corresponding to the first through-hole 110c can be achieved by adjusting the etching conditions of the etching process.

Next, as shown in FIG. 4, a metal layer (not labeled) is formed on the passivation layer 110, and the metal layer is patterned to form a second metal pattern layer 114, wherein the second metal pattern layer 114 includes an upper layer. The electrode 114a, a second pad 114b, a source 114c and a drain 114d. The active substrate 100 of this embodiment is thus completed.

In the present embodiment, the upper electrode 114a is disposed corresponding to the lower electrode 104a and extends through the first through hole 110c of the passivation layer 110 to the bottom of the recess 106b of the first insulating layer 106. Therefore, the upper electrode 114a, the lower electrode 104a, and the first insulating layer 106 and the second insulating layer 112 located between the upper electrode 114a and the lower electrode 104a in the recess 106b may constitute the storage capacitor C, and the upper electrode located in the recess 106b The first insulating layer 106 and the second insulating layer 112 between the 114a and the lower electrode 104a can serve as a dielectric layer of the storage capacitor C1. In addition, the second pad 114b is disposed corresponding to the first pad 104b, and is electrically connected to the first pad 104b through the third through hole 110a, the fourth through hole 106a, and the fifth through hole 112a. Sexual connection. Moreover, the source 114c and the drain 114d are disposed corresponding to the semiconductor layer 108, and are electrically connected to the semiconductor layer 108 through the second vias 110b, respectively, such that the gate 104c, the first insulating layer 106, the second insulating layer 112, and the semiconductor layer 108. The source electrode 114c and the drain electrode 114c constitute a thin film transistor Tr. The first insulating layer 106 and the second insulating layer 112 serve as a gate insulating layer of the thin film transistor Tr.

It should be noted that, since the maximum thickness T1 of the first insulating layer 106 is greater than the thickness T2 of the second insulating layer 112, and the dielectric constant of the first insulating layer 106 is smaller than the dielectric constant of the second insulating layer 112, the gate is insulated. The dielectric constant of the layer can be lowered to be close to the dielectric constant of the first insulating layer 106 to further reduce the parasitic capacitance of the thin film transistor Tr, and reduce the driving load of the active substrate 100 and eliminate unnecessary coupling capacitance. Furthermore, although the maximum thickness T1 of the first insulating layer 106 and the dielectric constant and the thickness T2 of the second insulating layer 112 and the dielectric constant need to be fixed in order to reduce the driving load of the active substrate 100, the storage capacitor C1 of the present embodiment is still The area size can be reduced by reducing the spacing between the bottom of the recess 106b and the lower surface of the first insulating layer 106 without changing the capacitance value. In this way, the active substrate 100 of the embodiment can simultaneously have the advantages of low power consumption and low storage capacitance area. In other embodiments, the active substrate may not include the second insulating layer.

In other embodiments, the active substrate may not include the second insulating layer, such that the storage capacitor is composed of the upper electrode, the lower electrode, and the first insulating layer between the upper electrode and the lower electrode in the recess, and the thin film transistor is It is composed of a gate, a first insulating layer, a semiconductor layer, a source, and a drain.

The active substrate of the present invention and the method of fabricating the same are not limited to the above embodiments. The other embodiments and variations of the present invention will be further described in the following, and in order to simplify the description and the differences between the various embodiments or variations, the same reference numerals will be used to refer to the same elements, and the repeated parts will not be described again. .

Referring to FIG. 5 to FIG. 8 , FIG. 5 to FIG. 8 are schematic diagrams showing a method for fabricating an active substrate according to a second embodiment of the present invention, and FIG. 8 is a schematic structural view of the active substrate according to the second embodiment of the present invention. Compared with the first embodiment, the method for fabricating the active substrate 200 in the present embodiment is the same as the first embodiment in the step of forming the first insulating layer 106, and therefore the steps are not here. Do more details. As shown in FIG. 5, after the first insulating layer 106 is formed, a semiconductor pattern layer 202 is formed on the first insulating layer 106, so that the semiconductor pattern layer 202 includes a first semiconductor layer 202a and a second semiconductor layer 202b. The first semiconductor layer 202a is disposed corresponding to the lower electrode 104a, and the second semiconductor layer 202b is disposed corresponding to the gate 104c. Subsequently, a passivation layer 110 is formed on the semiconductor pattern layer 202 and the first insulating layer 106. In this embodiment, the step of forming the first metal pattern layer 104 and the step of forming the first insulating layer 106 may also selectively form a second insulating layer between the first metal pattern layer 104 and the first insulating layer 106. 112, and the second insulating layer 112 covers the first metal pattern layer 104 and the substrate 102. Also, the maximum thickness T1 of the first insulating layer 106, that is, the thickness when not yet etched, and the thickness T2 of the second insulating layer 112 are greater than the thickness T3 of the passivation layer 110, and the maximum thickness T1 of the first insulating layer 106 is greater than The thickness T2 of the second insulating layer 112. For example, the first insulating layer 106 may have a maximum thickness T1 of 1500 angstroms to 6000 angstroms, preferably 2500 angstroms to 4500 angstroms, and the second insulating layer 112 may have a thickness T2 of 100 angstroms to 3,000 angstroms, and the passivation layer. The thickness of the semiconductor pattern layer 202 may be from 50 angstroms to 3,000 angstroms, and the thickness T4 of the semiconductor pattern layer 202 may be from 50 angstroms to 2,000 angstroms, preferably from 200 angstroms to 600 angstroms. Furthermore, the dielectric constant of the first insulating layer 106 is smaller than the dielectric constant of the second insulating layer 112. For example, the material of the first insulating layer 106 may include yttrium oxide (SiOx), yttrium oxynitride (SiNxOy) or aluminum oxide (AlOx), and the material of the second insulating layer 112 may include tantalum nitride (SiNx), nitrogen. Cerium oxide (SiNxOy), alumina (AlOx), yttrium oxide (HfOx) or zirconia (ZrOx). The material of the semiconductor pattern layer 202 may include an oxide semiconductor, and the oxide semiconductor may be an oxide or an oxynitride containing indium, zinc, tin, gallium or a combination of the above elements, for example, indium gallium zinc oxide (IGZO), indium. Tin-zinc oxide (ITZO), zinc oxide (ZnO) or zinc oxynitride (ZnOxNy), and the material of the passivation layer 110 may include yttrium oxide (SiOx) or yttrium oxynitride (SiNxOy). In order to clarify the manufacturing method of the active substrate of the present embodiment, the step after the formation of the passivation layer 110 is described by the structure in which the second insulating layer 112 is formed, but the present invention is not limited thereto. In other embodiments, the second insulating layer may not be formed between the first metal pattern layer and the first insulating layer.

Next, as shown in FIG. 6, a first lithography and etching process is performed on the passivation layer 110, and a first via 110c, a second via 110b, and a third via 110a are formed in the passivation layer 110. First A through hole 110c is disposed corresponding to the first semiconductor layer 202a and exposes the first semiconductor layer 202a. The second through hole 110b is disposed corresponding to the second semiconductor layer 202b and exposes the second semiconductor layer 202b. The third through hole 110a is disposed corresponding to the first pad 104b and exposes the first insulating layer 106.

Then, as shown in FIG. 7, a second lithography and etching process is performed on the first insulating layer 106 to form a fourth via 106a in the first insulating layer 106 exposed by the third via 110a, and in the fourth A fifth through hole 112a is formed in the second insulating layer 112 exposed by the through hole 106a, so that the first pad 104b is exposed.

Next, as shown in FIG. 8, a metal layer (not labeled) is formed on the passivation layer 110, and the metal layer is patterned to form a second metal pattern layer 114, wherein the second metal pattern layer 114 includes an upper electrode 114a, The second pad 114b, the source 114c, and the drain 114d. The active substrate 200 of this embodiment is thus completed. In the present embodiment, the upper electrode 114a is disposed on the passivation layer 110 corresponding to the first semiconductor layer 202a, and extends through the first through hole 110c of the passivation layer 110 to be electrically connected to the first semiconductor layer 202a, so that the lower electrode 104a, The first insulating layer 106, the second insulating layer 112, the first semiconductor layer 202a, and the upper electrode 114a may constitute a storage capacitor C2. The second pad 114 is disposed on the passivation layer 110 and penetrates the third via 110a of the passivation layer 110, the fourth via 106a of the first insulating layer 106, and the fifth via 112a and the first pad 104b of the second insulating layer 112. Electrical connection. The source 114c and the drain 114d are disposed on the passivation layer 110 corresponding to the second semiconductor layer 202b, and are electrically connected to the second semiconductor layer 202b through the second vias 110b, respectively, such that the gate 104c, the first insulating layer 106, The second insulating layer 112, the second semiconductor layer 202b, the source 114c, and the drain 114d may constitute a thin film transistor Tr.

In other embodiments, the active substrate may not include the second insulating layer, such that the storage capacitor is composed of the lower electrode, the first insulating layer, the first semiconductor layer, and the upper electrode, and the thin film transistor is composed of the gate and the first insulating layer. The layer, the second semiconductor layer, the source, and the drain are formed.

Please refer to FIG. 9. FIG. 9 is a top view of the active substrate according to a third embodiment of the present invention. As shown in FIG. 9, the active substrate 300 of the present embodiment may have a display area 300a and a peripheral area 300b surrounding the display area 300a. And, the active substrate 300 includes at least one shift register (shift Register 302, a level shifter 304, and at least one pixel structure 306. The shift register 302 and the electric displacement converter 304 are disposed in the peripheral area 300b, and the pixel structure 306 is disposed in the display area 300a. A portion of the shift register 302 may be formed by at least one first thin film transistor Tr1 and at least one first storage capacitor Cst1. A portion of the electric displacement transducer 304 may be formed by at least one second thin film transistor Tr2 and at least one second storage capacitor Cst2. The pixel structure 306 can be composed of at least a third thin film transistor Tr3, at least a third storage capacitor Cst3, and at least one pixel electrode 308. In this embodiment, at least one of the first thin film transistor Tr1, the second thin film transistor Tr2, and the third thin film transistor Tr3 may be the thin film transistor Tr structure shown in FIG. 4 of the first embodiment, respectively. The thin film transistor Tr structure shown in FIG. 8 of the second embodiment, and at least one of the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 may be respectively the fourth embodiment of the first embodiment. The structure of the storage capacitor C1 shown or the storage capacitor C2 shown in FIG. 8 of the second embodiment is not described here.

It is noted that at least one of the first storage capacitor Cst1 and the second storage capacitor Cst2 can be reduced by reducing the spacing between the bottom of the recess 106b and the lower surface of the first insulating layer 106 without changing the capacitance value. The area occupied thereby can reduce the space for setting at least one of the first storage capacitor Cst1 and the second storage capacitor Cst2. Thereby, the width W of the peripheral region 300b, that is, the distance between the display region 300a and the side of the substrate 102 can be reduced, and the width W can be 0.4 mm to 2.5 mm or 0.8 mm according to the size of the display panel. The thickness is from 1.3 mm (small size) or from 1 mm to 5 mm (large size), so that the display panel to which the active substrate 300 of the present embodiment is applied can effectively reduce the width of the bezel. Moreover, when the third storage capacitor Cst3 is shrunk to reduce the area between the bottom of the recess 106b and the lower surface of the first insulating layer 106, the range of the pixel structure 306 can also be reduced, so that the pixel structure per unit area The number of 306, the resolution, is increased.

Please refer to Figure 10 and refer to Figure 9 together. Figure 10 is a cross-sectional view showing a display panel in accordance with an embodiment of the present invention. As shown in FIG. 10, the display panel 400 of the present embodiment may include an active substrate 402, a display medium layer 404, and an upper substrate 406. The active substrate 402 can be any of the above The active substrate of the embodiment is therefore not described here. The display medium layer 404 may be a liquid crystal layer, but is not limited thereto. The display panel 400 of the present invention can be any active array display panel, such as a liquid crystal display panel, an organic light emitting diode display panel, an electrophoretic display panel, or an electrochromic display panel.

In summary, in the active substrate of the present invention, the storage capacitor can reduce the area by reducing the spacing between the bottom of the recess and the lower surface of the first insulating layer without changing the capacitance value, so that the active substrate can simultaneously It combines the advantages of low power consumption and low storage capacitance area, which in turn reduces the frame width of the display panel.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧Active substrate

102‧‧‧Base

104‧‧‧First metal pattern layer

104a‧‧‧ lower electrode

104b‧‧‧first mat

104c‧‧‧ gate

106‧‧‧First insulation

106a‧‧‧fourth perforation

106b‧‧‧ dent

108‧‧‧Semiconductor layer

110‧‧‧ Passivation layer

110a‧‧‧ third perforation

110b‧‧‧second perforation

110c‧‧‧first perforation

112‧‧‧Second insulation

112a‧‧‧ fifth perforation

114‧‧‧Second metal pattern layer

114a‧‧‧Upper electrode

114b‧‧‧second mat

114c‧‧‧ source

114d‧‧‧Bungee

C1‧‧‧ storage capacitor

D‧‧‧Deep

T1‧‧‧Maximum thickness

T2, T3‧‧‧ thickness

Tr‧‧‧thin film transistor

G‧‧‧ spacing

Claims (12)

An active substrate includes: a substrate; a lower electrode disposed on the substrate; a first insulating layer disposed on the lower electrode, and the first insulating layer has a recess; a passivation layer disposed on the first On the insulating layer, the passivation layer has a first through hole corresponding to the recess; and an upper electrode is disposed on the passivation layer and extends through the first through hole to the bottom of the recess, wherein the lower electrode The first insulating layer and the upper electrode constitute a storage capacitor. The active substrate of claim 1, further comprising: a gate disposed on the substrate, wherein the first insulating layer covers the gate; a semiconductor layer disposed on the first insulating layer and correspondingly a gate electrode, wherein the passivation layer is disposed on the semiconductor layer, and has two second vias respectively exposing the semiconductor layer; and a source and a drain are disposed on the passivation layer, and the source is The drain is electrically connected to the semiconductor layer through each of the second vias, wherein the gate, the first insulating layer, the semiconductor layer, the source and the drain form a thin film transistor. The active substrate of claim 2, wherein the substrate has a display area and a peripheral area surrounding the display area, and the thin film transistor and the storage capacitor are located in the peripheral area to form a shift register. One part of a shift register or part of a level shifter. The active substrate of claim 2, wherein the substrate has a display area and a peripheral area surrounding the display area, the active substrate further comprises a pixel electrode, and the pixel electrode, the thin film transistor and the storage A capacitor is located in the display area to form part of a pixel structure. The active substrate of claim 1, wherein the storage capacitor further comprises a second insulating layer disposed between the first insulating layer and the lower electrode, and the first insulating layer has a maximum thickness greater than the second insulating layer a thickness of the layer, wherein a dielectric constant of the first insulating layer is less than a dielectric constant of the second insulating layer, wherein a spacing between a bottom of the recess and a lower surface of the first insulating layer and a second insulating layer The sum of the thicknesses is between 50% and 150% of the thickness of the passivation layer, and the sum of the spacing between the bottom of the recess and the lower surface of the first insulating layer and the thickness of the second insulating layer is 500 angstroms Up to 3,500 angstroms. The active substrate of claim 1, wherein the material of the first insulating layer comprises yttrium oxide (SiOx), yttrium oxynitride (SiNxOy) or aluminum oxide (AlOx), and the material of the passivation layer comprises yttrium oxide (SiOx). Or bismuth oxynitride (SiNxOy). An active substrate includes: a substrate; a lower electrode disposed on the substrate; a first insulating layer disposed on the lower electrode; a first semiconductor layer disposed on the first insulating layer; a passivation layer, And disposed on the first insulating layer and the first semiconductor layer, and the passivation layer has a first via to expose the first semiconductor layer; and an upper electrode disposed on the passivation layer and transmitting through the first The through hole is electrically connected to the first semiconductor layer, wherein the lower electrode, the first insulating layer, the first semiconductor layer and the upper electrode form a storage capacitor. The active substrate of claim 7, further comprising: a gate disposed on the substrate, wherein the first insulating layer covers the gate; a second semiconductor layer disposed on the first insulating layer and disposed on the gate electrode, wherein the passivation layer is disposed on the second semiconductor layer and has two second vias respectively exposing the second semiconductor And a source and a drain are disposed on the passivation layer, and the source and the drain are electrically connected to the second semiconductor layer through the second through holes, wherein the gate, the first An insulating layer, the semiconductor layer, the source, and the drain form a thin film transistor. The active substrate of claim 8, wherein the substrate has a display area and a peripheral area surrounding the display area, and the thin film transistor and the storage capacitor are located in the peripheral area to form a shift register. One part or one part of an electric displacement transducer. The active substrate of claim 8, wherein the substrate has a display area and a peripheral area surrounding the display area, the active substrate further includes a pixel electrode, the pixel electrode, the thin film transistor and the storage capacitor It is located in the display area to form part of a pixel structure. The active substrate of claim 7, wherein the storage capacitor further comprises a second insulating layer disposed between the first insulating layer and the lower electrode, and the first insulating layer has a thickness greater than the second insulating layer The thickness of the first insulating layer is less than the dielectric constant of the second insulating layer, wherein the first insulating layer has a thickness of 1500 angstroms to 6000 angstroms, and the second insulating layer has a thickness of 100 angstroms to 3000 angstroms, and the first semiconductor layer has a thickness of 50 angstroms to 2000 angstroms. The active substrate of claim 7, wherein the material of the first insulating layer comprises cerium oxide (SiOx), cerium oxynitride (SiNxOy) or aluminum oxide (AlOx), and the material of the first semiconductor layer comprises indium and zinc. An oxide or oxynitride of tin, gallium or a combination of the above elements, and the material of the passivation layer comprises cerium oxide (SiOx) or cerium oxynitride (SiNxOy).