JP2010078632A - Display and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display that can have a gate insulating film of a thin film transistor and an inter-layer insulating film at a wiring intersection part formed to suitable thicknesses respectively without increasing mask processes. <P>SOLUTION: The method of manufacturing the display includes the processes of: forming first and second thin film transistors on an insulating substrate; forming the gate insulating film covering a gate electrode of the first thin film transistor, a gate electrode of the second thin film transistor, and a gate signal line; forming a dehydrogenated first amorphous silicon semiconductor layer on the insulating film; altering the first amorphous silicon semiconductor layer in a formation region of the first thin film transistor into a polycrystalline silicon semiconductor layer; etching the amorphous silicon semiconductor layer in a formation region of the first thin film transistor and a part of the insulating film from a surface in order; and forming a second amorphous silicon semiconductor layer on the insulating film while covering the polycrystalline silicon semiconductor layer and first amorphous silicon semiconductor layer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a display device and a manufacturing method thereof, and more particularly to an active matrix display device and a manufacturing method thereof.

  This type of display device includes a display area unit composed of pixels arranged in a matrix and a peripheral circuit unit (scanning signal drive circuit, video signal drive circuit) that drives each pixel in the display area unit. ing.

  In the display area portion, a pixel row is selected by sequentially supplying a scanning signal by the scanning signal driving circuit to each gate signal line formed in common for each pixel in the row direction, and at the time of this selection, the video signal driving circuit A video signal is supplied to each pixel through a drain signal line formed in common for each pixel in the column direction.

  For this reason, each pixel is formed with a transistor that is turned on by the supply of the scanning signal and guides the video signal to the pixel. The scanning signal driving circuit and the video signal driving circuit also have a large number of transistors. It is configured.

  Here, in such a display device, the peripheral circuit portion is formed in parallel with the formation of the display region portion, and the display region portion and the peripheral circuit portion are provided on the same substrate. Things are known. In this case, each transistor in the peripheral circuit section is formed of a thin film transistor (TFT) like the transistor of each pixel.

  Such a thin film transistor is provided with a gate insulating film, and this gate insulating film is used as an interlayer insulating film at a wiring intersection (intersection of a gate signal line and a drain signal line) in another region or as a pixel. In the case where a capacitive element for accumulating the video signal supplied therein for a relatively long time is provided, it may be configured as a dielectric film of the capacitive element. In this case, when the thickness of the gate insulating film is uniform over the entire area of the substrate, there arises a disadvantage that a large film thickness cannot be secured at the wiring intersection, or a small film thickness cannot be secured in the capacitive element.

Patent Document 1 below discloses a configuration in which the dielectric film is formed in a separate process from the gate insulating film of the thin film transistor in order to reduce the thickness of the dielectric film of the capacitive element. An extra mask process is required, which increases the manufacturing process.
JP 2001-13520 A

  For this reason, it is preferable that the gate insulating film of the thin film transistor, the interlayer insulating film at the wiring intersection, or the dielectric film of the capacitor element have a thickness suitable for each, and in this case, an increase in the manufacturing process can be avoided. desired.

  In recent years, the thin film transistor formed in each pixel is composed of an amorphous silicon semiconductor layer made of, for example, amorphous Si, whereas the thin film transistor formed in the peripheral circuit portion is made of, for example, a polycrystalline silicon semiconductor layer made of poly-Si. What is made up of is known. This is because the peripheral circuit portion requires a thin film transistor having excellent charge mobility. In this case, also in these thin film transistors, it is preferable to make the thicknesses of the gate insulating films different in accordance with their characteristics.

  An object of the present invention is to provide a gate insulating film of a thin film transistor including an amorphous silicon semiconductor layer, a gate insulating film of a thin film transistor including a polycrystalline silicon semiconductor layer, and an interlayer insulating film at a wiring intersection without increasing the mask process. An object of the present invention is to provide a display device which can be formed with an appropriate thickness.

  Another object of the present invention is to provide a gate insulating film of a thin film transistor including an amorphous silicon semiconductor layer, a gate insulating film of a thin film transistor including a polycrystalline silicon semiconductor layer, a dielectric film in a capacitor portion, and a wiring without increasing the mask process. An object of the present invention is to provide a display device in which interlayer insulating films at intersections can be formed with appropriate thicknesses.

  The configuration of the present invention can be as follows, for example.

(1) The display device of the present invention is a display device having, for example, a first thin film transistor and a second thin film transistor having a bottom gate structure, a gate signal line, and a drain signal line on an insulating substrate. The first gate electrode of the thin film transistor, the second gate electrode of the second thin film transistor, and the gate signal line are formed in the same layer, the source / drain electrodes of the first thin film transistor, and the source / drain of the second thin film transistor The electrode and the drain signal line are formed in the same layer, and the gate signal line and the drain signal line have wiring intersections that intersect with each other via an interlayer film, and cover the first gate electrode. The first insulating film has a first height, a second height smaller than the first height, and a third height smaller than the second height. The region of the insulating film in which the second height is formed is farther from the first gate electrode in plan view than the region in which the first height is formed. The region of the first insulating film in which the third height is formed is farther from the first gate electrode in plan view than the region in which the second height is formed. A polycrystalline silicon semiconductor layer and an amorphous silicon semiconductor layer, which are sequentially stacked, are formed on the first height surface of the first insulating film, and the second insulating film covering the second gate electrode is The region having the fourth height smaller than the first height and the third height and having the third height of the second insulating film is formed with the fourth height. The distance from the second gate electrode in a plan view is larger than the region where the fourth insulating film has the fourth height of the second insulating film. An amorphous silicon semiconductor layer is formed on the surface, and the interlayer film includes a third insulating film and an amorphous silicon semiconductor layer that cover the gate signal line, and the third insulating film includes the first insulating film. 1, the second height, and the third height, and an amorphous silicon semiconductor layer is formed on the first height surface of the third insulating film. And

(2) In the display device of the present invention, for example, in (1), the insulating substrate includes a display region portion having a plurality of pixels and a peripheral circuit portion surrounding the display region portion, and the first thin film transistor Is formed in the peripheral circuit portion.

(3) In the display device of the present invention, for example, in (2), the first thin film transistor is formed in a scanning signal driving circuit.

(4) In the display device of the present invention, for example, in (2), the first thin film transistor is formed in an RGB switching circuit.

(5) In the display device of the present invention, for example, in (1) to (4), the two thin film transistors are formed in a pixel.

(6) In the display device of the present invention, for example, in (1) to (5), the amorphous silicon semiconductor layer formed on the first height surface of the third insulating film is a first non- It has a crystalline silicon semiconductor layer and a second amorphous silicon semiconductor layer formed on the first amorphous silicon semiconductor layer.

(7) In the display device of the present invention, for example, in (6), the second amorphous silicon semiconductor layer has a hydrogen concentration higher than that of the first amorphous silicon semiconductor layer. The display device according to claim 6.

(8) In the display device of the present invention, for example, in (6) or (7), the first amorphous silicon semiconductor layer is the first height surface of the insulating film covering the first gate electrode. The polycrystalline silicon semiconductor layer is formed in the same layer.

(9) In the display device of the present invention, for example, in (1) to (8), the capacitive signal line, the capacitive signal line, and the fourth insulating film in the same layer as the one gate electrode are formed on the insulating substrate. And the fourth insulating film has the third height. The capacitor element includes a drain / source electrode and an electrode in the same layer that are overlapped with each other.

(10) The display device of the present invention is characterized in that, for example, in (9), the capacitive element is formed in a pixel.

(11) The manufacturing method of the display device of the present invention includes, for example, a first thin film transistor and a second thin film transistor having a bottom gate structure having a gate electrode as the same layer on an insulating substrate, and a gate signal line in the same layer as the gate electrode. And a drain signal line having the same layer as the source / drain electrodes of the first thin film transistor and the second thin film transistor, and a display device comprising a wiring intersection where the gate signal line and the drain signal line intersect each other A method of forming a gate electrode of the first thin film transistor, a gate electrode of the second thin film transistor, and the gate signal line on the insulating substrate, a gate electrode of the first thin film transistor, and the second thin film transistor Forming an insulating film covering the gate electrode and the gate signal line, and dehydrating the insulating film Forming a converted first amorphous silicon semiconductor layer; transforming the first amorphous silicon semiconductor layer in a formation region of the first thin film transistor into a polycrystalline silicon semiconductor layer; and Forming a mask in a formation region and a wiring crossing region, sequentially etching a part from the surface of the amorphous silicon semiconductor layer and the insulating film in the formation region of the second thin film transistor, and removing the mask; And forming a second amorphous silicon semiconductor layer on the insulating film so as to cover the polycrystalline silicon semiconductor layer and the first amorphous silicon semiconductor layer.

(12) A method for manufacturing a display device according to the present invention includes, for example, a first thin film transistor and a second thin film transistor having a bottom gate structure having a gate electrode as the same layer on an insulating substrate, and a gate signal line in the same layer as the gate electrode. A drain signal line having the same layer as the source / drain electrodes of the first thin film transistor and the second thin film transistor, and a wiring intersection where the gate signal line and the drain signal line intersect each other, and the gate electrode And a capacitive element having an insulating film interposed between the one electrode in the same layer and the other electrode in the same layer as the source / drain electrode, on the insulating substrate, Forming a gate electrode of the first thin film transistor, a gate electrode of the second thin film transistor, the gate signal line, and one electrode of a capacitor; A step of forming an insulating film covering the gate electrode of the thin film transistor, the gate electrode of the second thin film transistor, the gate signal line, and one electrode of the capacitor; and a first amorphous film dehydrogenated on the insulating film A step of forming a porous silicon semiconductor layer, a step of transforming the first amorphous silicon semiconductor layer in a formation region of the first thin film transistor into a polycrystalline silicon semiconductor layer, a formation region of the first thin film transistor, and a wiring intersection Forming a first mask in the region, and sequentially etching a part of the second thin film transistor and the capacitive element from the surface of the amorphous silicon semiconductor layer and the insulating film in the formation region; The mask is removed, and the polycrystalline silicon semiconductor layer and the first amorphous silicon semiconductor layer are covered on the insulating film. Forming a second mask in a region where the first thin film transistor is formed, a region where the second thin film transistor is formed, and a region where the wiring intersects; Etching a part from the surface of the insulating film.

  The above-described configuration is merely an example, and the present invention can be modified as appropriate without departing from the technical idea. Further, examples of the configuration of the present invention other than the above-described configuration will be clarified from the entire description of the present specification or the drawings.

  According to the display device of the present invention, the gate insulating film of the thin film transistor including the amorphous silicon semiconductor layer, the gate insulating film of the thin film transistor including the polycrystalline silicon semiconductor layer, and the interlayer insulating film at the wiring intersection without increasing the mask process. , Each can be formed with an appropriate thickness.

  According to the display device of the present invention, without increasing the mask process, the gate insulating film of the thin film transistor including the amorphous silicon semiconductor layer, the gate insulating film of the thin film transistor including the polycrystalline silicon semiconductor layer, the dielectric film in the capacitor element, and The interlayer insulating films at the wiring intersections can be formed with appropriate thicknesses.

  Other effects of the present invention will become apparent from the description of the entire specification.

  Embodiments of the present invention will be described with reference to the drawings. In each drawing and each example, the same or similar components are denoted by the same reference numerals and description thereof is omitted.

<Example 1>
(Overall configuration of display device)
FIG. 2 is a plan view showing Embodiment 1 of the display device according to the present invention. FIG. 2 shows an overall configuration of a liquid crystal display device incorporated in, for example, a mobile phone.

  In FIG. 2, the liquid crystal display device is configured to form an envelope by a rectangular substrate SUB1 and a substrate SUB2 made of, for example, glass. A liquid crystal (not shown) is sandwiched between the substrate SUB1 and the substrate SUB2, and this liquid crystal is sealed by a sealing material SL that fixes the substrate SUB1 and the substrate SUB2. The region in which the liquid crystal is sealed by the sealing material SL has a liquid crystal display region AR. The liquid crystal display area AR is an area where a plurality of pixels are arranged in a matrix.

  The lower side portion of the substrate SUB1 has a portion exposed from the substrate SUB2, and one end of a flexible substrate FPC for inputting a signal from the outside is connected to this portion. On the substrate SUB1, a semiconductor device SCN made of a chip is mounted in a region between the flexible substrate FPC and the substrate SUB2. In this semiconductor device SCN, each signal from the flexible substrate FPC is input via a wiring WL formed on the surface of the substrate SUB1.

  Further, a scanning signal driving circuit V is formed in a region between the sealing material SL and the liquid crystal display region AR, for example, in a left region of the liquid crystal display region AR, and an RGB switching circuit RGBS is formed in a lower region. . Signals are supplied from the semiconductor device SCN to the scanning signal drive circuit V and the RGB switching circuit RGBS. The scanning signal driving circuit V includes a circuit for sequentially supplying scanning signals to a plurality of gate signal lines GL, which will be described later, and the RGB switching circuit RGBS uses red and green video signals to be supplied to a plurality of drain signal lines DL, which will be described later. And a circuit that switches in time series for each blue and blue color.

  Here, the scanning signal driving circuit V and the RGB switching circuit RGBS are circuits formed on the substrate SUB1 in parallel with the formation of the pixels in the liquid crystal display area AR. For example, a polycrystalline silicon semiconductor layer made of poly-Si is used. A plurality of thin film transistors TFT (indicated by reference numeral TFT (p) in the figure) are provided. This is because these thin film transistors TFT (p) can be configured as transistors having excellent charge mobility.

  A gate signal line GL and a drain signal line DL are formed in the liquid crystal display area AR. The gate signal lines GL extend in the x direction in the figure and are arranged in parallel in the y direction, and their left ends are connected to the scanning signal drive circuit V. The drain signal lines DL extend in the y direction in the drawing and are juxtaposed in the x direction, and their lower ends are connected to the RGB switching circuit RGBS. Each gate signal line GL and each drain signal line DL are formed in different layers with an insulating film (not shown) interposed therebetween, and the gate signal line GL and the drain signal line DL are connected to a wiring intersection (described later) at the intersection. Middle code WI).

  A region surrounded by a pair of adjacent gate signal lines GL and a pair of adjacent drain signal lines DL (for example, within a dotted oval frame in the drawing) corresponds to the region of the pixel PIX. As shown in an equivalent circuit diagram in the solid oval frame A in the figure, the pixel PIX is turned on by a thin film transistor TFT (indicated by a symbol TFT (a) in the figure) that is turned on by a scanning signal from the gate signal line GL. The pixel electrode PX to which the video signal from the drain signal line DL is supplied via the thin film transistor TFT (a), and the capacitive element CP formed between the pixel electrode PX and the capacitive signal line CL are provided. .

  In the thin film transistor TFT (a), the semiconductor layer is, for example, an amorphous silicon semiconductor layer of amorphous Si. This is because the thin film transistor TFT (a) in the pixel does not require a high charge mobility like the thin film transistor TFT (p) in the scanning signal drive circuit V, for example.

  The capacitive element CP is provided to store the video signal (information) supplied to the pixel electrode PX for a relatively long time. Further, the capacitance signal line CL is formed, for example, in the same layer as the gate signal line GL in parallel with the gate signal line GL.

  In FIG. 2, a liquid crystal display device incorporated in a mobile phone is described as an example, but the present invention is not limited to this type of liquid crystal display device.

  Further, the pixel shown in FIG. 2 shows a structure called a so-called vertical electric field method. However, the present invention is not limited to this, and can be applied to, for example, a pixel called a horizontal electric field method. In this case, in the horizontal electric field type pixel, the counter electrode is formed on the substrate side on which the pixel electrode is formed, and a capacitor is easily formed between the pixel electrode and the counter electrode. CP may not be provided.

(Configuration on the liquid crystal side surface of the substrate SUB1)
FIG. 1 is a diagram showing a cross section of thin film transistors TFT (p), TFT (a), a capacitor element CP, and a wiring intersection WI formed on the liquid crystal side of the substrate SUB1.

  In FIG. 1, the thin film transistor TFT (p), the thin film transistor TFT (a), the capacitive element CP, and the wiring intersection WI are sequentially shown from the left side to the right side.

  As described above, the thin film transistor TFT (p) of the polycrystalline silicon semiconductor layer is formed in the scanning signal driving circuit V and the RGB switching circuit RGBS. The thin film transistor TFT (a) of the amorphous silicon semiconductor layer is formed in the pixel PIX. The capacitive element CP is formed in the pixel PIX. The wiring intersection WI is an intersection between the gate signal line GL and the drain signal line DL.

  In addition, in each material shown in FIG. 1, those having the same hatching or pattern attached thereto are formed by selective etching by the photolithography technique and are in the same layer. Yes.

  The thin film transistor TFT (p) and the thin film transistor TFT (a) each have a so-called bottom gate structure in which a gate electrode is formed below the semiconductor layer.

  Hereinafter, the configuration of the thin film transistor TFT (p), the thin film transistor TFT (a), the capacitor element CP, and the wiring intersection WI will be described in order.

(Configuration of thin film transistor TFT (p))
A gate electrode GT1 is formed on the surface of the substrate SUB1, and an insulating film GI is formed covering the gate electrode GT1. This insulating film GI functions as a gate insulating film of the thin film transistor TFT (p). Here, the insulating film GI has the highest surface (first height H1) in the upper surface of the gate electrode GT1, and is lower by one step as the distance from the gate electrode GT1 increases in plan view. A surface (second height) and a further lower surface (lowest surface: third height H3) are formed, and are formed so as to have two step portions DIL1 and DIL2 in total. . The thickness of the insulating film GI determined by the highest surface of the insulating film GI is determined based on the characteristics to be obtained by the thin film transistor TFT (p). A polycrystalline silicon semiconductor layer PS made of poly-Si is formed on the highest surface of the insulating film GI, and an amorphous silicon semiconductor layer AS made of amorphous Si is formed on the upper surface thereof. The sequential stacked body of the polycrystalline silicon semiconductor layer PS and the amorphous silicon semiconductor layer AS is formed so as to intersect the running direction of the gate electrode GT1 (perpendicular to the drawing sheet). On the surface of the amorphous silicon semiconductor layer AS, a pair of electrodes (source / drain electrodes SD) facing each other with a region above the gate electrode GT1 (corresponding to a channel region) in between is formed. The drain electrode SD is formed of the gate insulating film GI along the side wall surfaces of the amorphous silicon semiconductor layer AS and the polycrystalline silicon semiconductor layer AS and the side wall surfaces formed by the step portions DIL1 and DIL2 of the gate insulating film GI. It extends to the lowest side of the. A protective film PAS is formed on the surface of the substrate SUB1 covering the source / drain electrodes SD. This protective film PAS is provided in order to avoid direct contact of the thin film transistor TFT (p) with the liquid crystal.

(Configuration of thin film transistor TFT (a))
A gate electrode GT2 is formed on the surface of the substrate SUB1, and an insulating film GI is formed to cover the gate electrode GT2. This insulating film GI functions as a gate insulating film of the thin film transistor TFT (a). Here, the insulating film GI has the highest surface (fourth height H4) in the upper surface of the gate electrode GT2, and is lower by one step as the distance from the gate electrode GT2 increases in plan view. A surface (the lowest surface: the third height H3) is formed, and is formed to have one step portion DIL3. The film thickness of the insulating film GI determined by the highest surface (fourth height H4) of the insulating film GI is determined based on the characteristics to be obtained by the thin film transistor TFT (a), and the above-described thin film transistor TFT (p). The thickness is lower than the thickness of the insulating film GI determined by the highest surface (first height H1). Then, an amorphous silicon semiconductor layer AS made of amorphous Si is formed on the highest surface (fourth height H4) of the insulating film GI. The amorphous silicon semiconductor layer AS is formed so as to intersect the running direction of the gate electrode GT2 (perpendicular to the drawing sheet). On the surface of the amorphous silicon semiconductor layer AS, a pair of electrodes (source / drain electrodes SD) facing each other with a region above the gate electrode GT (corresponding to a channel region) in between are formed. Is on the lowest surface (third height H3) of the gate insulating film GI along the side wall surface of the amorphous silicon semiconductor layer AS and each side wall surface formed by the step portion DIL3 of the gate insulating film GI. Has been extended to. A protective film PAS is formed on the surface of the substrate SUB1 covering the source / drain electrodes SD. A pixel electrode PX is formed on the surface of the protective film PAS, and a part of the pixel electrode PX is connected to one of the pair of electrodes (source / drain electrodes SD) through a through hole TH formed in the protective film PAS. Electrically connected.

(Configuration of capacitive element CP)
One electrode AT of each electrode of the capacitive element CP is formed on the surface of the substrate SUB1, and an insulating film GI serving as a dielectric film is formed covering the electrode AT. Here, the insulating film GI has the lowest surface (third height H3), and the film thickness is determined based on characteristics to be obtained by the capacitive element CP. On the upper surface of the insulating film GI, the other electrode OT among the electrodes of the capacitive element CP is formed so as to overlap the electrode AT. A protective film PAS is formed on the surface of the substrate SUB1 covering the electrode OT.

(Configuration of wiring intersection WI)
A gate signal line GL is formed on the surface of the substrate SUB1, and an insulating film GI is formed covering the gate signal line GL. Here, the insulating film GI has the highest surface (first height H1) in the upper surface of the gate signal line GL, and is lower by one step as it is farther from the gate signal line GL in plan view. The lower surface and the lower surface (the lowest surface: the third height H3) are formed, and are formed so as to have two step portions DIL1 and DIL2 in total. An amorphous silicon semiconductor layer AS ′ made of amorphous Si and an amorphous silicon semiconductor layer AS are sequentially stacked on the highest surface (first height H1) of the insulating film GI. The amorphous silicon semiconductor layer AS ′ is a dehydrogenated semiconductor layer. A sequential stack of the insulating film GI, the amorphous silicon semiconductor layer AS ′, and the amorphous silicon semiconductor layer AS is configured as an interlayer film at the wiring intersection WI. A drain signal line DL is disposed on the upper surface of the amorphous silicon semiconductor layer AS so as to intersect the gate signal line GL. The drain signal line DL is formed of the amorphous silicon semiconductor layer AS and the amorphous silicon semiconductor layer AS ′. Are extended to the lowest surface (third height H3) of the gate insulating film GI along the respective side wall surfaces formed by the step portions DIL1 and DIL2 of the gate insulating film GI. A protective film PAS is formed on the surface of the substrate SUB1 so as to cover the drain signal line DL.

(Production method)
3 (a) to (c), FIGS. 4 (d) to (f), FIGS. 5 (g) to (i), and FIGS. 6 (j) and 6 (k) show the method for manufacturing the display device of the present invention. It is a series of process diagrams showing the embodiment. The drawings showing these steps are drawn corresponding to FIG. 1 and show the thin film transistor TFT (p), the thin film transistor TFT (a), the capacitor element CP, and the wiring intersection WI from the right side to the left side in the drawing. . Hereinafter, it demonstrates in order of a process.

Step 1. (Fig. 3 (a))
For example, a substrate SUB1 made of glass is prepared, and a patterned metal film is formed on the main surface of the substrate SUB1. This metal film has a gate electrode GT1 in the formation region of the thin film transistor TFT (p) of the polycrystalline silicon semiconductor layer, and a gate electrode GT2 in the formation region of the thin film transistor TFT (a) of the amorphous silicon semiconductor layer. One electrode AT is formed in the formation region of the capacitive element CP, and the gate signal line GL is formed in the wiring intersection region.

Step 2. (Fig. 3 (b))
An insulating film GI having a first height H1 is formed on the main surface of the substrate SUB1 so as to cover the gate electrode GT1, the gate electrode GT2, the electrode AT, and the gate signal line GL. The insulating film GI is formed in accordance with the characteristics to be obtained by the thin film transistor TFT (p), and the film thickness is set to a film thickness value as a gate insulating film of the thin film transistor TFT (p).

  Then, a semiconductor layer AS made of dehydrogenated amorphous Si (a-Si) is formed on the upper surface of the insulating film GI.

Step 3. (Fig. 3 (c))
The semiconductor layer AS in the formation region of the thin film transistor TFT (p) of the polycrystalline silicon semiconductor layer (or the surrounding region may be included) is polycrystallized by, for example, laser light irradiation, and is made of poly-Si (p-Si). The resulting semiconductor layer PS is altered. The semiconductor layer AS in the remaining region is left as it is as the semiconductor layer AS ′.

Step 4. (Fig. 4 (d))
A patterned photoresist film RES1 is formed in the formation region of the thin film transistor TFT (p). At the same time as the formation of the photoresist film RES1, a patterned photoresist film RES2 is formed in the region of the wiring intersection WI.

  These photoresist film RES1 and photoresist film RES2 become photoresist films for holding the insulating film GI in the region where the thin film transistor TFT (p) is formed and the region where the wiring intersects without changing the film thickness. .

  Then, using the photoresist film RES1 and the photoresist film RES2 as a mask, the surface of the semiconductor layer PS and the semiconductor layer AS ′ exposed from the mask and the insulating film GI below them are etched (for example, dry etching), The film thickness (fourth height H4) of the insulating film GI is set to a predetermined value.

  The insulating film GI to be etched is formed in accordance with the characteristics to be obtained by the thin film transistor TFT (a), and the film thickness is set to a film thickness value as a gate insulating film of the thin film transistor TFT (a).

Step 5. (Fig. 4 (e))
The photoresist film RES1 and the photoresist film RES2 are removed. Then, a semiconductor layer AS made of amorphous Si is formed on the upper surfaces of the semiconductor layer PS and the insulating film GI.

Step 6. (Fig. 4 (f))
Patterned photoresist films RES3, RES4, and RES5 are formed in the formation region of the thin film transistor TFT (p), the formation region of the thin film transistor TFT (a), and the region of the cross wiring portion WI, respectively. The photoresist film RES3 is formed on the formation region of the semiconductor layer of the thin film transistor TFT (p), the photoresist film RES4 is formed on the formation region of the thin film transistor TFT (a), and the photoresist film RES5 includes the wiring intersection WI and Formed on its periphery.

  The photoresist film RES5 formed on the wiring intersection WI and its periphery is provided in order to use the underlying semiconductor layer AS and semiconductor layer AS ′ as an interlayer insulating film.

  Using the photoresist films RES3, RES4, and RES5 as a mask, etching is performed with a part of the insulating film GI remaining. In this case, the etching is performed in the capacitor element CP so that the insulating film GI serving as a dielectric film has a predetermined thickness (third height H3).

  In this case, in the formation region of the thin film transistor TFT (p), the insulating film GI has a first height surface (first height H1) which is the uppermost surface on the surface above the gate electrode GT1, and is planar. As shown in the figure, the outer surface of the gate electrode GT1 is formed to have a shape reaching the third height surface (third height H3) which has the two step portions DIL1 and DIL2 and becomes the lowermost surface as the distance from the gate electrode GT1 increases. It becomes like this. In the region where the thin film transistor TFT (a) is formed, the insulating film GI has a fourth height surface (fourth height H4) lower than the first height surface on the surface above the gate electrode GT2. And having a stepped portion DIL3 outside the gate electrode and having a shape that reaches the third height surface (third height H3). Further, in the formation region of the wiring intersection WI, the insulating film GI has a first height surface (first height H1) which is the uppermost surface on the surface above the gate signal line GL, and is planar. As seen from the gate signal line GL, it is formed in a shape that has two step portions DIL1 and DIL2 and reaches the third height surface (third height H3) that is the bottom surface as it goes farther outward. It becomes like this.

Step 7. (Fig. 5 (g))
A metal film MT is formed over the entire surface of the substrate SUB1 processed in this way.

Step 8. (Fig. 5 (h))
The metal film MT is formed in a predetermined pattern by selective etching using a photolithography technique. As a result, the source / drain electrode SD is formed in the formation region of the thin film transistor TFT (p), the source / drain electrode SD is formed in the formation region of the thin film transistor TFT (a), and the other electrode OT is formed in the formation region of the capacitive element CP. The drain signal line DL is formed in the wiring intersection forming region.

Step 9. (Fig. 5 (i))
A protective film PAS is formed over the entire surface of the substrate SUB1 processed in this way.

Step 10. (Fig. 6 (j))
A through hole TH is formed in a part of the protective film PAS, and a part of one of the source / drain electrodes SD of the thin film transistor TFT (a) is exposed.

Step 11. (Fig. 6 (k))
A transparent conductive film made of, for example, ITO is formed over the entire surface of the substrate SUB1 processed in this manner, and the pixel electrode PX is formed by performing selective etching using a photolithography technique.

<Example 2>
In the embodiment described above, the pixel PIX includes the capacitive element CP, and the capacitive element CP is formed in parallel with the thin film transistor TFT. However, the capacitor element CP is not necessarily formed in parallel. This is because, for example, in a horizontal electric field type liquid crystal display device, the pixels may not include the capacitor element CP.

<Example 3>
In the above-described embodiments, the liquid crystal display device has been described as an example. However, the present invention is not necessarily limited to the liquid crystal display device, and can be applied to other display devices such as an organic EL display device.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing an embodiment of a display device of the present invention, and shows a thin film transistor of a polycrystalline silicon semiconductor layer, a thin film transistor of an amorphous silicon semiconductor layer, a capacitor element, and a wiring intersection from the left side to the right side in the figure. Yes. It is a schematic plan view which shows one Example of the display apparatus of this invention. It is a figure which shows the process of one Example of the manufacturing method of the display apparatus of this invention, and is a figure which shows a series of processes with FIG.4, FIG.5, FIG.6. It is a figure which shows the process of one Example of the manufacturing method of the display apparatus of this invention, and is a figure which shows a series of processes with FIG.3, FIG.5, FIG.6. It is a figure which shows the process of one Example of the manufacturing method of the display apparatus of this invention, and is a figure which shows a series of processes with FIG.3, FIG.4, FIG.6. It is a figure which shows the process of one Example of the manufacturing method of the display apparatus of this invention, and is a figure which shows a series of processes with FIG.3, FIG.4, FIG.5.

Explanation of symbols

SUB1, SUB2 ... Substrate, SL ... Sealing material, AR ... Liquid crystal display area, PIX ... Pixel, FPC ... Flexible substrate, SCN ... Semiconductor device, V ... Scanning signal drive circuit, RGBS ... RGB switching Circuit, GL: Gate signal line, DL: Drain signal line, CL: Capacitance signal line, TFT: Thin film transistor, TFT (p) ... Thin film transistor (polycrystalline silicon semiconductor layer), TFT (a): Thin film transistor (Amorphous silicon semiconductor layer), PX ... Pixel electrode, CP ... Capacitor element, GT1, GT2 ... Gate electrode, DIL1, DIL2 ... Stepped portion, AT ... One electrode of capacitor element, OT ... The other electrode of the capacitive element, GI... Insulating film, AS... Amorphous silicon semiconductor layer, PS... Polycrystalline silicon semiconductor layer, RES1 to RES5. Photoresists film, SD ...... source-drain electrode, PAS ...... protective film.

Claims (12)

A display device having a bottom gate first thin film transistor and a second thin film transistor, a gate signal line, and a drain signal line on an insulating substrate,
The first gate electrode of the first thin film transistor, the second gate electrode of the second thin film transistor, and the gate signal line are formed in the same layer,
The source / drain electrodes of the first thin film transistor, the source / drain electrodes of the second thin film transistor, and the drain signal line are formed in the same layer,
The gate signal line and the drain signal line have wiring intersections that cross each other through an interlayer film,
A first insulating film covering the first gate electrode has a first height, a second height smaller than the first height, and a third height smaller than the second height;
The region of the first insulating film in which the second height is formed is farther from the first gate electrode in plan view than the region in which the first height is formed. ,
The region of the first insulating film in which the third height is formed is farther from the first gate electrode in a plan view than the region in which the second height is formed. ,
A polycrystalline silicon semiconductor layer and an amorphous silicon semiconductor layer that are sequentially stacked are formed on the first height surface of the first insulating film,
A second insulating film covering the second gate electrode has a fourth height smaller than the first height and the third height;
The region of the second insulating film in which the third height is formed is farther from the second gate electrode in plan view than the region in which the fourth height is formed. ,
An amorphous silicon semiconductor layer is formed on the fourth height surface of the second insulating film,
The interlayer film has a third insulating film and an amorphous silicon semiconductor layer covering the gate signal line,
The third insulating film has the first height, the second height, and the third height,
A display device, wherein an amorphous silicon semiconductor layer is formed on the first height surface of the third insulating film. The insulating substrate has a display area part having a plurality of pixels, and a peripheral circuit part surrounding the display area part,
The display device according to claim 1, wherein the first thin film transistor is formed in the peripheral circuit portion.   The display device according to claim 2, wherein the first thin film transistor is formed in a scanning signal driving circuit.   The display device according to claim 2, wherein the first thin film transistor is formed in an RGB switching circuit.   The display device according to claim 1, wherein the two thin film transistors are formed in a pixel.   The amorphous silicon semiconductor layer formed on the first height surface of the third insulating film is formed on the first amorphous silicon semiconductor layer and the first amorphous silicon semiconductor layer. 6. The display device according to claim 1, further comprising a second amorphous silicon semiconductor layer.   The display device according to claim 6, wherein the second amorphous silicon semiconductor layer has a hydrogen concentration higher than that of the first amorphous silicon semiconductor layer.   The first amorphous silicon semiconductor layer is formed in the same layer as the polycrystalline silicon semiconductor layer formed on the first height surface of the insulating film covering the first gate electrode. The display device according to claim 6 or 7. A capacitance signal line in the same layer as the one gate electrode and an electrode in the same layer as the drain / source electrode superimposed on the capacitance signal line via a fourth insulating film are formed on the insulating substrate. With a capacitive element
The display device according to claim 1, wherein the fourth insulating film has the third height.   The display device according to claim 9, wherein the capacitive element is formed in a pixel. A first thin film transistor and a second thin film transistor having a bottom gate structure having a gate electrode as the same layer on an insulating substrate, a gate signal line in the same layer as the gate electrode, and source / drain electrodes of the first thin film transistor and the second thin film transistor And a drain signal line in the same layer,
A method of manufacturing a display device including a wiring intersection where the gate signal line and the drain signal line intersect each other,
On the insulating substrate,
Forming a gate electrode of the first thin film transistor, a gate electrode of the second thin film transistor, and the gate signal line;
Forming an insulating film covering the gate electrode of the first thin film transistor, the gate electrode of the second thin film transistor, and the gate signal line;
Forming a dehydrogenated first amorphous silicon semiconductor layer on the insulating film;
Transforming the first amorphous silicon semiconductor layer in the formation region of the first thin film transistor into a polycrystalline silicon semiconductor layer;
Forming a mask in a region where the first thin film transistor is formed and a region where wiring intersects, and sequentially etching portions of the amorphous silicon semiconductor layer and the insulating film in the formation region of the second thin film transistor from the surface; ,
Removing the mask, and covering the polycrystalline silicon semiconductor layer and the first amorphous silicon semiconductor layer to form a second amorphous silicon semiconductor layer on the insulating film. A method for manufacturing a display device. A first thin film transistor and a second thin film transistor having a bottom gate structure having a gate electrode as the same layer on an insulating substrate, a gate signal line in the same layer as the gate electrode, and source / drain electrodes of the first thin film transistor and the second thin film transistor And a drain signal line in the same layer,
An insulating film is interposed between the wiring intersection where the gate signal line and the drain signal line intersect each other, and one electrode in the same layer as the gate electrode and the other electrode in the same layer as the source / drain electrode A manufacturing method of a display device comprising a capacitive element,
On the insulating substrate,
Forming a gate electrode of the first thin film transistor, a gate electrode of the second thin film transistor, the gate signal line, and one electrode of a capacitor;
Forming an insulating film covering the gate electrode of the first thin film transistor, the gate electrode of the second thin film transistor, the gate signal line, and one electrode of the capacitor;
Forming a dehydrogenated first amorphous silicon semiconductor layer on the insulating film;
Transforming the first amorphous silicon semiconductor layer in the formation region of the first thin film transistor into a polycrystalline silicon semiconductor layer;
A first mask is formed in a region where the first thin film transistor is formed and a region where the wiring intersects, and the first thin film transistor and the capacitor element are formed from the surface of the amorphous silicon semiconductor layer and the insulating film in each formation region of the capacitor. Etching the parts sequentially,
Removing the first mask and covering the polycrystalline silicon semiconductor layer and the first amorphous silicon semiconductor layer to form a second amorphous silicon semiconductor layer on the insulating film;
Forming a second mask in a region where the first thin film transistor is formed, a region where the second thin film transistor is formed, and a region where wiring intersects, and etching a part from the surface of the insulating film in the region where the capacitor element is formed And a method of manufacturing a display device.

Images