KR102573966B1 - Display device having a intermediate supply line disposed adjacent to a pixel area, and Method for fabricating the same - Google Patents

Abstract

The present invention relates to a display device in which an intermediate supply wiring is located on a wiring area adjacent to a pixel area. The intermediate supply wire may supply a specific voltage, for example, a common voltage, to pixels positioned within the pixel area. The intermediate supply wire may have a lower reflectance than a gate electrode of a thin film transistor positioned in the pixel area. Accordingly, in the display device according to the embodiment of the present invention, reflectance of the intermediate supply wire may be reduced. Therefore, in the display device according to the embodiment of the present invention, degradation of image quality caused by light reflected from the wiring area can be minimized.

Description

Display device having an intermediate supply line disposed adjacent to a pixel area, and Method for fabricating the same

The present invention relates to a display device in which an intermediate supply wire for supplying a specific voltage to each pixel located in a pixel area is located on a wiring area adjacent to a pixel area, and a method of manufacturing the same.

In general, electronic devices such as monitors, TVs, laptop computers, digital cameras, and the like include display devices for implementing images. For example, the display device may include a liquid crystal display device and/or an organic light emitting display device.

The display device may include a plurality of pixels to implement an image according to a user's request. Each pixel may include a thin film transistor and a pixel electrode electrically connected to the thin film transistor. The display device may further include at least one driving driver generating a signal for controlling each pixel, for example, controlling the thin film transistor.

The driving driver may be located outside a pixel area where the plurality of pixels are located. A wiring area may be positioned between the driving driver and the pixel area, in which wires for transmitting signals for controlling each pixel are formed. For example, an intermediate supply wire supplying a specific voltage, such as a common voltage, to each pixel may be positioned on the wiring area.

The intermediate supply wire may include a material having high conductivity. The intermediate supply wiring may be formed using the process of forming the thin film transistor. For example, the intermediate supply wire may include the same metal as the gate electrode of the thin film transistor. However, in the display device, since the intermediate supply wiring has a high reflectance, the light incident to the wiring area is reflected by the intermediate supply wiring, and thus the quality of the implemented image may be degraded. For example, in a liquid crystal display device in which light is supplied from a backlight unit to a liquid crystal panel, since light reflected from a wiring area of the liquid crystal panel may be reflected back by an optical sheet of the backlight unit, reflection of the intermediate supply wiring As a result, a bright line may occur at the edge of the pixel area.

An object of the present invention is to provide a display device capable of minimizing deterioration of image quality caused by reflection in a wiring area and a manufacturing method thereof.

The problems to be solved by the present invention are not limited to the aforementioned problems. Subjects not mentioned herein will become clear to those skilled in the art from the following description.

A display device according to the technical idea of the present invention for achieving the above object includes an array substrate. The array substrate includes a pixel area and a wiring area. The wiring area is located adjacent to the pixel area. A plurality of pixels are positioned on the pixel area of the array substrate. Each pixel includes a thin film transistor and a pixel electrode. A pixel electrode of each pixel is electrically connected to a thin film transistor of the corresponding pixel. An intermediate supply wiring and a dummy electrode pattern are positioned on the wiring area of the array substrate. The intermediate supply wiring carries a specific voltage or signal to each pixel. The dummy electrode pattern is located on the same layer as the pixel electrode. The intermediate wiring has higher conductivity than the dummy electrode pattern and lower reflectance than the gate electrode of the thin film transistor.

The intermediate supply wiring may include a region overlapping the dummy electrode pattern.

A lower surface of the pixel electrode facing the array substrate may be coplanar with a lower surface of the gate electrode facing the array substrate.

The gate electrode may have a stacked structure of a first electrode layer and a second electrode layer. The first electrode layer of the gate electrode may include the same material as the pixel electrode. The second electrode layer of the gate electrode may have higher conductivity than the first electrode layer of the gate electrode.

A source electrode of the thin film transistor may have a lower reflectance than a gate electrode of the thin film transistor. The intermediate supply wiring may have the same structure as the source electrode of the thin film transistor.

The source electrode of the thin film transistor may have a stacked structure of a first electrode layer and a second electrode layer. The second electrode layer of the source electrode may have higher conductivity than the first electrode layer of the source electrode.

Each pixel may further include a common electrode including at least one slit overlapping the corresponding pixel electrode. The common electrode may be connected to the intermediate supply wire.

Each pixel may further include a planarization layer positioned between the pixel electrode and the common electrode. A gate insulating layer of the thin film transistor may extend between the corresponding pixel electrode and the planarization layer.

Each pixel may further include a pixel connection wire connecting the thin film transistor and the pixel electrode. The pixel connection line may include the same material as the common electrode.

A common voltage supply line and an intermediate connection line may be positioned on the wiring area of the array substrate. The intermediate connection wire may connect the intermediate supply wire to the common voltage supply wire. The common voltage supply wire may have the same structure as the gate electrode of the thin film transistor.

A dummy semiconductor pattern may be positioned between the dummy electrode pattern and the intermediate supply line.

The dummy semiconductor pattern may include the same material as the semiconductor pattern of the thin film transistor.

In the display device and method of manufacturing the display device according to the technical concept of the present invention, an intermediate supply line positioned on a wiring area adjacent to a pixel area may have a lower reflectance than a gate electrode of a thin film transistor positioned within the pixel area. Accordingly, in the display device and the manufacturing method according to the technical idea of the present invention, re-introduction of light supplied from a backlight unit or the outside to the wiring area into the pixel area can be minimized. Accordingly, in the display device and the manufacturing method according to the technical idea of the present invention, the quality of implemented images can be improved.

1 is a schematic diagram of a display device according to an embodiment of the present invention.
FIG. 2 is an enlarged view of region P of FIG. 1 .
FIG. 3 is a view taken along line II′ of FIG. 2 .
4 and 5 are diagrams each illustrating a display device according to another embodiment of the present invention.
6 to 11 are diagrams sequentially illustrating a method of manufacturing a display device according to an embodiment of the present invention.

The above objects and technical configurations of the present invention and details of the operation and effect thereof will be more clearly understood by the following detailed description with reference to the drawings illustrating the embodiments of the present invention. Here, since the embodiments of the present invention are provided to sufficiently convey the technical spirit of the present invention to those skilled in the art, the present invention may be embodied in other forms so as not to be limited to the embodiments described below.

Also, parts denoted by the same reference numerals throughout the specification mean the same components, and the length and thickness of a layer or region in the drawings may be exaggerated for convenience. In addition, when a first component is described as being “on” a second component, the first component is not only located on the upper side in direct contact with the second component, but also the first component and the second component. A case where the third component is located between the second components is also included.

Here, terms such as first and second are used to describe various components, and are used for the purpose of distinguishing one component from another. However, the first component and the second component may be named arbitrarily according to the convenience of those skilled in the art within the scope of the technical idea of the present invention.

Terms used in the specification of the present invention are only used to describe specific embodiments, and are not intended to limit the present invention. For example, a component expressed in the singular number includes a plurality of components unless the context clearly indicates only the singular number. In addition, in the specification of the present invention, terms such as "comprise" or "having" are intended to designate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, but one or It should be understood that it does not preclude the possibility of the presence or addition of more other features, numbers, steps, operations, components, parts, or combinations thereof.

In addition, unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and unless explicitly defined in the specification of the present invention, in an ideal or excessively formal meaning. not interpreted

(Example)

1 is a schematic diagram of a display device according to an embodiment of the present invention. FIG. 2 is an enlarged view of region P of FIG. 1 . FIG. 3 is a view taken along line II′ of FIG. 2 .

Referring to FIGS. 1, 2 and 3 , a display device according to an embodiment of the present invention may include an array substrate 110 . The array substrate 110 may include an insulating material. The array substrate 110 may include a transparent material. For example, the array substrate 110 may include plastic or glass.

The array substrate 110 may include a display area AA. The display area AA may implement an image according to a user's request. At least one driving driver 10 , 20 , or 30 generating a signal for realizing an image may be positioned outside the display area AA. For example, a data driver 10 generating a data signal, a gate driver 20 generating a gate signal, and a common voltage supply source 30 generating a common voltage may be positioned outside the display area AA. there is.

The display area AA may include a pixel area PA and a wiring area LA. A gate line GL for transmitting the gate signal and a data line DL for transmitting the data signal may be positioned in the pixel area PA. The data line DL may cross the gate line GL. For example, a plurality of pixels defined by the gate line GL and the data line DL may be located in the pixel area PA.

Each pixel may include a driving thin film transistor TR. The driving thin film transistor TR may be controlled by the gate signal and the data signal. For example, the driving thin film transistor TR may include a driving gate electrode 210, a driving gate insulating layer 220, a driving semiconductor pattern 230, a driving source electrode 240, and a driving drain electrode 250. there is.

The driving gate electrode 210 may be positioned close to the array substrate 110 . For example, the driving gate electrode 210 may directly contact the array substrate 110 . The driving gate electrode 210 may include a conductive material. The driving gate electrode 210 may have a multilayer structure. For example, the driving gate electrode 210 may have a stacked structure of a transparent gate electrode layer 211 and a highly conductive gate electrode layer 212 .

The transparent gate electrode layer 211 may have higher transmittance than the highly conductive gate electrode layer 212 . For example, the transparent gate electrode layer 211 may include ITO or IZO. The highly conductive gate electrode layer 212 may have higher conductivity than the transparent gate electrode layer 211 . For example, the highly conductive gate electrode layer 212 may include metals such as aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W).

The driving gate electrode 210 may be electrically connected to the gate line GL. The gate line GL may have the same structure as the driving gate electrode 210 . For example, the driving gate electrode 210 may protrude from the gate line GL extending in one direction.

The driving gate insulating layer 220 may be positioned on the driving gate electrode 210 . The driving gate insulating layer 220 may extend outward of the driving gate electrode 210 . For example, side surfaces of the driving gate electrode 210 may be covered by the driving gate insulating layer 220 .

The driving gate insulating layer 220 may include an insulating material. For example, the driving gate insulating layer 220 may include silicon oxide and/or silicon nitride. The driving gate insulating layer 220 may include a high-K material. For example, the driving gate insulating layer 220 may include hafnium oxide (HfO) or titanium oxide (TiO).

The driving semiconductor pattern 230 may be positioned on the driving gate insulating layer 220 . The driving semiconductor pattern 230 may overlap the driving gate electrode 210 . For example, the driving semiconductor pattern 230 may be insulated from the driving gate electrode 210 by the driving gate insulating layer 220 .

The driving semiconductor pattern 230 may include a semiconductor material. For example, the driving semiconductor pattern 230 may include amorphous silicon or polycrystalline silicon. The driving semiconductor pattern 230 may be an oxide semiconductor. For example, the driving semiconductor pattern 230 may include IGZO.

The driving semiconductor pattern 230 may include a source region, a drain region, and a channel region. The channel region may be positioned between the source region and the drain region. The channel region may have lower conductivity than the source region and the drain region. For example, the source region and the drain region may include conductive impurities.

The driving source electrode 240 may be electrically connected to the source region of the driving semiconductor pattern 230 . For example, the driving source electrode 240 may directly contact the source region of the driving semiconductor pattern 230 .

The driving source electrode 240 may include a conductive material. For example, the driving source electrode 240 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). The driving source electrode 240 may have a lower reflectance than the driving gate electrode 210 . For example, the driving source electrode 240 may have a stacked structure of a low reflection source electrode layer 241 and a high conductivity source electrode layer 242 .

The low-reflection source electrode layer 241 may be positioned close to the driving gate insulating layer 220 . For example, the low reflection source electrode layer 241 may be positioned between the driving gate insulating layer 220 and the high conductivity source electrode layer 242 . The low reflection source electrode layer 241 may have a lower reflectance than the high conductivity source electrode layer 242 . The high conductivity source electrode layer 242 may have higher conductivity than the low reflection source electrode layer 241 .

The driving source electrode 240 may be electrically connected to the data line DL. The data line DL may include the same material as the driving source electrode 240 . For example, the driving source electrode 240 may protrude from the data line DL extending in one direction.

The driving drain electrode 250 may be electrically connected to the drain region of the driving semiconductor pattern 230 . For example, the driving drain electrode 250 may directly contact the drain region of the driving semiconductor pattern 230 . The driving drain electrode 250 may be spaced apart from the driving source electrode 240 . For example, the driving source electrode 240 and the driving drain electrode 250 may expose the channel region of the driving semiconductor pattern 230 .

In the display device according to the exemplary embodiment of the present invention, a portion of the driving semiconductor pattern 230 is exposed by the driving source electrode 240 and the driving drain electrode 250 . However, a display device according to another embodiment of the present invention may include an etch stopper positioned on the driving semiconductor pattern 230 . The etch stopper may prevent damage to the driving semiconductor pattern 230 due to a manufacturing process. For example, in a display device according to another embodiment of the present invention, a portion of the etch stopper may be exposed by the driving source electrode 240 and the driving drain electrode 250 .

The driving drain electrode 250 may include a conductive material. For example, the driving drain electrode 250 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), or tungsten (W). The driving drain electrode 250 may have the same structure as the driving source electrode 240 . For example, the driving drain electrode 250 may have a stacked structure of a low reflection drain electrode layer 251 and a high conductivity drain electrode layer 252 . The low-reflection drain electrode layer 251 may include the same material as the low-reflection source electrode layer 241 . The high conductivity drain electrode layer 252 may include the same material as the high conductivity source electrode layer 242 . For example, the driving drain electrode 250 may have the same reflectance as the driving source electrode 240 .

A planarization layer 120 may be positioned on the driving thin film transistor TR. A level difference caused by the driving thin film transistor TR may be removed by the planarization layer 120 . For example, an upper surface of the planarization layer 120 facing the array substrate 110 may be a flat plane. The planarization layer 120 may include an insulating material. For example, the planarization layer 120 may include an organic insulating material.

Each pixel may further include a pixel electrode 300 electrically connected to the driving thin film transistor TR. For example, the pixel electrode 300 may be electrically connected to the driving drain electrode 250 of the driving thin film transistor TR. The pixel electrode 300 may be positioned close to the array substrate 110 . For example, the pixel electrode 300 may be positioned between the array substrate 110 and the planarization layer 120 . The planarization layer 120 may include at least one contact hole exposing a portion of the driving drain electrode 250 and a portion of the pixel electrode 300 .

The pixel electrode 300 may not overlap the driving gate electrode 210 , the driving semiconductor pattern 230 , the driving source electrode 240 and the driving drain electrode 250 . there is. The pixel electrode 300 may be spaced apart from the driving gate electrode 210 , the driving semiconductor pattern 230 , the driving source electrode 240 and the driving drain electrode 250 . For example, the pixel electrode 300 may be positioned outside the driving gate electrode 210 , the driving semiconductor pattern 230 , the driving source electrode 240 and the driving drain electrode 250 .

A lower surface of the pixel electrode 300 facing the array substrate 110 may be coplanar with a lower surface of the gate electrode 210 facing the array substrate 110 . For example, the pixel electrode 300 may directly contact the array substrate 110 . The driving gate insulating layer 220 may extend between the pixel electrode 300 and the planarization layer 120 . The driving gate insulating layer 220 may include at least one contact hole exposing a partial region of the pixel electrode 300 positioned within the contact hole of the planarization layer 120 .

The pixel electrode 300 may include a conductive material. The pixel electrode 300 may include a transparent material. For example, the pixel electrode 300 may include ITO or IZO. The pixel electrode 300 may include the same material as the transparent gate electrode layer 211 of the driving gate electrode 210 .

A common electrode 400 may be positioned on the planarization layer 120 . The common electrode 400 may form a horizontal electric field with the pixel electrode 300 . For example, a display device according to an embodiment of the present invention is an IPS in which an array substrate 110 on which a driving thin film transistor (TR), a pixel electrode 300, and a common electrode 400 are formed is disposed between a backlight unit and a liquid crystal layer. type of liquid crystal display device. The common electrode 400 may include at least one slit overlapping the pixel electrode 300 .

The common electrode 400 may include a conductive material. The common electrode 400 may include a transparent material. For example, the common electrode 400 may include ITO or IZO.

Common electrodes 400 of pixels adjacent in one direction may be connected to each other. For example, the common electrode 400 may extend in a direction parallel to the gate line GL. The driving thin film transistor TR may be positioned outside the common electrode 400 . For example, the thin film transistor TR of each pixel may not overlap the common electrode 400 .

A pixel connection wire 500 may be positioned on the planarization layer 120 . The pixel connection wire 500 may electrically connect the driving thin film transistor TR and the pixel electrode 300 through a contact hole of the planarization film 120 and a contact hole of the driving gate insulating film 220 . there is.

The pixel connection wire 500 may include a conductive material. The pixel connection wire 500 may include the same material as the common electrode 400 . For example, the pixel connection wire 500 may include ITO or IZO. The pixel connection wire 500 may be insulated from the common electrode 400 . For example, the pixel connection wire 500 may be spaced apart from the common electrode 400 .

The wiring area LA of the array substrate 110 may be positioned outside the pixel area PA of the array substrate 110 . The wiring area LA may be positioned adjacent to the pixel area PA. The pixel area PA may be surrounded by the wiring area LA. For example, the pixel area PA may be defined by the wiring area LA.

A dummy electrode pattern 350 may be positioned in the wiring area LA. The dummy electrode pattern 350 may be positioned on the same layer as the pixel electrode 300 . For example, the dummy electrode pattern 350 may be positioned between the array substrate 110 and the driving gate insulating layer 220 . The dummy electrode pattern 350 may directly contact the array substrate 110 . The dummy electrode pattern 350 may be positioned in parallel with the pixel electrode 300 . Accordingly, in the display device according to the embodiment of the present invention, damage to the pixel electrode 300 due to a difference in density during the forming process can be prevented by the dummy electrode pattern 350 . The dummy electrode pattern 350 may include the same material as the pixel electrode 300 . For example, the dummy electrode pattern 350 may include ITO or IZO.

An intermediate supply line 700 may be positioned in the wiring area LA to transfer a specific voltage or signal to each pixel. For example, the intermediate supply wire 700 may be connected to the common voltage supply wire 600 through the first intermediate connection wire 810 . The common voltage supply wire 600 may be electrically connected to the common voltage supply source 30 . For example, each pixel may receive a common voltage through the intermediate supply line 700 . The common electrode 400 of each pixel may be connected to the intermediate supply wire 700 . For example, the intermediate supply line 700 may extend in a direction parallel to the data line DL.

The intermediate supply wire 700 may be positioned on the driving gate insulating layer 220 . The intermediate supply wire 700 may include an area overlapping the dummy electrode pattern 350 . The intermediate supply line 700 may include a conductive material. The intermediate supply wire 700 may have transmittance lower than that of the dummy electrode pattern 350 . For example, the intermediate supply wire 700 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), or tungsten (W). Accordingly, in the display device according to the embodiment of the present invention, light passing through the dummy electrode pattern 350 may be blocked by the intermediate supply wire 700 . For example, when the display device according to the embodiment of the present invention is a liquid crystal display device, light supplied from a backlight unit may not pass through the wiring area LA of the array substrate 110 . Therefore, in the display device according to the embodiment of the present invention, sharpness can be improved.

The intermediate supply wire 700 may have a lower reflectance than the driving gate electrode 210 of the driving thin film transistor TR. The intermediate supply wire 700 may have a multi-layer structure. The intermediate supply wire 700 may have the same structure as the driving source electrode 240 . For example, the intermediate supply wire 700 may have a stacked structure of a low-reflection intermediate electrode layer 701 and a high-conductivity intermediate electrode layer 702 .

The low-reflection intermediate electrode layer 701 may be positioned between the driving gate insulating layer 220 and the highly conductive intermediate electrode layer 702 . The low-reflection intermediate electrode layer 701 may be positioned on the same layer as the low-reflection source electrode layer 241 . For example, the low-reflection intermediate electrode layer 701 may directly contact the driving gate insulating layer 220 . The low-reflection intermediate electrode layer 701 may include the same material as the low-reflection source electrode layer 241 . The high conductivity intermediate electrode layer 702 may be located on the same layer as the high conductivity source electrode layer 242 . The high conductivity intermediate electrode layer 702 may include the same material as the high conductivity source electrode layer 242 . Accordingly, in the display device according to the embodiment of the present invention, reflection by the intermediate supply wire 700 may be reduced. That is, in the display device according to the embodiment of the present invention, light L2 reflected by the intermediate supply wiring 700 may be less than light L1 supplied to the wiring area LA. For example, when the display device according to the embodiment of the present invention is a liquid crystal display, light supplied from the backlight unit to the wiring area LA is reflected by the intermediate supply wiring 700 and the optical sheet of the backlight unit. Therefore, generation of bright lines at the edges of the pixel area PA may be minimized.

A dummy semiconductor pattern 235 may be positioned between the driving gate insulating layer 220 and the intermediate supply wire 700 . The dummy semiconductor pattern 235 may include a semiconductor material. For example, the dummy semiconductor pattern 235 may include the same material as the driving semiconductor pattern 230 . That is, in the display device according to the embodiment of the present invention, light traveling in the direction of the intermediate supply wiring 700 and light reflected by the intermediate supply wiring 700 may pass through the dummy semiconductor pattern 235 . . Accordingly, in the display device according to the embodiment of the present invention, reflection by the intermediate supply wire 700 can be effectively reduced.

The display device according to the embodiment of the present invention is described as lowering the reflectance of the intermediate supply wire 700 through the physical properties of the low-reflection intermediate electrode layer 701 . However, in a display device according to another embodiment of the present invention, the reflectance of the intermediate supply wire 700 may be reduced through a structural method. For example, in the display device according to another embodiment of the present invention, light reflected from the lower surface of the low-reflection intermediate electrode layer 701 toward the array substrate 110 is transmitted between the low-reflection intermediate electrode layer 701 and the high-conductivity intermediate electrode layer. The thickness of the low-reflection intermediate electrode layer 701 may be adjusted to offset light reflected from the interface between the layers 702 . Accordingly, in the display device according to another embodiment of the present invention, the degree of freedom regarding the material of the intermediate supply wire 700 can be improved. In addition, in the display device according to another embodiment of the present invention, the thickness ratio of the low reflection source electrode layer 241 and the high conductivity source electrode layer 242 and the thickness ratio of the low reflection drain electrode layer 251 and the high conductivity drain electrode layer 252 The thickness ratio of the low-reflection intermediate electrode layer 701 and the high-conductivity intermediate electrode layer 702 may be the same. Accordingly, the display device according to another embodiment of the present invention may optimize the characteristics of the driving source electrode 240 and the driving drain electrode 250 and reduce the reflectance of the intermediate supply wire 700 .

The common voltage supply wire 600 may include a conductive material. The common voltage supply wire 600 may have the same structure as the driving gate electrode 210 . For example, the common voltage supply wire 600 may have a stacked structure of a transparent supply electrode layer 601 and a highly conductive supply electrode layer 602 . The transparent supply electrode layer 601 may be positioned on the same layer as the transparent gate electrode layer 211 . For example, the transparent supply electrode layer 601 may include the same material as the transparent gate electrode layer 211 . The highly conductive supply electrode layer 602 may be located on the same layer as the highly conductive gate electrode layer 212 . For example, the highly conductive supply electrode layer 602 may include the same material as the highly conductive gate electrode layer 212 .

The intermediate supply wire 700 may be positioned closer to the pixel area PA than the common voltage supply wire 600 . For example, the common voltage supply wire 600 may be positioned outside the intermediate supply wire 700 . Accordingly, the display device according to the embodiment of the present invention can minimize the effect of the reflectance of the common voltage supply line 600 on the quality of implemented images. Therefore, in the display device according to the embodiment of the present invention, the degree of freedom regarding the structure and/or material of the common voltage supply line 600 can be improved.

The planarization layer 120 may extend on the common voltage supply wire 600 and the intermediate supply wire 700 . For example, the first intermediate connection wire 810 may be positioned on the planarization layer 120 . The planarization layer 120 may include at least one contact hole exposing a partial region of the common voltage supply wire 600 and at least one contact hole exposing a partial region of the intermediate supply wire 700. . The driving gate insulating layer 220 may include a contact hole exposing a partial region of the common voltage supply wire 600 positioned within the contact hole of the planarization layer 120 . The first intermediate connection wire 810 is between the common voltage supply wire 600 and the intermediate supply wire 700 through contact holes of the planarization film 120 and contact holes of the driving gate insulating film 120. can be electrically connected.

The first intermediate connection wire 810 may include a conductive material. The first intermediate connection wire 810 may include the same material as the common electrode 400 . For example, the first intermediate connection wire 810 may include ITO or IZO. The first intermediate connection wire 810 may be spaced apart from the common electrode 400 .

As a result, in the display device according to the embodiment of the present invention, the intermediate supply wiring 700 located in the wiring area LA adjacent to the pixel area PA and supplying a specific voltage or signal to each pixel has a relatively low reflectance. Accordingly, deterioration in quality of an image realized by the intermediate supply wire 700 can be minimized.

In the display device according to the exemplary embodiment of the present invention, it is described that the common voltage supply line 600 has the same structure as the driving gate electrode 210 of the thin film transistor TR. However, in a display device according to another embodiment of the present invention, the common voltage supply wire 600 may have the same structure as the intermediate supply wire 700 . For example, in a display device according to another embodiment of the present invention, the common voltage supply line 600 may have the same reflectance as the driving source electrode 240 of the thin film transistor TR. In a display device according to another embodiment of the present invention, the intermediate supply wire 700 may directly contact the common voltage supply wire 600 . Accordingly, reflection of the wiring area LA may be effectively reduced in the display device according to another embodiment of the present invention.

The display device according to the embodiment of the present invention may further include a common voltage transmission line 900 and a second connection line 820 located in the wiring area LA. The common voltage transfer wire 900 may supply a common voltage to the data driver 10 and/or the gate driver 20 . The second connection wire 820 may connect the common voltage transfer wire 900 to the common voltage supply wire 600 . The common voltage transfer wire 900 may be positioned in parallel with the intermediate supply wire 700 . For example, the common voltage transfer wire 900 may be positioned between the gate driver 20 and the intermediate supply wire 700 . The common voltage transfer wire 900 may have the same structure as the intermediate supply wire 700 . For example, the reflectance of the common voltage transfer wire 900 may be the same as that of the intermediate supply wire 700 . Accordingly, in the display device according to the embodiment of the present invention, the quality of implemented images can be effectively improved.

In the display device according to the exemplary embodiment of the present invention, the dummy semiconductor pattern 235 is positioned between the driving gate insulating layer 220 and the intermediate supply wire 700 . However, as shown in FIG. 4 , a display device according to another embodiment of the present invention may include an intermediate supply wire 700 directly contacting the driving gate insulating layer 220 . Accordingly, in the display device according to another embodiment of the present invention, the degree of freedom in the forming material and forming process of the driving semiconductor pattern 230 may be improved. Therefore, in the display device according to another embodiment of the present invention, process efficiency is improved, and quality degradation of implemented images due to light reflected from the wiring area can be effectively prevented.

In the display device according to the embodiment of the present invention, it is described that the intermediate supply wire 700 has the same structure as the driving source electrode 240 . However, a display device according to another embodiment of the present invention may include an intermediate supply wire having a single layer structure. For example, as shown in FIG. 5 , in a display device according to another embodiment of the present invention, a low-reflection supply electrode layer 701 positioned between the dummy semiconductor pattern 235 and the planarization film 120 is provided for each pixel. It may directly contact the common electrode 400 and the first intermediate connection wire 810 . Accordingly, in the display device according to another embodiment of the present invention, reflection in the wiring area can be effectively minimized.

6 to 11 are diagrams sequentially illustrating a method of forming a display device according to an embodiment of the present invention.

A method of forming a display device according to an embodiment of the present invention will be described with reference to FIGS. 3 and 6 to 11 . First, as shown in FIG. 6 , a method of forming a display device according to an embodiment of the present invention includes forming a transparent conductive material layer 211a on an array substrate 110, the transparent conductive material layer 211a The method may include forming a highly conductive gate material layer 212a on the high conductive gate material layer 212a and forming a first mask pattern MP on the highly conductive gate material layer 212a.

The transparent conductive material layer 211a may be formed of a conductive material. The transparent conductive material layer 211a may be formed of a transparent material. For example, forming the transparent conductive material layer 211a may include forming a layer made of ITO or IZO on the array substrate 110 .

The highly conductive gate material layer 212a may be formed of a conductive material. The highly conductive gate material layer 212a may be formed of a material having higher conductivity than the transparent conductive material layer 211a. For example, the forming of the highly conductive gate material layer 212a may include aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten ( W) may include forming a layer made of a metal.

The first mask pattern MP may cover an area where the driving gate electrode, the pixel electrode, the data line, the dummy electrode pattern, and the common voltage supply line are formed through a subsequent process. The first mask pattern MP may include a first mask area MP1 and a second mask area MP2 having a thickness smaller than that of the first mask area MP1. For example, a region where a driving gate electrode, a data line, and a common voltage supply wire are formed by a subsequent process may be covered by the first mask region MP1. A region where a dummy electrode pattern and a pixel electrode are formed by a subsequent process may be covered by the second mask region MP2 . For example, forming the first mask pattern MP may include forming a mask material layer on the highly conductive gate material layer 212a and patterning the mask material layer using a halftone mask. can include

As shown in FIGS. 7 and 8 , the method of forming a display device according to an embodiment of the present invention includes a driving gate electrode 210, a data line DL, a pixel electrode 300, A step of forming the dummy electrode pattern 350 and the common voltage supply wire 600 may be included.

The driving gate electrode 210, the data line DL, and the common voltage supply wire 600 may have a double-layer structure. For example, the driving gate electrode 210 has a stacked structure of a transparent gate electrode layer 211 and a high-conductivity gate electrode layer 212, and the data line DL has a stacked structure of a transparent data electrode layer and a high-conductivity data electrode layer. , The common voltage supply wire 600 may have a laminated structure of a transparent supply electrode layer 601 and a highly conductive supply electrode layer 602 . The pixel electrode 300 and the dummy electrode pattern 350 may have a single layer structure. For example, the pixel electrode 300 and the dummy electrode pattern 350 may be a single layer including the same material as the transparent conductive material layer 211a.

The forming of the driving gate electrode 210, the data line DL, the pixel electrode 300, the dummy electrode pattern 350, and the common voltage supply wire 600 is performed without additional formation of a mask pattern. It can be. For example, the forming of the driving gate electrode 210, the data line DL, the pixel electrode 300, the dummy electrode pattern 350, and the common voltage supply wire 600 is shown in FIG. 7. As shown, the step of etching the transparent conductive material layer 211a and the highly conductive gate material layer 212a using the first mask pattern MP, the ashing process of the first mask pattern MP Forming a second mask pattern MP3 from which the second mask region MP2 is removed through an ashing process and a gate exposed by the second mask pattern MP3 as shown in FIG. 8 . A step of removing the material pattern 212p may be included.

As shown in FIG. 9 , the method of forming a display device according to an embodiment of the present invention includes the driving gate electrode 210, the data line DL, the pixel electrode 300, and the dummy electrode pattern 350. and forming a driving gate insulating layer 220 on the array substrate 110 on which the common voltage supply wire 600 is formed.

The driving gate insulating layer 220 may be formed of an insulating material. For example, the driving gate insulating layer 220 may be formed of silicon oxide and/or silicon nitride. The driving gate insulating layer 220 may be formed of a high-K material such as hafnium oxide (HfO) and titanium oxide (TiO).

As shown in FIG. 10 , in a method of forming a display device according to an embodiment of the present invention, a driving thin film transistor TR, a dummy semiconductor pattern 235 and a driving gate insulating film 220 are formed on an array substrate 100 . A step of forming the intermediate supply wiring 700 may be included.

The forming of the driving thin film transistor TR may include forming the driving semiconductor pattern 230 on the driving gate insulating layer 220 and the driving source electrode 240 and the driving drain connected to the driving semiconductor pattern 230 . A step of forming the electrode 250 may be included.

Forming the driving semiconductor pattern 230 may include forming a semiconductor material layer on the driving gate insulating layer 220 and patterning the semiconductor material layer. The semiconductor material layer may be formed of a semiconductor material. For example, the semiconductor material layer may be formed of silicon oxide and/or silicon nitride. The semiconductor material layer may be formed of a semiconductor oxide such as IGZO.

The driving source electrode 240 and the driving drain electrode 250 may have a double layer structure. For example, the driving source electrode 240 has a stacked structure of a low-reflection source electrode layer 241 and a high-conductivity source electrode layer 242, and the driving drain electrode 250 has a low-reflection drain electrode layer 251 and a high-conductivity source electrode layer 242. It may be a stacked structure of the drain electrode layer 252 . The driving drain electrode 250 may be formed simultaneously with the driving source electrode 240 . For example, forming the driving source electrode 240 and the driving drain electrode 250 may include forming a low-reflection material layer on the array substrate 110 on which the driving semiconductor pattern 230 is formed; The method may include forming a high conductivity material layer on the low reflection material layer and sequentially patterning the low reflection material layer and the high conductivity material layer.

The low-reflection material layer and the high-conductivity material layer may be formed of a conductive material. For example, the low-reflection material layer and the high-conductivity material layer are formed of metals such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). It can be. The low-reflection material layer may be formed of a material having a lower reflectance than the high-conductivity material layer. The high-conductivity material layer may be formed of a material having higher conductivity than the low-reflection material layer.

The dummy semiconductor pattern 235 may be formed of the same material as the driving semiconductor pattern 230 . For example, forming the dummy semiconductor pattern 235 may be performed simultaneously with forming the driving semiconductor pattern 230 .

The dummy semiconductor pattern 235 may be formed to overlap the dummy electrode pattern 350 . That is, in the method of forming a display device according to an embodiment of the present invention, the dummy semiconductor pattern 235 may be formed in an area where light passing through the dummy electrode pattern 350 may be incident.

The intermediate supply wire 700 may have the same structure as the driving source electrode 240 . For example, the intermediate supply wire 700 may have a stacked structure of a low-reflection intermediate electrode layer 701 and a high-conductivity intermediate electrode layer 702 . The intermediate supply wire 700 may be formed simultaneously with the intermediate source electrode 240 .

The intermediate supply wiring 700 may be formed on an upper surface of the dummy semiconductor pattern 235 facing the array substrate 110 . For example, the intermediate supply wire 700 may be formed to overlap the dummy electrode pattern 350 . That is, in the method of forming a display device according to an embodiment of the present invention, the intermediate supply wiring 700 is formed in a region capable of blocking light passing through the dummy electrode pattern 350 and the dummy semiconductor pattern 235. can

As shown in FIG. 11 , in the method of forming a display device according to an embodiment of the present invention, the array substrate ( 110), forming a planarization film 120 on a portion of the driving drain electrode 250, a portion of the pixel electrode 300, a portion of the common voltage supply wire 600, and the intermediate supply Exposing a partial area of the wire 700 may be included.

Forming the planarization film 120 is a step of applying an insulating material on the array substrate 110 on which the driving source electrode 240, the driving drain electrode 250, and the intermediate supply line 700 are formed. can include For example, the planarization layer 120 may be formed of an organic insulating material. A step of the array substrate 110 on which the driving source electrode 240 , the driving drain electrode 250 , and the intermediate supply wire 700 are formed may be removed by the process of forming the planarization layer 120 .

Exposing a partial area of the driving drain electrode 250, a partial area of the pixel electrode 300, a partial area of the common voltage supply wire 600, and a partial area of the intermediate supply wire 700 is the planarization step. Forming contact holes in the layer 120 and forming contact holes in the driving gate insulating layer 220 may be included.

Contact holes formed in the driving gate insulating layer 220 may be positioned within contact holes formed in the planarization layer 120 . For example, forming the contact holes in the planarization layer 120 may include removing the planarization layer 120 formed on a region of the driving gate insulating layer 220 exposed by the contact hole. there is.

As shown in FIG. 3 , in the method of forming a display device according to an embodiment of the present invention, a common electrode 400, a pixel connection wire 500 and a first intermediate connection wire 810 are formed on the planarization film 120. It may include the step of forming.

The common electrode 400 may be formed to have at least one slit overlapping the pixel electrode 300 . The pixel connection wire 500 may be formed to electrically connect the driving drain electrode 250 and the pixel electrode 300 to each other. The first intermediate connection wire may be formed to connect the intermediate supply wire 700 to the common voltage supply wire 600 .

The common electrode 400 , the pixel connection wire 500 and the first intermediate connection wire 810 may be formed at the same time. For example, in the step of forming the common electrode 400, the pixel connection wire 500, and the first intermediate connection wire 810, a transparent conductive layer is formed on the planarization layer 120 in which contact holes are formed. and patterning the transparent conductive layer. The transparent conductive layer may be formed of a transparent conductive material. For example, the transparent conductive layer may be formed of ITO or IZO.

As a result, in the method of forming a display device according to an embodiment of the present invention, the dummy electrode pattern 350 and the intermediate supply wiring 700 overlapping each other have relatively low reflectivity to prevent damage to the pixel electrode 300 due to a difference in density. By forming at the same time as the driving source electrode 240 having , reflection by the intermediate supply wire 700 can be reduced without an additional process. Accordingly, in the method of forming a display device according to an embodiment of the present invention, the quality of implemented images can be effectively improved without reducing process efficiency.

110: array substrate TR: driving thin film transistor
210: driving gate electrode 230: driving semiconductor pattern
235: dummy semiconductor pattern 240: driving source electrode
250: driving drain electrode 300: pixel electrode
350: dummy electrode pattern 400: common electrode
500: pixel connection electrode 600: common voltage supply wiring
700: intermediate supply wiring 701: low-reflection intermediate electrode layer
810: Intermediate connection wiring

Claims (20)

an array substrate including a pixel area and a wiring area positioned adjacent to the pixel area;
pixels positioned on the pixel region of the array substrate and including a thin film transistor and a pixel electrode electrically connected to the thin film transistor;
an intermediate supply wiring located on the wiring area of the array substrate and transmitting a specific voltage or signal to each pixel; and
A dummy electrode pattern positioned on the wiring region of the array substrate and positioned on the same layer as the pixel electrode,
The intermediate supply wiring has a higher conductivity than the dummy electrode pattern and a lower reflectance than the gate electrode of the thin film transistor;
The intermediate supply wiring includes a low-reflection intermediate electrode layer and a high-conductivity intermediate electrode layer stacked on the low-reflection intermediate electrode layer;
The low reflection intermediate electrode layer has a lower reflectance than the high conductivity intermediate electrode layer. According to claim 1,
The intermediate supply wire includes a region overlapping the dummy electrode pattern. According to claim 1,
A lower surface of the pixel electrode facing the array substrate is coplanar with a lower surface of the gate electrode facing the array substrate. According to claim 3,
The display device of claim 1 , wherein the gate electrode has a laminated structure of a transparent gate electrode layer including the same material as the pixel electrode and a highly conductive gate electrode layer having higher conductivity than the transparent gate electrode layer. According to claim 3,
The source electrode of the thin film transistor has a lower reflectance than the gate electrode,
The intermediate supply wiring has the same structure as the source electrode of the thin film transistor. According to claim 5,
The source electrode has a laminated structure of a low reflection source electrode layer and a high conductivity source electrode layer,
The reflectance of the low reflection source electrode layer is lower than the reflectance of the high conductivity source electrode layer. According to claim 1,
Each pixel further includes a common electrode including at least one slit overlapping the corresponding pixel electrode,
The common electrode is connected to the intermediate supply wire. According to claim 7,
Each pixel further includes a planarization film positioned between the pixel electrode and the common electrode,
The display device of claim 1, wherein the gate insulating film of the thin film transistor extends between the corresponding pixel electrode and the planarization film. According to claim 7,
Each pixel further includes a pixel connection wire connecting the thin film transistor and the pixel electrode,
The pixel connection wire includes the same material as the common electrode. According to claim 9,
a common voltage supply wiring positioned on the wiring area of the array substrate; and
Further comprising an intermediate connection wire connecting the intermediate supply wire to the common voltage supply wire,
The common voltage supply wire has the same structure as the gate electrode of the thin film transistor. According to claim 1,
The display device further comprises a dummy semiconductor pattern positioned between the dummy electrode pattern and the intermediate supply wire. According to claim 11,
The dummy semiconductor pattern includes the same material as the semiconductor pattern of the thin film transistor. providing an array substrate including a pixel area and a wiring area adjacent to the pixel area;
forming a gate electrode and a pixel electrode on the pixel region of the array substrate, and forming a dummy electrode pattern on the wiring region of the array substrate;
forming a gate insulating layer on the array substrate to cover the gate electrode, the pixel electrode, and the dummy electrode pattern;
forming a driving thin film transistor including the gate electrode and the gate insulating layer on the pixel region of the array substrate;
forming an intermediate supply wiring overlapping the dummy electrode pattern on the wiring area of the array substrate;
forming a planarization film on the array substrate to cover the driving thin film transistor and the intermediate supply line; and
Forming a pixel connection wire connecting the driving thin film transistor and the pixel electrode on the planarization film,
The intermediate supply wiring is formed to have a lower reflectance than the gate electrode of the driving thin film transistor,
The intermediate supply wiring includes a low-reflection intermediate electrode layer and a high-conductivity intermediate electrode layer stacked on the low-reflection intermediate electrode layer;
The method of manufacturing a display device wherein the low reflection intermediate electrode layer has a lower reflectance than the high conductivity intermediate electrode layer. According to claim 13,
The dummy electrode pattern is formed on the same layer as the pixel electrode. According to claim 13,
Forming the gate electrode, the pixel electrode, and the dummy electrode pattern may include:
forming a transparent conductive material layer on the array substrate;
forming a highly conductive gate material layer on the transparent conductive material layer;
forming a first mask pattern including a first mask area and a second mask area thinner than the first mask area on the highly conductive gate material layer;
The transparent conductive material layer and the highly conductive gate material layer are sequentially etched by the first mask pattern to be positioned on the gate electrode, the pixel electrode, the dummy electrode pattern, and the pixel electrode and the dummy electrode pattern. forming a gate material pattern;
ashing the first mask pattern to form a second mask pattern from which the second mask area is removed;
removing the gate material pattern using the second mask pattern;
The first mask area corresponds to the gate electrode, and the second mask area corresponds to the pixel electrode and the dummy electrode pattern. According to claim 13,
Forming the driving thin film transistor.
forming a semiconductor pattern overlapping the gate electrode on the gate insulating layer;
forming a source electrode connected to a source region of the semiconductor pattern on the gate insulating layer; and
Forming a drain electrode connected to a drain region of the semiconductor pattern on the gate insulating film,
The intermediate supply wire is formed at the same time as the source electrode manufacturing method of the display device. 17. The method of claim 16,
Further comprising forming a dummy semiconductor pattern between the dummy electrode pattern and the intermediate supply wiring,
The method of manufacturing a display device in which the dummy semiconductor pattern is formed simultaneously with the semiconductor pattern. 17. The method of claim 16,
Forming the source electrode and the intermediate supply wiring,
forming a low-reflection intermediate electrode layer on the array substrate on which the semiconductor pattern is formed;
forming a high conductivity intermediate electrode layer on the low reflection intermediate electrode layer; and
and sequentially patterning the low-reflection intermediate electrode layer and the high-conductivity intermediate electrode layer. According to claim 18,
The low reflection intermediate electrode layer is a method of manufacturing a display device formed of a material having a lower reflectance than the high conductivity intermediate electrode layer. According to claim 13,
forming a common voltage supply wire on the wiring area of the array substrate; and
Forming an intermediate connection wire connecting the intermediate supply wire to the common voltage supply wire on the planarization film;
The common voltage supply wire is formed simultaneously with the gate electrode,
The intermediate connection wire is formed at the same time as the pixel connection wire.

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