TWI338939B - Package module and electronic device - Google Patents
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- TWI338939B TWI338939B TW096130128A TW96130128A TWI338939B TW I338939 B TWI338939 B TW I338939B TW 096130128 A TW096130128 A TW 096130128A TW 96130128 A TW96130128 A TW 96130128A TW I338939 B TWI338939 B TW I338939B
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- H—ELECTRICITY
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- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
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- H—ELECTRICITY
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06589—Thermal management, e.g. cooling
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Description
1338939 九、發明說明: 【發明所屬之技術領域】 本發明有關於一種電子封裝技術,特別是有關於一種 具有可撓式散熱片(heat spreader )的封裝模組,以降低所 產生的熱應力並增加裝置的散熱(heat dissipation )效果。 【先前技術】 可攜式電子產品,例如手機、行動電腦及其他消費性 _ 產品需要在厚度薄、重量輕及低成本的限制因素下呈現高 效能及功能,因而驅使製造業者必須增加半導體晶片的集 積度。亦即,製造業者開始轉向三維(3D)封裝,藉由打 線(wire bonding )法或覆晶(flip chip )法等組裝技術而 將多重晶片疊置於一封裝中。 因此,多重封裝模組(multi-package module, MPM) 近來越來越受到矚目,其可在一基板上整合不同功能的晶 • 片,例如微處理器或記憶體、邏輯及光學積體電路等,取 代了將個別的晶片放置於較大尺寸的印刷電路板(printed circuit board, PCB )上的方式。然而,相較於個別的單晶封 裝而言,多重封裝模組具有較高的功率密度,而使得熱管 理變的更為重要且成為其成功發展之關鍵因素。 傳統上解決熱產生的方法係包含於裝置操作期間,提 供一散熱裝置(即,散熱片)與1C封裝模組中的1C晶片 作熱接觸。第1圖係繪示出傳統具有多重封裝模組100之
Client's Docket N〇.:V1T07-0053/2007-08-13 TT’s Docket No:0608-A41248-TW/fmal/王琮郁/ 5 1338939 電子裝置剖面示意圖。此電子裝置包括一多重封裝模組 100,其組裝於一印刷電路板(PCB) 101上,且其包括一 基板12。基板12之上表面及下表面各組裝有不同功能之 晶2 16及Μ而構成多重封裝模組2〇。基板12下表面具 有複數錫球1G’其對應連接至印刷電路板K)1上的谭塾u (bcmdmgpad),使晶片16及14與印刷電路板ι〇ι作電 性連接。在多重封|模組中,晶片16所產生的熱可藉由一 散熱裝置將其排出。舉例而言,—散熱片2〇 #由黏著層 17而與晶片16上表面接觸。再者’晶片16周圍的基板12 上’設置有加固環(stiffener) 18,其藉由黏著層Η及P 固疋散熱片2G與基板η並作為散熱片2G的支標。 在上述的電子裝置中,由於晶片14與印刷電路板1〇1 之間的間隙狹小的關係’使得晶4 14所產生的埶難 出。因此’在設計上,基板12下表面僅能放置低轉的晶 片而使電路❸博性降低。再者,由於典型的散熱片加及 加固環15由剛性材料所構成,因此容易在熱製程中產生敎 應力,造成散熱片2G的剝離(de]ammati()n)或是晶片& 的龜裂,使裝置的可靠度降低。另外,不同的多重封裝模 組尺寸具衫同尺相加固環15,_增加了製造成本。、 甘因此’有必要尋求-種可具有高效率散熱片的封裝模 組’/、可改善習知封裝模組的缺點。 【發明内容】 6 1-338939 • 有鑑於此,本發明提供一種封裝模組及電子裝置,其 藉由改變散熱片的材料及組裝方式,以有效降低熱應力及 降低製造成本。 根據上述之目的,本發明提供一種封裝模組,其包括: 一基板、一晶片、及一可撓式散熱片。基板具有一表面, 且此表面具有·一晶片區。晶片設置於基板表面的晶片區。 可撓式散熱片順應性覆蓋基板的部分表面及晶片。 又根據上述之目的,本發明提供一種電子裝置,其包 • 括:一封裝模組及一電路板,其中封裝模組包括:一基板、 複數錫球、一晶片、及一可撓式散熱片。基板具有一第一 表面及一第二表面,其中第一表面具有一晶片區。錫球依 陣列排置於基板的第二表面。晶片設置於基板的第一表面 的晶片區。可撓式散熱片順應性覆蓋基板的部分第一表面 ' 及晶片。電路板具有複數焊墊對應接合至錫球。 【實施方式】 以下配合第2圖說明本發明實施例之具有封裝模組之 • 電子裝置。在第2圖中,電子裝置包括:一封裝模組200 及一電路板301,例如一印刷電路板。封裝模組200包括: 一基板100 (如,封裝基板或1C載板)、複數錫球112、 晶片102及104、以及可撓式散熱片106及110。在本實施 例中,基板100可為塑膠基板、陶瓷基板、無機基板或是 有機基板。再者,基板100具有一第一表面及一第二表面。 在本實施例中,第一表面可以是上表面100a及第二表面可 以是下表面l〇〇b。此處,下表面100b係指面向電路板301
Client's Docket N〇.:VIT07-0053/2007-08-13 TT’s Docket N〇:0608-A41248-TW/final/王琮郁/ ⑷ 8939 ίίΓ㉝而上表面驗係指背向於下表面祕之表面。
3及4圖’其分麟示出封裝模組的上視及 面示意圖。在第3圖中,基板刚的上表面】_具 。曰曰片區l〇la。而基板i⑻的下表面】嶋則具有一晶 •品b以及至少一熱通道區1〇1。,如第4圖所示。典 型的晶片區1〇13或1()lb大體位於基板刚的中心部。而' 不同於傳統_裝魏,紐⑽的下表面難具有熱通 道區1〇lc且其自晶片㊣101b向外延伸至基板100的一邊 彖或角落。舉例而言,熱通道區101c自矩形晶片區⑼b 的兩相對邊緣向外延伸至基板100的兩相對邊緣,如第4 圖所不。在其他實施例巾,熱料區脈自矩形晶片區 lb的四個角落向外延伸至基板100的四個角落,如第5 圖所示。熟習此技藝之人士可輕易了解基板可具有一或多 個熱通道區自晶片區沿不同方向延伸至基板邊緣或角落而 不侷限於第4及5圖之型態。 請參照第2、3、4及5圖,具有不同功能的晶片1〇2 及1〇4可藉由相同或不同的封裝方法而分別組裝於基板 1〇〇上表面l〇〇a的晶片區1〇la以及下表面1〇〇b的晶片區 l〇lb中。舉例而言,晶片1〇2及1〇4可藉由覆晶法或打線 法組裝於基板100。 複數錫球(solder ball) 112 ’係依陣列排置於基板1〇〇 的下表面100b的晶片區i〇ib及熱通道區i〇ic外的區域, 用以將來自晶片102及1 〇4之信號傳輸至外部電路,其中
Client's Docket N〇.:VIT07-0053/2007-08-13 TT’s Docket N〇:0608-A41248-TW/fmal/王琮郁/ 8 錫求/12之間的間距小於熱通道區101c之寬度。 ^撓式散熱片】〇6及n〇分別設置於基板⑽的上表 力固二A下表面祕上。而不同於傳統剛性的散熱片以 的口U ^支禮,可撓式散熱片W係順應性覆蓋基板_ 接二表面_及晶片區咖上的日日日片K)2,而另一可 二政’、’、片】10則順應性覆蓋基板_的下表面100b的埶 =區㈣及晶片區腿上的晶片刚而不與錫球⑴ 在本實施财’可撓式散熱片⑽可以是順應性覆 瓜基板m的整個或部份的上表面施及晶片區⑼&上 的晶片1〇2。再者,可撓式散熱片106及m可自基板⑽ 2少-邊緣向外延伸且彼此接合。舉例而言,可挽式散 '、,、片】〇6及m自基板100的兩相對邊緣向外延伸 接合。 在本實施例中,可撓式散熱片1〇6及ιι〇可分別包括: 一可撓式導熱層105及位於其下方的—黏著層⑼,如第6 圖所不。可撓式導熱層105可由碳管勝片(⑽_ _ _preg)或是厚度小於30μπι的金屬所構成,而金屬例如 是銅。當使用銅金屬作為可撓式導熱層⑽時,可在背向 黏著層1G3的可援式導熱層1G5的表面額外形成一保護層 105a’例如鎳金屬或陽極氧化材料。亦即,保護層心經 由可撓式導熱層H)5隔開黏著層⑽。而位於可撓式導熱 層1〇5與基板H)〇之間的黏著層1()3,例如㈣樹脂(B_stage _)、聚亞賴(pGlyimide,pi)、或其他習用的黏著材
Client's Docket N〇.:VIT07-0053/2007-08-13 TT’s Docket No:0608-A41248-TW/fmal/王综郁/ L338939 • 料,係用以將可撓式導熱層105貼附於基板100及晶片102 ' 及104上。特別是,具有可撓特性之B階樹脂,更能夠使 位於上方的可撓式導熱層順應性覆蓋於基板100上。另 外,可撓式導熱層105具有大體平坦的表面,使黏著層103 隔開晶片102及104與可撓式導熱層105。然而,在其它 實施例中,可撓式導熱層105的表面可具有複數凸面圖案 105b而形成一粗糙表面,如第7圖所示。當可撓式散熱片 B 106及110受力壓合而覆蓋於基板100上時,凸面圖案105b 會穿過黏著層103,以便於分別與晶片102及104直接接 觸而進一步提昇散熱效果。 電路板301具有複數焊墊(bonding pad) 302,其對應 接合至錫球112,以電性連接電路板301與晶片102及 104。典型的電路板包括至少一或多個金屬層以及至少一或 多個絕緣層,其中金屬層可作為信號層、電源層、及/或接 地層。此處,為簡化圖式,僅繪示出一平整基板301。另 • 外,電路板30上可具有散熱裝置(未繪示),而可撓式散 熱片106或110的一端可進一步接合至電路板301上的散 熱裝置,以增加電子裝置的散熱效果。為了簡化圖式,此 處僅以可撓式散熱片106的一端接合至電路板301上作為 範例說明。 另外,在上述實施例中,封裝模組200為具有晶片102 及 104 的多重封裝模組(multi-package module,MPM )。 而在其它實施例中,可在封裝模組200的基板100與可撓
Client's Docket N〇.:VIT07-0053/2007-08-13 TT,s Docket No:0608-A41248-TW/final/王琮郁/ 10 1338939
式放熱片106之間設置-封裝農置心封裝裝置115經 由稷數凸塊(b_P)接合至基板⑽,⑽成封裝 (package on package,P〇p )模組,如第 8 圖所示。、 另外’雖然上述f施例細具有W 1()2 &⑽及 應的可撓式散熱片106及110的多重封裝模組作為範例說 明’然而所屬技術領域中具有通常知識者可輕易的瞭解 裝模組亦可僅具有單一的晶片102及單-的可撓式散 熱片_未繪示)。在這種情形之下,同樣可在封裝模: 細的基1〇〇與可撓式散熱4 1G6之間設置封裝裝置 115 ’而構成-4 層㈣(package ⑽ package, ρ〇ρ)模植, 如第9圖所示。 根據上述實施例,由於位於基板下表面娜的晶 “片104所產生的熱可藉由散熱片11()而排出,因此在電路 設計上,晶片104可為-高功率晶片,例如:中央處理哭 晶片。亦即’在電路設計上可具有較大的彈性^者,由 於可撓式散熱β a no可降低熱製程中所產生敎應 力,因此可避免散熱片106及110的剝離或是晶片ι〇6及 no的龜裂,使電子裝置的可靠度增加。另外,由於可撓 式散熱片】G6 A 11G不需額外使用加固環來固定及支禮散 熱片106及110,因此可降低製造成本。 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明’任何所屬技術領域中具有通常知識者,在不 脫離本發明之精神和範_,當可作更動與潤飾,因此本
Client's Docket No.:VIT07-0053/2007-08-13 ^’s Docket No:0608-A41248-TW/final/王琮郁/ 1338939 發明之保護範圍當視德 寸之^月專利範圍所界定者為準。 【圖式簡單說明】 面示=圖騎示㈣統具有多重封裝模組之電子裝置剖 電根據本發明實施例之具有封㈣組之 面示2圖係㈣出根據本發明實施例之㈣模組上視平 平面不出根據本發明實施例之封裝模組之底視 第5圖係繪示出根據本發明另一齒 底視平面示意圖。 料㈣,'關之封裝模組之 第6圖係繪示出根據, 面示意圖。 據本心月貝〜例之可撓式散熱片剖 第7圖係繪示出根據本 麻 片剖面示意圖。 月另例之可撓式散熱 第8圖係繪示出根據本 組之電子裝置剖面示意圖3 ^例之具有封裝模 蚊第電出,發明另一實施例之具有封裝模 、.且之電子裝置刮面不意圖。 【主要元件符號說明】 習知 10〜錫球;11〜焊墊;12〜基板;14、
Client’s Docket No.:VIT07-0053/2007-〇8-13 TT’s Docket No:0608-A41248-TW/fmai/王综部 / 16, 曰曰 片;15 12 1338939 17〜黏著層;18〜加固環;20〜散熱片;100〜多重封裝模 組;101印刷電路板。 實施例 100〜基板;l〇〇a〜上表面;100b〜下表面;101a、101b〜 晶片區;101c〜熱通道區;102、104〜晶片;103〜黏著層; 105〜可撓式導熱層;105a〜保護層;105b〜凸面圖案;106、 110〜可撓式散熱片;112〜錫球;114〜封裝裝置;115〜凸塊; 200〜封裝模組;301〜電路板;302〜焊墊。
Client's Docket N〇.:VIT07-0053/2007-08-13 TT’s Docket No:0608-A41248-TW/final/王琮郁/
Claims (1)
1338939 十、申請專利範圍: 1·一種封裝模組,包括: 一晶;t板’具有一第—表面,”該第-表面具有-第 片區=晶片,設置於該基板的該第-表面的該第-晶 一表熱片,順應性覆蓋該基板的部分該第 2·如申請專利範圍第!項所述之封裝模組,其中該基 板更具有:第二表面,相對於該第一表面,其中該第二: 面具有-第二晶片區及自該第二晶片區一邊緣或角落向夕: 延伸至該基板的―邊緣或角落的至少—熱通道區。 3·如申請專利範圍第2項所述之封裝模組,更包括, 片區晶片’設置於該基板的該第二表面的該第二晶 二晶片 第二可撓式散熱片,順應性覆蓋該熱通道區及該第 其中該第-可撓式散熱片及該第二可撓式散熱片自該 基板的至少一邊緣向外延伸且彼此接合。 4.如申請專利|請第3項所叙職亥第 一可撓式散熱片及該第二可撓式散熱片分別包括:〆 一可撓式導熱層;以及 一黏著層,位於該可撓式導熱層與該基板之間。 5.如申請專利範圍第4項所述之封裝模組,其令該可 撓式導熱層包括金屬,且其厚度小於3〇/πώ。 Client’s Docket No.: VIT07-0053/2007-08-13 TT’s Docket No:0608-A41248-TW/final/王稼郁/ 1338939 6.如申請專利範圍第4項所述之 一可撓式散勒τ戒衩、,且,其中該第 =放熱片及,玄苐二可撓式散熱片更分別包括 曰 < 於忒可撓式導熱層上且經由該 …隻 黏著層隔開。 j撓式v熱層而與該 ❹7:二申請專利範圍第6項所述之封裝模組,|中,伴 4層包括鎳金屬或陽極氧化材料。 、中忒保 匕申請專利範圍第4項所述之封裝模組,並中 Γ面具有複數凸面圖案而形—當 二熱片及該第二可挽式散熱片分別受力屋合 板上時,該等凸面圖案穿過該黏著層而分別 〃。亥弟a曰片及該第二晶片直接接觸。 9. 如申請專利範圍第4項所述之封裝模組,其中 挽式導熱層包括碳管膠片。 ° 10. 如申請專利範圍帛4項所述之封裝模組,其十該羝 著層包括B階樹脂或聚亞醯胺。 — 如申請料]範1|第】項所述之封裝模組,更包括— 封裝裝置’設置於該第一可撓式散熱片與該基板之間。 12.—種電子裝置,包括: 一封裝模組,包括: 一基板,具有一第一表面及與該第一表面相對的 -第二表面,其中該第一表面具有一第一晶片區; 複,錫球,依陣列排置於該基板的該第二表面; 一第一晶片,設置於該基板的該第一表面的該第 一晶片區;以及 一第一可撓式散熱片,順應性覆蓋該基板的部分 Chent*s Docket Nq.:VIT07-0053/2007~08-13 TT’s Docket N〇:0608-A41248-丁W/final/王辟郁/ 15 1338939 該第一表面及該第一晶片;以及 —電路板’具有複數焊墊對應接合至該等錫球。 ★ 一 13.如申請專利範圍第12項所述之電子裝置,其中該 第一表面具有一第二晶片區及至少一熱通道區自第二晶片 區邊緣或角落向外延伸至該基板的一邊緣或角落,且爷 等錫球排置於該基板的該第二表面的該第二晶片區及該埶 通道區之外的區域。 ‘ M·如申請專利範圍第13項所述之電子裝 1 封裝模組更包括: ” 一第二晶片,設置於該基板的該第二表面的 曰 片區;以及 ^ X乐一日日 曰I第二可撓式散熱片,順應性覆蓋該熱通道區及該第 Α板^該第I可撓式散熱片及該第二可撓式散熱片自該 基板的至少一邊緣向外延伸且彼此接合。 .如申請專利第14項所述之電子裝置,其中該 4錫球之間的間距小於該熱通道區之寬度。 μ 16.如巾請專利範圍第14項所述之^裝置, 弟一可撓式散熱片及該第二可撓式散熱片分別包括: 一可撓式導熱層;以及 -黏著層,位於該可撓式導熱層與該基板之間。 Π.如申料利第16項所叙電子裝置, 可撓式導熱層包括金屬,且其厚度小於3一。 18^巾料·圍第〗6顧述之電子裝置, 第-可撓式散熱片及該第二可撓式散熱片更分別包 Clients Docket N〇.:VIT07-0053/2007-08-13 TT’s Docket Ν〇·Ό608-Α41248· 丁 W/final/王踪郁/ 16 護層,位於該可撓式導熱層上讀 該黏著層。 j操式導熱層隔開 〗9.如申請專·㈣】8項所述 保護層包括錄金眉或陽極氧化材料。?衣置,其中該 可料利1請第16項料之電子裝置,立Μ 可撓式導熱層的表面具有複數 i ,、忪亥 卷« ㈣而形成_表面, U該第二可撓式㈣0別受力壓 合而覆盍於該基板上蚌,兮楚几二门办_ 彳又刀么 別料第”1 專凸面圖案穿過該黏著層而分 另J,、》玄第一晶片及該第二晶片直接接觸。 21,如申請專利朗第16項所述 可撓式導熱層包括碳管膠片。 ^其中该 黏著層’L申亞 12所述之電子裝置,其中該 _ 23.如申請專利範圍第14項所述之電子裝置,其中該 ^可撓式散熱片或該第二可撓式散熱片之—端係接合至 Λ 該電路板。 设口主 -封12項所述之電子裝置,更包括 置於该弟一可撓式散熱片與該基板之間。 17
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