TWI334183B - Conductive structure for a semiconductor integrated circuit and method for forming the same - Google Patents

Conductive structure for a semiconductor integrated circuit and method for forming the same Download PDF

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Publication number
TWI334183B
TWI334183B TW096105681A TW96105681A TWI334183B TW I334183 B TWI334183 B TW I334183B TW 096105681 A TW096105681 A TW 096105681A TW 96105681 A TW96105681 A TW 96105681A TW I334183 B TWI334183 B TW I334183B
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Taiwan
Prior art keywords
region
layer
dimension
conductive
longitudinal dimension
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TW096105681A
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English (en)
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TW200834766A (en
Inventor
J B Chyi
Cheng Tang Huang
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Chipmos Technologies Inc
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Application filed by Chipmos Technologies Inc filed Critical Chipmos Technologies Inc
Priority to TW096105681A priority Critical patent/TWI334183B/zh
Priority to US11/898,612 priority patent/US8319337B2/en
Publication of TW200834766A publication Critical patent/TW200834766A/zh
Application granted granted Critical
Publication of TWI334183B publication Critical patent/TWI334183B/zh
Priority to US13/568,465 priority patent/US20120309186A1/en

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Description

1334183 九、發明說明： 【發明所屬之技術領域】 本發明係一種半導體結構；特別是一種用於形成平坦化表面 之半導體結構及其成形方法。 【先前技術】
凸塊電鑛於微電子(microelectronics)及微系統(micro systemJ 等領域已發展出許多技術》諸如平面顯不|§ (flat panel displays， FPD)與驅動晶片（driver ICs)的連接、珅化嫁晶片上的傳導線與氣 橋(air bridges)技術、以及LIGA技術中X-ray光罩的製作等，均 於不同階段使用到該凸塊電鑛技術。 以電路板與1C晶片的連接為例’ 1C晶片可利用各種方式與電 路板連接’而其封裝方式主要便是利用凸塊（特別是金凸塊）電 鍍技術，將1C晶片中的襯墊與電路板電性連接。此技術不僅可大 幅縮小1C晶片的體積，亦使其可直接崁入電路板上，具有節省空 間、低感應及散熱能力佳等特性，加上電鑛製程的低成本優勢， 致使凸塊電鍍技術得以蓬勃發展。 /典型的凸塊電鍍製程，例如金凸塊電鍍製程，需要在襯墊上 先行形成一底層金屬(under bump metal)，底層金屬除作為接合凸 塊與襯墊之黏著層外，亦通常與一導電層電性連結，其中該導電 層實質上可與底層金屬可分別或㈣形成、亦可棚相同製程與 材料形成，以於電鍍形成凸塊後，共同作為導電媒介之用，使^ =以順獅成於底層金屬上方，並透過底層金屬與襯塾進行 ΪΪΙ,ΙΞ此在電鍍開始之前，需先在晶片表面，除了襯塾以外 =他，方’形成複數導電層（或傳導底層金屬），在凸塊電 成後’再利用餘刻方式，將該些導電層（或傳導底層金屬）去除。 凸塊於電鍵程序完結後，需呈現具有較襯墊與底層金屬更大 5 133.4183 =橫，尺寸，以在凸塊與電路板接合時，在凸塊底部得以形成足 夠的子撐，避免因製程產生之擠壓而破裂或變形。因此，如第i ，所不，底層金屬12形成於襯墊13與保護層14間所定義之開口 區域上方時，會自然呈現二相對之轉折區域12a。當一凸塊10自 底層金f 12上方等向累積形成（例如藉由電鍍累積成形）時，自 函蓋底層金屬12的轉折區域12a。，故凸塊1()頂部會因底層 金，12之底面不平整，而對應呈現不平整的頂部表面^，其中所 突角101與102，即代表因前述不平整而導致表面11之外 觸面!與102 ’於凸塊1〇與電路板接合時，易造成接 If ί不良，影響導電性。因此通常需要藉由額外 亦難控制。研磨）消除突角，程序相當不便’且後製程序之品質 值蓮’由於晶片表面可能會具有部分_表面，因此當 ΐ ^因糙表面時，容易因此產生斷點，而無法導 知技術均以形解均厚度較厚之底層金屬，以 金屬以效I阻失。但厚度增加的底層 率降低，而需要進行後二使凸塊電鍍的良 述問ί鑑於上述缺失，本發抑提供如下之技術突破，以解決上 【發明内容】 6 1334183 本發明之一目的在於提供一種用於一半導體積體電路 j，該半ΐ體積體電路包含一襯塾以及一保護層，局部覆ίί 莫界定出具有-第—橫向尺寸之―第—開口區域，使得^ J電結構適可透過該第—開口區域，與該襯墊呈電性連接吏= =構包含-支撐層，具有-第二開口_，以在其中二 整頂面之導體，作為凸塊。 戍千 本發明之另一目的，在於提供一種用於一半導體積體 ▲導電結構’該半導體積體電路包含一襯墊以及一保護|體:U ，無斷點之形成，並使半導體積體電路具有穩定阻抗之i 為達上述目的，本發明揭露一種導電結構，包含一 ^-導體。該支#層覆蓋該第—開D區域之—邊緣，並^ 第一橫向尺寸之一第二開口區域❶該導體，形成於該第二^ 口區域内’其中該第二橫向尺寸實質上不大於該第—橫向尺寸。 本發明更揭露-種於-半導體積職路上碱上述導電 ^方法’該半導體積體電路包含一襯签，及一保護層，局 =婦’以狀出具有-第—橫向尺寸之—第—開口區域 方法包含下列步驟：形成-捕層，蚊義具有—第二橫向尺 =一第二開Π區域’其中該第二橫向尺寸實質上不大於該第一橫 =尺寸，以及形成-導體於該第二開口區域内，以使該導體適可 透過該第一開口區域，與該襯墊呈電性連接。 為讓本發明之上述目的、技術特徵、和優點能更明顯易懂， 下文係以較佳實施例配合所附圖式進行詳細說明。 【實施方式】 第2(a)圖到第2(e)圖係顯示本發明之一較 其 種用於一半導體積體電路20之製造流程。罕1貫 見 7 1334183 如第2(a)圖所示，該半導體積體電路2〇，包含一概^^以及 -保遵層22 ’在本實施例中該襯墊21為紹所製成，且該保護層 22局部覆蓋該襯塾2卜以將該襯塾21部分裸露，以形成一第一 開口區域，作為之後與凸塊電性連接之窗口其中該第一 域具有-第-橫向尺t W1。由於保護層22 第-開口區域之第-檢向尺寸W1將會小於襯塾之橫向尺寸。 接著形成_導電層’例如-鈦鎢合金導電層23，以藉此導 電流，使得凸塊可以於電酿序巾形成^本實補恤鎢合金導 電層23形成時包含-中央區域231與一周緣區域232，其中該中 央區域231覆蓋該第一開口區域，且該周緣區域232延伸於保嘆 層22之上，如第2(b)圖所示。導電層亦可包含具有局部增厚之部 为丄如第3圖所不’其中中央區域具有—第—縱向尺寸m，周緣 ίίΪ—ΪΪ具有—第二縱向尺寸H2 ;且H2不小於H1。（關於 第3圖之完整說明，容後敘述）。 接著在鈦鎢合金導電層23之上形成一不具導電性之支撐層， =如一聚醯亞胺（Polyimide，PI)層24，並將該ρι層24於該第 區域位置之部分關如蝴之方式清除，以暴露出該欽鎮 ς金H層23 ’並定義-第二開口區域’其具有第二橫向尺寸 道第2⑹圖所示。其中該第二開口區域所暴露出的鈦鎢合金 電θ 23，係作為電鍍形成凸塊之底面。若不產生如所述先前技 Γ之缺失，該底面需為一實質上平整之表面，依此架構，W2實質 士 =大於W1，以確保由該第二開口區域所暴露出的鈦鎢合金導電 曰，係為一期待的平整表面。該PI層24於該一第二開口區域 =置’具有-第三縱向尺寸H3。該支撐層亦可由BCB材料所 一几，著在該第二開口區域，利用電鍍方式形成一導體，以做為 2/ ’該凸塊25可由金所製成，並具有—第四縱向尺寸H4， ;支撐層本身並不具有導電性，因此凸塊252H4需連續形成 8 1334183 πΊ】於支撐層之Η3為止’第2(d)圖所示之H4大於H3，意即 整上表面251之凸塊25順利與電路板電性連結，如 —最後，利用蝕刻方式將不需要部分去除，僅保留凸塊25與一 3例^支撐層24及其下方之結構，如第2(e)圖所示。該結▲之 ^凸塊25之橫向尺寸較絲技術者小，惟因其具備二側 雷支持，不但使凸塊25獲得平整之上表面，以供良好 電性連接，亦使整體結構更加穩固。 政如第夕1圖^示本發明之另一變化實施例’係為一半導體積體電 22+刀製程示意圖，其他製程因與上述實施例相同，在此不 再贅述。該導電結構包含具有局部增厚之鈦鎢合金導電層33 ϋϊίί合金導電層33具有一中央區域331以及一周緣區 該中央區域331 (延續至該周緣區域332之一第一部分 333)具有-第—縱向尺寸m，該周緣區域之一第二部份具有一 ，一縱向尺寸H2。且H2不小於m，如第3圖所示，H2大於 H1 〇 、 月後具冗減的表面，因此若鈦鎢合金導電層33之 亦可能會在粗縫表面形成斷點（即增加 抗、或使阻抗獨勻），而影響電鍍的效果。但若導 電層33之中央區域331厚度過厚，則鈦鎢合金即會顯現較 抗，而影響凸塊與襯墊之電性連結。因此 ^ : ，合金導電層33，使得H2大於m。而具有H2之^以^太 孙332 ’在凸塊形成後，會被綱清除，僅存留第—部份扭， 因此並不會影響最後的凸塊之導電結構。 施例中’導電層係以底層金屬構成，惟其不限於 由鈦鎢口金所製成，亦可僅利用例如鈦之金屬製成。 、 藉由亡述之揭露，本發明之導電結構_於 撺層之設計，可確保凸塊形成時具有平魏面，以射路板g 1334183 232周緣區域 24支撐層 25凸塊 251上表面 30半導體積體電路 33鈦鎢合金導電層 331中央區域 332周緣區域之第二部份 333周緣區域之第一部份

Claims (1)

1334183
第096105681號專利申請案 申請專利範圍替換本（無劃線版本，99年8月） 、申請專利範圍 1. 一種用於一半導體積體電路之導電結構，其中該半導體積體電 路包^一襯墊(Pad)及一保護層，局部覆蓋該襯墊，以界定出具 ，一第一橫向尺寸之一第一開口區域，該導電結構適可透過^亥 .第一開口區域’與該襯墊呈電性連接；該導電結構包含：Λ 支揮層，覆蓋§亥苐一開口區域之一邊緣，並定義出且有 -一第一橫向尺寸之一第二開口區域； —導體’形成於該第二開口區域内；以及 —導電層，其具有一中央區域及一周緣區域； .▲其中該中央區域實質上形成於該導體與該襯墊之 間；該周緣區域，形成於該中央區域之一外緣，且至少 f形成於該支撐層與該保護層之間；該周緣區域具有 、邛知及一第一部份，該中央區域及該周緣區域之第一部 份，均具有一第一縱向尺寸，而該周緣區域之第二部 具有一第二縱向尺寸； -縱ΪΓΐϊί橫向尺寸實質上不大於該第一橫向尺寸，該第 一縱向尺寸貫質上大於該第一縱向尺寸。 z 電結構’其中該支撐層具有—第三縱向尺寸， ΐ三縱向尺寸，該第四縱向尺寸實質上不小於該 3.如明求項1之導電結構’其中該導電層係由鈦鹤合金所製成。 導電結構’其中糊層材料係選自PI與腳 5‘ 半導體频電路之導f結構之成形方本 電路包含—簡Pad)，及— 界疋出具有一第—橫向尺寸之一第一開口區域，包含 12 1334183 Μ 第096105681號專利申請案 '. .j 申請專利範圍替換本（無劃線版本,99年8月） 使其一中央區域，座落於該第一開 口區域内，並使其一周緣區域，從該中央區域延伸於該保護層 上； (b) 形成一支撐層於該導電層上，該支撐層至少局部覆 蓋於該導電層之周緣區域，以定義具有一第二橫向尺寸之一第 二開口區域，其中該第二橫向尺寸實質上不大於該第一橫向尺 寸；以及 (c) 形成一導體於該第二開口區域内，以使該導體適可 透過該第一開口區域的該導電層，與該襯墊呈電性連接。 6. 下列步驟： (a) 形成一導電層 如請求項5之方法，其中該步驟(c)中，該導體係持續形成至該 導體之一第四縱向尺寸，實質上不小於該支撐層之一第三縱向 尺寸為止。 13
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