TWI327419B - - Google Patents
Download PDFInfo
- Publication number
- TWI327419B TWI327419B TW92124658A TW92124658A TWI327419B TW I327419 B TWI327419 B TW I327419B TW 92124658 A TW92124658 A TW 92124658A TW 92124658 A TW92124658 A TW 92124658A TW I327419 B TWI327419 B TW I327419B
- Authority
- TW
- Taiwan
- Prior art keywords
- circuit
- output
- input
- signal
- semiconductor integrated
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 claims description 40
- 230000007704 transition Effects 0.000 claims description 28
- 238000012544 monitoring process Methods 0.000 claims description 19
- 238000013508 migration Methods 0.000 claims description 11
- 230000005012 migration Effects 0.000 claims description 11
- 230000004044 response Effects 0.000 claims description 5
- 239000000758 substrate Substances 0.000 description 26
- 238000010586 diagram Methods 0.000 description 16
- 230000005540 biological transmission Effects 0.000 description 10
- 239000000872 buffer Substances 0.000 description 10
- 230000008054 signal transmission Effects 0.000 description 8
- 238000013016 damping Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 230000009471 action Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Landscapes
- Logic Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW092124658A TW200511720A (en) | 2003-09-05 | 2003-09-05 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW092124658A TW200511720A (en) | 2003-09-05 | 2003-09-05 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200511720A TW200511720A (en) | 2005-03-16 |
| TWI327419B true TWI327419B (enExample) | 2010-07-11 |
Family
ID=45074392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW092124658A TW200511720A (en) | 2003-09-05 | 2003-09-05 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TW200511720A (enExample) |
-
2003
- 2003-09-05 TW TW092124658A patent/TW200511720A/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| TW200511720A (en) | 2005-03-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4814791B2 (ja) | レベル・シフター | |
| JP3038094B2 (ja) | 半導体集積回路装置の出力回路 | |
| US5917348A (en) | CMOS bidirectional buffer for mixed voltage applications | |
| JP2002094365A (ja) | 出力バッファ回路 | |
| US6970024B1 (en) | Over-voltage protection of integrated circuit I/O pins | |
| US7271639B2 (en) | Voltage level converter circuit and semiconductor integrated circuit device | |
| US7843234B2 (en) | Break-before-make predriver and level-shifter | |
| JP4005086B2 (ja) | 半導体集積回路 | |
| US7906988B2 (en) | Tolerant buffer circuit and interface | |
| EP1717955B1 (en) | Buffer circuit | |
| TWI327419B (enExample) | ||
| US7663407B2 (en) | Semiconductor device having transfer gate between pre-buffer and main buffer | |
| US6741106B2 (en) | Programmable driver method and apparatus for high and low voltage operation | |
| US6798267B1 (en) | Buffer circuit with programmable switching thresholds | |
| JPH04153761A (ja) | 出力バッファ | |
| JPH07326958A (ja) | 半導体集積回路装置 | |
| JP2000307410A (ja) | 集積回路 | |
| JP2004180241A (ja) | アナログスイッチ回路 | |
| JP2903885B2 (ja) | Cmos出力バッファ回路 | |
| KR950007514Y1 (ko) | 반도체 장치의 출력 포트회로 | |
| US20080122487A1 (en) | Low Power Logic Output Buffer | |
| JPH0537345A (ja) | 半導体出力バツフア回路 | |
| JP2500775B2 (ja) | 半導体集積回路 | |
| KR100410813B1 (ko) | 반도체소자의고속저전력구동회로를구현하기위한인버터 | |
| JP2567152B2 (ja) | Cmos論理回路 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |