1297935 九、發明說明： 【發明的應用範圍】 本發明是關於一種覆晶構裝及其形成方法，特別是關於一種具有可靠 接合結構之覆晶構裝及其形成方法。 【發明的背景】 隨著電子產品朝輕、薄、短、小、高速化與高機能化之發展 趨勢，半導體元件構裝的技術不斷突破創新，對於增加元件可靠 度、密度以及減少元件尺寸方面的要求不斷提高，對於半導體元 件構裝以及接合技術的條件越來越嚴苛。 因此，傳統打線接合（wire bonding)技術逐漸被各種新的接 合技術所取代’如覆晶構裝技術（fl ip-chip)或覆晶直接晶片構裝 (flip-chip direct chip attachment，DCA)技術。覆晶構襞技術 係以晶片與基板的接合面形成銲球陣列（array of solder ball) 或是凸塊（bump)以取代習知封裝技術所使用的導線架（lead frame)。透過直接壓合晶片與基板的接合面之間的銲球陣列 (array of solder ball)或凸塊來達成電路導通，可降低晶片與芙 板間的電子訊號傳輸距離，適用於高速元件的封裝。 現今液晶顯示器在封裝方法上，多是採用捲帶式承载封裝（tape carrier package，TCP)，近來由於聚亞醯胺(polyimide，ρι)基板材料與 1297935 製程的進步’而演進至晶粒軟膜接合技術(chip 〇n flex, COF)的覆晶（flip chip)構裝方法，因而大幅地提昇接合間距(pitch)與可撓曲性。一般習知 晶粒軟膜接合技術的覆晶構裝方法，係於晶片及基板的表面形成凸塊(bu邮) 等接合結構，然後在基板表面塗佈接著劑；再將晶片及基板表面的凸塊經 過對位之後直接壓合即完成覆晶構裝結構。一般覆晶構裝所使用的接著劑 可分為異方向性導電接著劑（Anisotropic Conductive Film，ACF)及非導 電接著劑(Non-conductive Film，NCF)，兩者皆為環氧樹脂類的高分子材 料。由此可知，在晶片與基板使用接著劑加以接合時，彼此間具有 嚴重的熱膨脹係數差異。當溫度產生變化時，由於熱應力的影響 容易使晶肢基板的凸塊触產生變形。此外，由於魏樹鋪的高分子 材料具有賴性，也會使晶及基板的凸塊触產生氧化情形而影響其電 阻值。 因此，在JP2001-144143號日本專利中，提出一種新的覆晶構裝結構。 先在晶片及基板上以植球(stud b_)方式形成帶有—尖端之金屬球，並將 基板表面的金屬球之尖端處加以局部整平，以在基板形成中間帶有一凹處 的金屬球。最後將晶片表面之帶有一尖端之金屬球對位於基板之帶有一凹 處的金屬球再加以壓合。由於其形狀可以彼此丧合在一起有助於晶片與基 板之接點的可靠度，避免接點受到減力辟產生獅。但是湘此方法 的製程較為複雜’ f要分別在基板及晶壯植球。而且，由於需透過植球 1297935 方式來製造帶有—尖端之金屬球和帶有—凹處的金屬球，其接點不能太密 而影響到其線寬和間距。 【發明之目的與概述】 雲於以上習知技術的問題，本發明的目的在於提供一種覆晶構裝及其 形成方法。本發明係透過晶片表面之導電凸塊與基板表面之導電電極相互 嵌合，並且增加其接合的強度以及導電性質。本發明可應用於更細的線寬， 不僅可增加導電線路密度同時仍可達到一定的導電穩定性。 為達上述目的’本發明所提供之覆晶構裝，其包含有：一晶片，其表 面係具有複數個導電凸塊，複數個導電凸塊之頂端面積為W1，其硬度為H1; 一基板’其表面係具有複數個導電電極，且導電電極之頂端面積W2小於wi， 導電電極的硬度H2大於H1，複數個導電電極係穿進複數個導電凸塊以結合 晶片與基板；及一接著材料，係用以黏著與接合晶片與基板。本發明是透 過與導電凸塊相比硬度較高且頂端面積較小的導電電極；加壓使導電電極 與導電凸塊相互嵌合。 其中，複數個導電凸塊之材料係為金、錫與錫鉛合金其中之一；其複 數個導電電極之材料係為銅，外層鍍有鎳與金金屬層；複數個導電凸塊可 以電鍍與無電鍍其中之一方法形成；接著材料係為一熱固性高分子材料。 以及，應用相同的原理，本發明另有一覆晶構裝結構，係將上述之導 電凸塊和電極的硬度以及頂端面積加以改變，使導電電極之頂端面積f2大 1297935 於導電凸塊頂端面㈣，同時讓導電凸塊的硬度H1大於導電電極硬度取。 係將導電凸塊對健穿進導電電_互嵌合，以結合晶片與基板。 其中’複數個導電凸塊之獅係為峨難巾之―；複數個導電電極 之材料係為顯外層賴之編巾之魏個導電凸塊細續與無電 鍍其令之一方法形成。 此外，本發明更包含覆晶構裝的形成方法，係將上述之導電凸塊與導 電電極分別形成在晶>{與基板的表面，同時其複數個導電凸塊之頂端面積. 為Π ’其硬度為H1，·複數個導電電極之頂端面積為肫，其硬度為H2 ;塗 佈接著材料於基板表面；再將晶片表面之複數個導電凸塊對準基板表面 之複數個導ff極，域使其互減合，同時加熱以__著材料。 需注意當其複數個導電電極之頂端面積W2小於W1時，複數個導電電 極的硬度H2大於H1 ;其接點為導電電極穿入導電凸塊。而在複數個導電電 極之頂端面積W2大於W1時’複數個導電電極的硬度H2小於耵，其則為導 電凸塊穿入導電電極使兩者相互嵌合。 有關本發明的特徵與實作，茲配合圖示作最佳實施例詳細說明如下· 【較佳實施例說明】 根據本發明所揭露之覆晶構裝及其形成方法，乃利用晶片表面 電 凸塊與基板表面之導電電極相互嵌合。使覆晶結構具有更高的接點強声矛 良好的導電性質。同時，應用本發明之覆晶構裝的形成方法，相較於一 、一^般 1297935 的覆晶構裝方法僅需較低的壓力即可使導電電極與導電凸塊相互嵌合。 本發明之覆晶構裝結構’請參考第1圖，其為本發明之第一實 施例的覆晶構裝示意圖。包含：一晶片10，其表面係具有複數個導電 凸塊30 ; —基板20，其表面係具有複數個導電電極，且導電電極4〇之 截面為三角形，複數個導電電極40係穿進複數個導電凸塊3〇以結合晶片 與基板；及一接著材料50，係用以黏著與接合晶片與基板。本發明實施例 利用硬度鬲於導電凸塊30且截面為三角形的導電電極加壓使導電電極 40與導電凸塊30相互嵌合。 本發明的第-實施例則可由以下的操作步驟加以實行，請參考 第2圖，第2圖為本發明第—實施例之晶片與基板對位示意圖。 首先提t、曰曰片1 〇 ’在其表面形成複數個導電凸塊;其次， 提供-基板2G，於其頂端表面上形成_狀的複數個導電電極 化塗佈-接著_〇於基板2〇表面；再將晶片1〇表面之複數個導電凸 塊30對準基板20表面之複數個導電電極4Q，加壓使其互相嵌合，同時加 熱以固化接著材㈣。需注意細_電㈣的硬度係大於複數個導電 凸塊3〇’而域面為咖的導電電極仙在接合時使壓力集中在導電凸塊 3〇的某一區域’有助於使導電電極㈣入導電凸塊30。 其中，複數個導電凸塊之材料係為金、锡與錫錯合金其中之-；发複 數個導_之_為銅，外___其中之-；複數個導 1297935 電凸塊可以電鍍與無電鍍其中之—方法形成；接著材料鱗—熱固性高分 子材料。 以及，本發明另有-覆晶構裝結構，請參考第3圖，其為本發明之第 二實施例的示意圖。本發明之第二實施例係將上述之導電凸塊和電極的硬 度以及頂端面積加以改變，其包含有：—晶片6G，其表面係具有圓錐狀的 複數個導電凸塊80 ; -基板70，其表面係具有複數個導電電極9〇，複數個 導電凸塊80係穿進複數個導電電極90，與複數個導轉極9〇相互嵌合， 以結合晶片與基板；及-接著材料⑽，係用以黏著與接合晶片與基板。本 發明實施例利用硬度高於導電電㈣且頂端成圓錐狀的導電凸塊虬加壓 使導電凸塊9G欽導電電極8G以形成穩定的接點。本發明第二實施例係 與第-實施例的形成方法大致相同，請參考第4圖，第4圖為本發明 第二實施例之晶片與基板對位示意圖。僅改變導電電極與導電凸塊的 硬度以及雜（即頂端φ積）’以改變錢晶構裝接關嵌合結構。 欲使本發雜翻其姐，魏數辦電電極之頂端面積?2 小於導電凸塊的頂端面積W1時，複數個導電電極的硬度h2需大於導電凸 塊硬度H1 ;其接點為導電電極穿入導電凸塊。而在複數個導電電極之頂端 面積呢大於wi時，複數個導電電極的硬度H2小於m，其接點則為導電凸 塊穿入導電電極。本發明祕導電料對位並與導電電極相互嵌合以結合 晶片與基板。 1297935 當可作些許之更 4視本說明書所附之+請專利範圍 雖然本發明之較佳實施例揭露如上所述，然其並非用以限定本發明， 任何熟習相職藝者，在不_本魏之料和範圍内， 動與潤僻，因此本發明之專利保護範圍 所界定者為準。 【圖式簡單說明】 第1圖為本發明之第—實施例的覆晶構I示意圖； 圖為本發明第-實施例之晶片與基板對位示意圖； 第3圖為本發明之第二實施例的覆晶構裝示意圖；及 第4圖為本發明第-實施例之晶片與基板對位示意圖。 【主要元件符號說明】 10晶片 20基板 30導電凸塊 40導電電極 50接著材料 60晶片 70基被 80導電凸塊 90導電電極 12 1297935 100接著材料1297935 IX. DESCRIPTION OF THE INVENTION: Scope of Application of the Invention The present invention relates to a flip chip package and a method of forming the same, and more particularly to a flip chip package having a reliable joint structure and a method of forming the same. [Background of the Invention] With the development trend of electronic products toward lightness, thinness, shortness, smallness, high speed, and high performance, the technology of semiconductor component mounting has continuously broken through innovations, in terms of increasing component reliability, density, and component size reduction. The requirements are constantly increasing, and the conditions for semiconductor component mounting and bonding technology are becoming more and more stringent. Therefore, the traditional wire bonding technology is gradually being replaced by various new bonding technologies, such as flip ip-chip or flip-chip direct chip attachment (DCA) technology. . The flip-chip technique forms an array of solder balls or bumps on the interface between the wafer and the substrate to replace the lead frame used in conventional packaging techniques. The circuit conduction is achieved by directly pressing the array of solder balls or bumps between the bonding surface of the wafer and the substrate, thereby reducing the electronic signal transmission distance between the wafer and the board, and is suitable for packaging high-speed components. In today's liquid crystal display, most of the packaging methods are tape carrier package (TCP), which has recently evolved to die-film bonding due to the advancement of polyimide (polyimide, ρι substrate material and 1297935 process). The flip chip mounting method of the technology (chip 〇n flex, COF) greatly improves the pitch and flexibility of the joint. A conventional method for crystallizing a crystal film bonding technique is to form a bonding structure such as a bump on a surface of a wafer and a substrate, and then apply an adhesive on the surface of the substrate; and then pass the bumps on the surface of the wafer and the substrate. After the alignment, the flip-chip structure is completed by direct pressing. The adhesive used in the general flip chip mounting can be classified into an anisotropic conductive adhesive (ACF) and a non-conductive film (NCF), both of which are high in epoxy resin. Molecular material. From this, it is understood that when the wafer and the substrate are joined by using an adhesive, there is a serious difference in thermal expansion coefficient between each other. When the temperature changes, the bump of the crystal substrate is easily deformed due to the influence of thermal stress. In addition, due to the dependence of the polymer material of Wei Shupu, the bumps of the crystal and the substrate may be oxidized to affect the resistance value. Therefore, a new flip chip structure is proposed in Japanese Patent No. 2001-144143. First, a metal ball with a tip is formed on the wafer and the substrate in a stud b_ manner, and the tip of the metal ball on the surface of the substrate is partially flattened to form a metal ball with a recess in the middle of the substrate. . Finally, a metal ball with a tip on the surface of the wafer is pressed against a metal ball with a recess on the substrate. Since the shapes can be combined with each other to contribute to the reliability of the contact between the wafer and the substrate, the contact is prevented from being reduced to produce a lion. However, the process of this method is more complicated, and f is to be planted on the substrate and crystal. Moreover, since the metal ball with the tip and the metal ball with the recess are manufactured by the ball-feeding 1297935, the joints are not too dense to affect the line width and the pitch. [Objective and Summary of the Invention] The problem of the above conventional techniques is to provide a flip chip structure and a method of forming the same. In the present invention, the conductive bumps on the surface of the wafer are fitted to the conductive electrodes on the surface of the substrate, and the strength and conductive properties of the bonding are increased. The invention can be applied to a finer line width, which not only increases the density of the conductive line but also achieves a certain conductive stability. In order to achieve the above object, the flip chip package provided by the present invention comprises: a wafer having a plurality of conductive bumps on its surface, the plurality of conductive bumps having a top end area of W1 and a hardness of H1; 'The surface has a plurality of conductive electrodes, and the top surface area W2 of the conductive electrode is smaller than wi, the hardness H2 of the conductive electrode is greater than H1, and the plurality of conductive electrodes penetrate the plurality of conductive bumps to bond the wafer and the substrate; and a bonding material Used to bond and bond the wafer to the substrate. The present invention is a conductive electrode having a higher hardness and a smaller tip area than a conductive bump; the conductive electrode and the conductive bump are fitted to each other by pressurization. Wherein, the material of the plurality of conductive bumps is one of gold, tin and tin-lead alloy; the material of the plurality of conductive electrodes is copper, the outer layer is plated with nickel and gold metal layers; and the plurality of conductive bumps can be plated and One of the methods of electroless plating is formed; then the material is a thermosetting polymer material. And applying the same principle, the present invention has a flip-chip structure, which changes the hardness and the top end area of the conductive bump and the electrode, so that the top surface area f2 of the conductive electrode is 1297935 on the top surface of the conductive bump (4). At the same time, the hardness H1 of the conductive bump is greater than the hardness of the conductive electrode. The conductive bumps are mechanically inserted into the conductive body to bond the wafer and the substrate. Among them, the lion system of the plurality of conductive bumps is a sturdy towel; the material of the plurality of conductive electrodes is formed by one of the method of polishing the conductive bumps of the outer layer and the electroless plating. In addition, the present invention further includes a method for forming a flip chip package, wherein the conductive bump and the conductive electrode are respectively formed on the surface of the substrate, and the top surface area of the plurality of conductive bumps is Π ' The hardness is H1, the top surface area of the plurality of conductive electrodes is 肫, and the hardness is H2; the coating material is applied to the surface of the substrate; and the plurality of conductive bumps on the surface of the wafer are aligned with the plurality of ff poles on the surface of the substrate, The domains are made to reduce each other while heating to __ the material. It should be noted that when the top surface area W2 of the plurality of conductive electrodes is less than W1, the hardness H2 of the plurality of conductive electrodes is greater than H1; the contact point is that the conductive electrodes penetrate the conductive bumps. When the top surface area W2 of the plurality of conductive electrodes is larger than W1, the hardness H2 of the plurality of conductive electrodes is smaller than 耵, and the conductive bumps penetrate the conductive electrodes to fit the two. The features and implementations of the present invention will be described in detail with reference to the preferred embodiments. The preferred embodiment of the present invention is as follows: The flip-chip assembly and the method for forming the same according to the present invention utilize the surface electroconvening of the wafer. The block and the conductive electrode on the surface of the substrate are fitted to each other. The flip chip structure has a higher contact point and a good acoustic spear. At the same time, by applying the flip chip mounting method of the present invention, the conductive electrode and the conductive bump can be fitted to each other by a lower pressure than the flip chip mounting method of 1297935. The flip chip structure of the present invention is referred to Fig. 1, which is a schematic view of the flip chip structure of the first embodiment of the present invention. The invention comprises: a wafer 10 having a plurality of conductive bumps 30 on its surface; a substrate 20 having a plurality of conductive electrodes on its surface, and a cross section of the conductive electrode 4 is triangular, and a plurality of conductive electrodes 40 are inserted into the plurality of conductive electrodes 40. The conductive bumps 3 are bonded to the wafer and the substrate; and a bonding material 50 is used to adhere and bond the wafer and the substrate. In the embodiment of the present invention, the conductive electrode 40 and the conductive bump 30 are fitted to each other by pressurizing the conductive electrode having a hardness 鬲 to the conductive bump 30 and having a triangular cross section. The first embodiment of the present invention can be carried out by the following operational steps. Please refer to FIG. 2, which is a schematic view of the alignment of the wafer and the substrate according to the first embodiment of the present invention. First, t, the cymbal 1 〇 'forms a plurality of conductive bumps on the surface thereof; secondly, the substrate 2G is provided, and a plurality of conductive electrode coatings are formed on the top surface of the y-shaped surface - and then the substrate 2 The surface of the crucible is further aligned with a plurality of conductive bumps 30 on the surface of the wafer 1 by a plurality of conductive electrodes 4Q on the surface of the substrate 20, and pressed to be fitted to each other while being heated to cure the bonding material (4). It should be noted that the hardness of the electric (four) is greater than the plurality of conductive bumps 3〇', and the conductive electrodes of the domain are condensed to concentrate a certain area of the conductive bumps 3〇 during bonding to help make the conductive electrodes (4) Entering the conductive bump 30. Wherein, the materials of the plurality of conductive bumps are among the gold, tin and tin alloys; the plurality of conductive _ _ is copper, the outer ___ among them; the plurality of conductive 1297935 electric bumps can be plated and In electroless plating, the method is formed; then the material scale is a thermosetting polymer material. Further, the present invention has a flip-chip structure, and reference is made to Fig. 3, which is a schematic view of a second embodiment of the present invention. The second embodiment of the present invention changes the hardness and the top end area of the above-mentioned conductive bumps and electrodes, and includes: a wafer 6G having a plurality of conductive bumps 80 having a conical shape on the surface; - a substrate 70, The surface has a plurality of conductive electrodes 9〇, and the plurality of conductive bumps 80 are penetrated into the plurality of conductive electrodes 90, and are combined with the plurality of conductive electrodes 9〇 to bond the wafer and the substrate; and – the material (10), Used to bond and bond wafers and substrates. In the embodiment of the present invention, the conductive bumps 9G are used to press the conductive bumps 8G to form stable contacts by using conductive bumps having a hardness higher than that of the conductive electrodes (four) and having a tipped shape. The second embodiment of the present invention is substantially the same as the method of forming the first embodiment. Please refer to FIG. 4, which is a schematic diagram of the alignment of the wafer and the substrate according to the second embodiment of the present invention. Only the hardness and the miscellaneous (i.e., the top φ product) of the conductive electrode and the conductive bump are changed to change the chisel structure. If the top surface area of the electrode is smaller than the top surface area W1 of the conductive bump, the hardness h2 of the plurality of conductive electrodes needs to be greater than the hardness H1 of the conductive bump; the contact is a conductive electrode. Penetrate the conductive bumps. When the top end of the plurality of conductive electrodes is larger than wi, the hardness H2 of the plurality of conductive electrodes is less than m, and the contact points are the conductive bumps penetrating the conductive electrodes. The secret conductive material of the present invention is aligned and mated with the conductive electrodes to bond the wafer to the substrate. 1297935 The following is a description of the preferred embodiment of the present invention. Although the preferred embodiment of the present invention is as described above, it is not intended to limit the present invention, and any skilled practitioner is not Within the scope and scope of this invention, it is intended to be dynamic and invigorating, and therefore the scope defined by the patent protection of the present invention shall prevail. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a flip-chip structure of a first embodiment of the present invention; FIG. 3 is a schematic view of alignment of a wafer and a substrate according to a first embodiment of the present invention; FIG. 4 is a schematic view showing the alignment of a wafer and a substrate according to the first embodiment of the present invention. [Main component symbol description] 10 wafer 20 substrate 30 conductive bump 40 conductive electrode 50 bonding material 60 wafer 70 substrate 80 conductive bump 90 conductive electrode 12 1297935 100 followed by material