1294129 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種被動元件及其製造方法，特別是 指一種具有微歐姆（micro_Q )等級阻值的晶片電阻元件及 其製造方法。 【先前技術】 參閱圖1，晶片電阻元件是一種銲黏在積層電路板 (PCB)上的被動元件，用於提供微歐姆尺度的電阻值。該 晶片電阻元件i包含—基材U、二正端電極12、二背端口電 極13電阻層丨4、一保護層15、二側面電極16，及二 鍍層17。 一 北Λ基材11疋以絕緣材料構成，略成矩形板狀並具有一 月面U1、二分別自該背面111的相反兩側向上延伸的側面 112，及一連接該二侧面112頂邊的正面I”。 正知電極12是可導電並相間隔地形成在該BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a passive component and a method of fabricating the same, and more particularly to a chip resistor component having a micro-ohm (micro_Q) rating and a method of fabricating the same. [Prior Art] Referring to Fig. 1, a chip resistor element is a passive component soldered to a laminated circuit board (PCB) for providing a resistance value of a micro-ohmic scale. The chip resistive element i includes a substrate U, two positive terminal electrodes 12, two back port electrodes 13 resistive layer 丨4, a protective layer 15, two side electrodes 16, and a second plating layer 17. A north Λ substrate 11 疋 is made of an insulating material, has a rectangular plate shape and has a moon face U1, two side faces 112 extending upward from opposite sides of the back face 111, and a top side connecting the two side faces 112. Positive I". The electrode 12 is electrically conductive and spaced apart at the
上，且母一正端電極12相對遠離另一正端電極之側 與該基材11的一側面112相重合 月编電極13疋可導電並相間隔地形成在該背淺 且該每_背端電極13相對遠離另—背端電極〜 ’、與：基材u的一侧面ιΐ2相重合’使得該二正端, ^ 12、背端電極13彼此相對稱。 邊電阻層Η具有預定的電阻值，設置在該背面 位於該二背端電極13 之 分區域分別㈣一端雷：…，且，、相反的兩側邊部 一-一月鸲電極13側邊區域相疊合而盥該二 1294129 端電極13形成電連接。 該保護層15是以絕緣材料構成， 再风對應包覆该電阻層14 使该電阻層14與外界相隔絕。 该一側面電極16以可導雷的好 罨的材科構成，分別形成在二 側面112上並分別與同一側邊 此山+ 1㈣之叙、背端電極12、13相 接觸而電連接。 該二鍍層17分別以錫為主要構成材料形成在同側邊之 正端電極12、側面電極16與背端電極13上。 上述晶片電阻元件1確實可以藉由兩背端電極13與二 側面電極16以及二鍍層17並利用銲錫3〇〇 路板100的銲墊200上，淮而LV ώ蚀 上進而以自積層電路板1〇〇之一銲 墊200經過該晶片電阻元件1 -側的鍍層Π、背端電極13 、電阻層14、至另-侧的背端電極13，到達另一銲墊200 所形成的電流路徑提供電路中微歐姆尺度的電阻值。 但是，由於此等晶片電阻元件i在鲜固於積層電路板 100上時3保遵層15會直接接觸到積層電路板1〇〇及/或 疋銲墊2GG而造成二鑛層17相對欲銲固之銲墊成架空 狀態，不但不易於對應銲墊2〇〇放置正確的位置上，同時 ，以銲錫300銲黏固定時也常會造成假銲而導致電性失效 參閱圖2，有鏗於此，美國專利第6856234B2號「 CHIP RESISOR」提出另一種易於銲黏固定在積層電路板 100上的晶片電阻元件2，其包含一基材21、二正端電極 22、二背端電極23、一電阻層24、一保護層乃、二側面電 1294129 極26、二辅助填充物27，及二鍍層28。 該基材21是以絕緣材料構成，略成矩形板狀並具有一 月面211 —刀別自该背面211的相反兩側向上延伸的側面 212 ’及一連接該二側面212頂邊的正面213。 該二正端電極22是可導電並相間隔地形成在該正面 213上，且每一正端電極22相對遠離另一正端電極之側 邊與該基材21的一側面212相重合 該二背端電極23是可導電並相間隔地形成在該背面 211上，且該每一背端電極23相對遠離另一背端電極23之 側邊亦與該基材21的一側面212相重合，使得該二正端電 極22、背端電極23彼此相對稱。 該電阻層24具有預定的電阻值，設置在該背面2ιι之 位於該二背端電極23之間的區域上，且其相反的兩側邊部 分區域分別與該二背端電極23侧邊區域相疊合而與該二背 端電極23形成電連接。 該保護層25是以絕緣材料構成，對應包覆該電阻層24 使該電阻層24與外界相隔絕。 該二側面電極26以可導電的材料構成，分別形成在二 側面212上並分別與同一側邊之該正、背端電極22、相 接觸而電連接。 該二辅助填充物27分別以導電材料自該二背端電極23 表面向下形成且截面略成梯形。 該二鍍層28分別以鍚為主要構成材料自同侧邊之該正 端電極22、側面電極26與辅助填充物27表面向上形成。 1294129 上述晶片電阻元件2確實可藉由二輔助填充物27的形 狀，使得銲層28對應該二背端電極23的截面形狀斜向保 遵層25延伸，而易於對應定位至積層電路板1〇〇的銲墊 200上，進而利用以錫為主的材料構成的鍍層28與銲錫 300作良好的結合，而相對銲固在積層電路板1〇〇的銲墊 200 上。 但是，要形成此等晶片電阻元件2截面呈梯形的辅助 填充物27，一來會多增加至少一道製程步驟，二來亦無法 於貫際S產製程中，完美的成形出該等成特殊形狀態樣的 辅助填充物27，因此，該具有輔助填充物27的晶片電阻元 件2雖然在結構上確實可以良好定位並藉銲錫3〇〇銲固於 銲墊200上，但貫際上並無法於生產線上量產實施。 此外，由於此等晶片電阻元件2於電路中的功效在於 提供微歐姆尺度等級的電阻值，也就是說，由一銲墊2⑻ 經過元件2 —側的背端電極23、電阻層24、至另一側的背 端電極23，到達另一銲墊2〇〇所形成的電流路徑相對會嚴 重影響實際於電路中的電阻值；而美國專利第68562/4b2 號「cmPRESIS0R」提出之具有輔助填充物27的晶片電 阻元件3，由於增加了辅助填充物，所以相對使得電阻 層24較為遠離積層電路板1〇〇的銲墊2〇〇，如此一來不但 增加了電流路徑長，同時也使得晶片電阻元件2經過銲墊 200導熱的路徑長增加而相形困難，因此，元件2本身適用 的功率不但較小，同時提供的阻值亦因溫度的影響而較為 不穩定。 _ 1294129 所以’目前的晶片電阻元件！、2 f要加以改善，使其 不仁亦於位、良好地録固在銲墊上，同肖，也可適用於 大功率應用並提供穩定的微歐姆尺度電阻值。 【發明内容】 因此，本發明之目的，即在提供一種大功率且易於定 位銲固在積層電路板上的晶片電阻元件。 另外，本發明之另一目的，即在提供一種大功率且易 於疋位知固在積層電路板上的晶片電阻元件的製造方法。 、二正 面電極 於疋，本發明一種晶片電阻元件，包含一基材 端電極、二背端電極、一電阻層、一保護膜、二側 ，及二鍍膜。 该基材是絕緣並成板狀，且具有一背面、二分別自該 为面的相反兩側向上延伸的侧面，及一連接該二側面頂邊 的正面。 該二正端電極是可導電並相間隔地形成在該正面上， 且该母一正端電極相對遠離另一正端電極之側邊與該基材 的一側面相重合。 該二背端電極是可導電並相間隔地形成在該背面上， 且該每一背端電極相對遠離另一背端電極之側邊與該基材 的一側面相重合。 該電阻層是具有預定的電阻值並形成在該背面之位於 該二背端電極部之間的區域上，且相反的兩側邊區域分別 與該二背端電極部側邊區域相連接。 該保護膜對應包覆該電阻層表面使該電阻層與外界相 1294129 隔絕。 該二側面電極是可導電並分別形成在二側面上且分別 與同一侧邊之該正、背端電極相電連接。 該二鍍膜分別自同側邊之該正端電極、側面電極與背 端電極表面向上形成，該每一鍍膜具有一以銅為主成分並 與該正端電極、侧面電極與背端電極表面連接的第一鍛層 以鎳為主成分並與該第一鍍層表面連接的第二鍍層， 及-以錫為主成分並與該第二鍍層表面連接的第三鍍層。 再者，本發明一種晶片電阻元件的製造方法，包含以 下步驟。 先在絕緣基板的上表面形成多數縱向間隔排列的縱 破裂槽’及橫向間隔排列的橫破裂溝，該二相鄰的縱破裂 槽與橫破裂溝共同定義出一元件單體區。 再對應每一縱破裂槽在該基板下表面以導電材料形成 二位於該縱破裂槽相反兩側的背端電極條。 然後對應每-縱破裂槽在該基板上表面以導電材料形 成二位於該縱破裂槽相反兩侧的正端電極條。 接著在該基板下表面之每二相鄰之背端電極間的區域 上以預定金屬材料形成—兩側部分別與該二背端電極條電 連接的電阻層條。 再在該多數電阻層條上以絕緣材料分別形成一絕緣層 條。 繼續以高能量射束對應每一元件單體區精確切割調變 該多數絕緣層條與電阻層條的幾何形狀，以精確調變該每 10 1294129 一元件單體區的對應阻值。 然後再在製得之半成品的絕緣層條表面形成一使該具 有預定幾何形狀之電阻層條與外界隔絕的包覆層條。 接者繼績沿該多數縱破裂槽破裂製得之半成品，得到 多數條狀半成品。 然後於該每一條狀半成品的二破裂面以導電材料形成 分別與該正、背端電極條電連接的侧面電極條。 鲁 再沿該多數橫破裂溝破裂製得之每一條狀半成品，得 、到多數分別具有二正端電極、二背端電極、二側面電極、 一電阻層，及一保護膜的晶片電阻元件半成品單體。 最後自該每一晶片電阻元件半成品單體的二正、背、 側面電極表面依序以銅為主要材料成分、錄為主要材料成 为、錫主要材料成分形成二包含有一第一鍍層、一第二鍍 層，及一第三鍍層的鍍膜，製得多數晶片電阻元件。 本發明的功效在於更進一步以簡易的製程以銅、鎳、 • ^主要材料形成鍍層，而使元件簡易地利用液態銲錫正 t疋位在知塾上’並在銲錫凝固時良好的與輝錫鲜黏成一 ^並可以相對減少元件至銲塾的電子流通路徑以及熱傳 ^路U而使I件具有更大功率的應用以及在電路中提 供更精確的微歐姆尺度的電阻值。 【實施方式】 有關本發明之前琉芬甘 心刷迷及其他技術内容、特點與功效，在 以下配合參考圖式夕_如h 個較佳實施例的詳細說明中，將可 清楚的呈現。 11 1294129 在本發明被詳細描述之前，要注意的是，在以下的說 明内容中’類似的元件是以相同的編號來表示。 參閱圖3、圖4，本發明一種晶片電阻元件3的一較佳 貫加例’疋易於銲黏固定在積層電路板上的銲墊2〇〇 上’並易於散熱而適用於大功率應用，其包含一基材31、 二正端電極32、二背端電極33、一電阻層34、一保護膜 35、一側面電極％，及二鐘膜37。 該基材31是以絕緣材料構成，略成矩形板狀並具有一 背面311、二分別自該背面311的相反兩側向上延伸的侧面 312 ’及一連接該二侧面312頂邊的正面。 該二正端電極32是可導電，並分別成長矩形態樣相間 隔地形成在該正面313上，且每一正端電極相對遠離另一 正端電極之側邊與該基材的一側面相312重合。 該二背端電極33是可導電，並分別成長矩形態樣相間 隔地形成在該背面311上，且該每一背端電極33相對遠離 另一背端電極33之侧邊亦與該基材31的一側面312相重 合，使得該二正端電極32、背端電極33彼此相對稱。 該電阻| 34是以例如鈕、鉻、鎳、鋁、錳、銅、銀、 鈀鉑，及此等金屬疋素之合金構成，並具有預定的幾何 恶樣而具有精確的微歐姆尺度電阻值，形成在該背面311 位於該二背端電極33之間的區域上，且其相反的兩側邊^ 分區域分別與該二背端電極33側邊區域相疊合而與該二北 端電極33形成電連接。 月 該保護膜35 {以絕緣材料構成’ #有一形狀與該電阻 12 1294129 層34相似並與連接在該電阻層34表面的絕緣層％ 1，及— 連接在該絕緣層351上並包覆該電阻層34是其與外界 絕的包覆層352。 阳 該二側面電極36分別以可導電的材料，例如銀膏、金 屬荡..等構成，分別形成在二側面312上並分別與同一側邊 之該正、背端電極32、33相接觸而電連接。 邊-鑛膜37分別自同側邊之該正端電極％、側面電極 %與背端電極33表面向上形成，且每一鍍膜37具有—以 銅為主成为並與該正端電極32、侧面電極％與背端電極 33表面連接的第一鍍層371、一以鎳為主成分並與該第— 鍍層371表面連接的第二錢層372，及一以錫為主成分並盘 該第二鑛層372表面連接的第三鑛層奶，且該第芦、 =的厚度大於該第二、三鑛層372、373的厚度和，料 该弟-、二、三鍵層371、372、373的厚度和大於該基材 31背面311至該保護臈35表面的距離。 本月之曰曰片電阻70件3在銲固於積層電路板100的 銲塾 4過程中，可藉由該二錢37最外層以錫為主 要材f的f二鑛層373直接與銲墊接觸，並在接觸到 成炫融狀恶的鲜錫3 f) h 、 同夺炼融’而藉著成液態之銲錫300 WSI的内聚力而自動正確定位’而待輝錫凝固時即 可正確謂形良好地銲固在料上；_，由於該二 鑛膜、37的厚度相對極薄，且第―、二鑛層37卜372的主 要成分分別是導熱性極佳的銅與錄，也就是說銲固在銲墊 之後兀件3的電阻層34不但較接近二銲墊細，由一 13 1294129 I _經過元件3 -側的鑛膜37、背端電極％、電阻層 200至另—側的f端電極％、鍍膜37，而到達另一銲墊 所形成的電流路徑與導熱路徑也相對較短，因此較易於 =而可提供較穩定的微電阻值，同時，也適用於大功率 上述本發明晶片電阻元件3在經過如圖5所示的製程 說明後，當可更加清楚的明白。 參閱圖5 ’製備上述本發明晶片電阻元件3是先進行步 T 501，如圖6、圖7所示地在一絕緣基板謝上表面形成 多數縱橫交錯而成棋盤狀的破裂槽602，並由該相鄰的兩橫 向與縱向的破裂槽繼定義出一元件單體區6〇3;該絕緣基 板6〇1可以是例如玻璃基板、陶究基板，或是以環氧樹醋 $材料所構成的基板，較佳地，該等破裂槽6〇2的深度設 定在數微米之内，而可於後續的製程中以物理方式破裂取 传預定的半成品。 參閱圖5 ’接著進行步驟502，並配合參閱圖8、圖9 ，以印刷方式對應每一縱向的破裂槽6〇2在該基板6〇1下 表面以導電材料印刷形成二對應位於該縱向破裂槽602相 反兩侧的背端電極條6〇4。此外，例如金屬箔貼合方式、真 空賤錢方式、表面鍍金方式都是可以成形背端電極條6〇4 的方式’由於此等形成方式眾多，且非本發明創作重點所 在，在此不多加詳述。 參閱圖5 ’接著進行步驟503，並配合參閱圖1〇、圖u ’接著同樣以印刷方式對應每一縱向的破裂槽602在該基 14 1294129 板601上表面以道_ r 等電材料印刷形成二位於該縱向破裂槽602 相反兩側邊的正、電極條咖。類似地，例如金屬箱貼合方 式真工歳鍍方式等方式都是可以成形正端電極條605的 方式’由於此等形成方式眾多，且非本發明創作重點所在 ，在此不多加詳述。 多閱圖5，接著進行步驟504，並配合參閱圖12、圖 1=接著同樣以印刷方式對應地在該基板謝下表面之兩 月端電極# 604之間印刷形成—兩側邊分別與兩背端電極 604條重疊而連接的電阻層條6〇6。類似地，例如金屬箱貼 合方式、真空濺鍍方式等方式都是可以成形電阻層條_ 的方式，由於此等形点古斗、 /烕方式眾多，且非本發明創作重點所 在’在此不多加詳述。 " 接著進行步驟505，並配合參閱圖14、圖 接著同樣以印刷方式對應地在該每一電阻層冑祕表 面印刷形成一絕緣層條6〇7。 參閱圖5，接著進行步驟篇，並配合參閱^ 16、圖 ^後X例如“射之面能量射束對應每—元件單體區⑽ «切割該多數絕緣層條6〇7與電阻層條6〇6使其具有預 疋的精崔幾何瓜狀’以精確調變該每一元件單體區⑽的 對應電阻值。 參閱圖5，接著進行步驟^ 驟507，並配合參閱圖μ、圖 D，接著在經過上述步驟製 伸之+成品經過切割之絕緣層 條607表面印刷形成一包覆奴 、、二過切割之絕緣層條607與電 阻層條606而使切割後之電阻 層條606與外界隔絕的包覆 15 1294129 層條608。 參閱圖5,接著進行牛 2!，沿步驟5。7製得之::驟5°8’並配合參閱® 2〇、圖 進糾歹」 +成品的多數縱向破裂槽002直接 進仃物理破裂，而得到多數長條狀的半成品。 多閱圖5’接著進行步驟5〇9 23，接著自备一主屮σ l 上阢口翏閱圖22、圖 ⑽的二破裂面609以導電材料形成分 別與該每—半成品 ^材料成刀 的一正、背端電極條605、604電連 接的侧面電極條61〇;在本 甲 疋直接在母一半成品的二 破β面609上塗覆銀膏，待並 竹，、軏躲即成该二側面電極條61〇 參閱圖5，接著進行步驟51〇,並配合參閱目24、圖 25’在完成側面電極條⑽㈣作後，即沿著經過上述步 驟製付之母-條狀半成品的橫向破裂#繼直接物理破裂 該每-半成品，即製得多數分別具有二正端雜Μ、二背 端電極33、二側面電極36、一電阻| 34，及一包括絕緣層 351與包覆層352之保護膜35的晶片電阻元件半成品單體 參閱圖5，接著進行步驟511，並配合參閱圖％、圖 ，最後自該每一晶片電阻元件半成品單體的二正、背、侧 面電極32、33、36表面依序以銅為主要材料成分、鎳為主 要材料成分、錫主要材料成分鍍覆形成二包含有第一錢層 371、第二鑛層372，及第三鑛層373的鑛膜37，即完成晶 片電阻元件3的製作。 由上述說明可知，本發明主要是以簡易的鍍覆製程， 16 1294129 分別以銅、鎳、錫為主要材料形成包含三鍍層371、372、 373的鍍膜37，而使晶片電阻元件3可以利用熔融的液態 銲錫300的内聚力直接微調後正確定位在銲墊200上，並 在銲錫300凝固時良好的與銲錫30〇銲黏成一體；同時， 藉由鍍膜37相對較薄而可以相對減少元件3至銲墊200的 電子流通路徑以及熱傳導路徑長，而使元件3具有更大功 率的應用以及在電路中提供更精確的微歐姆尺度的電阻值 ，確實可以改進美國專利第6856234B2號提出之具有辅助 填充物27的晶片電阻元件2，其製程較為複雜，且幾乎不 可能貫際實施於量產的缺點，同時也改進了其元件2因為 增加了輔助填充物27，所以相對使得電流路徑增加長，而 使得元件2散熱困難而不適用於大功率的應用，以及提供 的阻值因溫度的影響而較為不穩定的缺點，確實達到本發 明的創作目的。 惟以上所述者，僅為本發明之較佳實施例而已，當不 能以此限定本發明實施之範圍，即大凡依本發明申請:利 範圍及發明說明内容所作之簡單的等效變化與修飾7皆仍 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 圖1是-剖視圖’說明-習知的晶片電阻元件，And the side of the mother-side positive electrode 12 facing away from the other positive-end electrode and the one side 112 of the substrate 11 are coincident. The moon-shaped electrode 13 is electrically conductive and spaced apart at the back and is formed on the back. The terminal electrode 13 is relatively distant from the other-back electrode #', and coincides with: a side surface ι2 of the substrate u such that the two positive ends, ^12, the back electrode 13 are symmetrical to each other. The edge resistance layer Η has a predetermined resistance value, and is disposed on the back surface of each of the sub-regions of the two back-end electrodes 13 at each of the (four) ends of the ray: ..., and, on the opposite sides, the one-to-one 鸲 electrode 13 side region The two 1294129 terminal electrodes 13 are electrically connected to each other. The protective layer 15 is made of an insulating material, and the resistive layer 14 is coated with the resistive layer 14 to isolate the resistive layer 14 from the outside. The one side electrode 16 is formed of a material which is capable of guiding the lightning, and is formed on the two side faces 112, respectively, and is electrically connected to the same side of the mountain + 1 (four), the back end electrodes 12, 13 are in contact with each other. The two plating layers 17 are formed of tin as a main constituent material on the same side of the positive electrode 12, the side electrode 16 and the back electrode 13. The chip resistor element 1 can be used by the two back electrodes 13 and the two side electrodes 16 and the two plating layers 17 and the solder pads 3 of the solder 3 circuit board 100, and the LV layer is etched and the self-layered circuit board is used. One of the pads 200 passes through the plating layer 1 side of the wafer resistive element 1 , the back end electrode 13 , the resistive layer 14 , and the other side of the back end electrode 13 to reach a current path formed by the other pad 200 Provides a resistance value in the micro-ohmic scale of the circuit. However, since the chip resistive element i is freshly fixed on the laminated circuit board 100, the layer 15 directly contacts the laminated circuit board 1 and/or the solder pad 2GG, causing the two layers 17 to be relatively soldered. The solid solder pad is in an overhead state, which is not easy to place in the correct position corresponding to the solder pad 2 ,. At the same time, when soldering and soldering the solder 300, it often causes false soldering and causes electrical failure. See Figure 2 for details. U.S. Patent No. 6,856,234 B2, "CHIP RESISOR", proposes another chip resistor element 2 which is easily soldered and fixed on a laminated circuit board 100, and comprises a substrate 21, two positive terminal electrodes 22, two back end electrodes 23, and a resistor. The layer 24, a protective layer, two side electrodes 1294129 pole 26, two auxiliary fillers 27, and two plating layers 28. The substrate 21 is made of an insulating material and has a rectangular plate shape and has a moon surface 211 - a side surface 212 ′ extending upward from opposite sides of the back surface 211 and a front surface 213 connecting the top sides of the two side surfaces 212 . The two positive terminal electrodes 22 are electrically conductive and spaced apart from each other on the front surface 213, and each of the positive terminal electrodes 22 is opposite to a side surface 212 of the substrate 21 with respect to a side edge away from the other positive terminal electrode. The back end electrodes 23 are electrically conductive and spaced apart from each other on the back surface 211, and the side of each of the back end electrodes 23 away from the other back end electrode 23 also coincides with a side surface 212 of the substrate 21. The two positive terminal electrodes 22 and the back end electrodes 23 are symmetrical to each other. The resistive layer 24 has a predetermined resistance value, and is disposed on a region of the back surface 2ι located between the two back end electrodes 23, and opposite side portions of the opposite sides are respectively opposite to the side regions of the two back end electrodes 23. The electrodes are electrically connected to the two back electrodes 23 by lamination. The protective layer 25 is made of an insulating material, and the resistive layer 24 is shielded from the outside by correspondingly covering the resistive layer 24. The two side electrodes 26 are made of an electrically conductive material, and are formed on the two side faces 212, respectively, and are electrically connected to the front and back end electrodes 22 of the same side. The two auxiliary fillers 27 are respectively formed downward from the surface of the two back end electrodes 23 with a conductive material and have a substantially trapezoidal cross section. The two plating layers 28 are formed with the crucible as a main constituent material, and the front end electrode 22, the side surface electrode 26, and the auxiliary filler 27 are formed upward from the same side. 1294129 The above-mentioned chip resistive element 2 can be formed by the shape of the two auxiliary fillers 27, so that the cross-sectional shape of the solder layer 28 corresponding to the two back-end electrodes 23 is obliquely extended to the layer 25, and is easily positioned correspondingly to the laminated circuit board. On the tantalum pad 200, a plating layer 28 made of a tin-based material is bonded to the solder 300 in a good manner, and is soldered to the pad 200 of the laminated circuit board 1 . However, in order to form the auxiliary filler 27 having a trapezoidal shape in section of the chip resistive element 2, at least one process step is added, and the process is not formed in the S-process. The state-like auxiliary filler 27, therefore, the wafer resistor element 2 having the auxiliary filler 27 can be well positioned and soldered to the pad 200 by soldering, but it is not possible to Production on the production line. In addition, since the effect of the chip resistive elements 2 in the circuit is to provide a resistance value of a micro-ohmic scale, that is, a pad 2 (8) passes through the back end electrode 23 of the element 2 side, the resistive layer 24, to another The current path formed by the back electrode 23 on one side and reaching the other pad 2 will seriously affect the resistance value actually in the circuit; and the auxiliary filler proposed by "cmPRESIS0R" in US Pat. No. 68562/4b2 The chip resistive element 3 of 27, because of the addition of the auxiliary filler, relatively makes the resistive layer 24 farther away from the pad 2 of the laminated circuit board 1 如此, which not only increases the current path length, but also makes the chip resistor The path length of the element 2 through the heat conduction of the pad 200 is increased and the phase shape is difficult. Therefore, the power applied to the element 2 itself is not only small, but the resistance value provided is also unstable due to the influence of temperature. _ 1294129 So 'the current chip resistance component! 2 f should be improved to make it in place and well recorded on the solder pad. It can also be applied to high power applications and provide stable micro-ohmic resistance values. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a chip resistor element that is high-powered and easily positioned and soldered to a laminated circuit board. Further, another object of the present invention is to provide a method of manufacturing a chip resistor element which is high in power and easy to clamp on a laminated circuit board. The two-surface electrode is a chip resistor element comprising a substrate end electrode, two back-end electrodes, a resistive layer, a protective film, two sides, and two plating films. The substrate is insulated and plate-shaped and has a back surface, two sides extending upward from opposite sides of the surface, and a front surface connecting the top sides of the two sides. The two positive terminal electrodes are electrically conductive and spaced apart from each other on the front surface, and the side of the mother positive electrode opposite to the other positive electrode overlaps a side surface of the substrate. The two back end electrodes are electrically conductive and spaced apart on the back surface, and each of the back end electrodes is opposite to a side of the substrate opposite to the side of the other back end electrode. The resistive layer has a predetermined resistance value and is formed on a region of the back surface between the two back end electrode portions, and opposite side edge regions are respectively connected to the two back end electrode portion side regions. The protective film covers the surface of the resistive layer to insulate the resistive layer from the external phase 1294129. The two side electrodes are electrically conductive and are respectively formed on the two sides and electrically connected to the positive and back end electrodes of the same side, respectively. The two coatings are respectively formed upward from the surfaces of the positive electrode, the side electrode and the back electrode of the same side, and each coating has a copper-based component and is connected to the surface of the positive electrode, the side electrode and the back electrode. The first forged layer is a second plating layer mainly composed of nickel and connected to the surface of the first plating layer, and a third plating layer mainly composed of tin and connected to the surface of the second plating layer. Further, a method of manufacturing a chip resistor element of the present invention comprises the following steps. First, a plurality of longitudinally spaced longitudinal rupture grooves ′ and laterally spaced transverse rupture grooves are formed on the upper surface of the insulating substrate, and the two adjacent longitudinal rupture grooves and the lateral rupture grooves together define a single element region. Further, corresponding to each longitudinal rupture groove, a back electrode strip on the opposite sides of the vertical rupture groove is formed on the lower surface of the substrate by a conductive material. Then, corresponding to each of the longitudinal rupture grooves, a positive electrode strip on the opposite sides of the longitudinal rupture groove is formed on the upper surface of the substrate by a conductive material. Then, a resistive layer strip electrically connected to the two back end electrode strips on both sides is formed on a region between each of the two adjacent back end electrodes of the lower surface of the substrate by a predetermined metal material. Further, an insulating layer strip is formed on the plurality of resistive layer strips by an insulating material. Continuing to cut and modulate the geometry of the majority of the insulating strips and the resistive strips with a high energy beam corresponding to each of the component cell regions to precisely modulate the corresponding resistance of each of the elemental regions of the 10 1294129. Then, on the surface of the insulating strip of the obtained semi-finished product, a strip of the insulating layer which is insulated from the outside by the strip of the predetermined geometrical shape is formed. The successor succeeded in the production of semi-finished products along the majority of the longitudinal rupture grooves, resulting in a majority of strip-shaped semi-finished products. Then, side electrode strips respectively electrically connected to the positive and negative electrode strips are formed of a conductive material on the two fracture faces of each of the strip-shaped semi-finished products. Each of the strip-shaped semi-finished products obtained by the rupture of the majority of the transverse rupture trenches, and the semi-finished products of the wafer resistors having two positive-side electrodes, two-back electrodes, two-side electrodes, a resistive layer, and a protective film respectively monomer. Finally, the surface of the two positive, back and side electrodes of the semi-finished monomer of each of the resistor elements of the wafer is sequentially made of copper as the main material component, and the main material composition of the tin is formed. The main material composition of the tin comprises a first plating layer and a second coating layer. The plating layer and a third plating layer are coated to produce a plurality of wafer resistor elements. The effect of the invention is to further form a plating layer with copper, nickel, and the main material in a simple process, so that the component can be easily utilized by the liquid solder, and the solder is solidified. Freshly bonded and can reduce the electron flow path of the component to the solder fillet and the heat transfer path U to make the I piece have more power application and provide a more accurate micro-ohmic resistance value in the circuit. [Embodiment] Prior to the present invention, the present invention will be clearly described in the following detailed description of the preferred embodiments with reference to the accompanying drawings. 11 1294129 Before the present invention is described in detail, it is to be noted that in the following description, similar elements are denoted by the same reference numerals. Referring to FIG. 3 and FIG. 4, a preferred embodiment of the chip resistor element 3 of the present invention is easy to solder and fix on the pad 2 on the laminated circuit board and is easy to dissipate for high power applications. It comprises a substrate 31, two positive terminals 32, two back electrodes 33, a resistive layer 34, a protective film 35, a side electrode %, and a second film 37. The substrate 31 is made of an insulating material and has a rectangular plate shape and has a back surface 311, two side surfaces 312' extending upward from opposite sides of the back surface 311, and a front surface connecting the top sides of the two side surfaces 312. The two positive terminals 32 are electrically conductive, and are respectively formed on the front surface 313 at intervals in a rectangular shape, and each side of the positive electrode is relatively away from the side of the other positive electrode and a side of the substrate. 312 coincides. The two back electrodes 33 are electrically conductive, and are respectively formed on the back surface 311 at intervals in a rectangular shape, and the side of each of the back electrodes 33 is away from the other back electrode 33 and the substrate. One side surface 312 of 31 coincides such that the two positive terminal electrodes 32 and the back end electrodes 33 are symmetrical to each other. The resistor | 34 is composed of, for example, a button, chromium, nickel, aluminum, manganese, copper, silver, palladium platinum, and an alloy of such metal halogens, and has a predetermined geometrical impurity and has an accurate micro-ohmic resistance value. Formed on the back surface 311 on a region between the two back end electrodes 33, and opposite side edges thereof are respectively overlapped with the side edges of the two back end electrodes 33 and the north north end electrodes 33 Form an electrical connection. The protective film 35 {constructed by an insulating material' has a shape similar to the layer 12 of the resistor 12 1294129 and is connected to the insulating layer 5% 1 and connected to the surface of the resistive layer 34, and is coated with the insulating layer 351 The resistive layer 34 is a cladding layer 352 that is independent of the outside world. The two side electrodes 36 are respectively made of an electrically conductive material, such as silver paste, metal slab, etc., respectively formed on the two side faces 312 and respectively in contact with the positive and back end electrodes 32, 33 of the same side. Electrical connection. The edge-mine film 37 is formed upward from the side of the positive electrode, the side electrode %, and the surface of the back electrode 33, respectively, and each of the plating films 37 has a copper-based and positive-side electrode 32 and a side surface. a first plating layer 371 having an electrode % connected to the surface of the back electrode 33, a second gold layer 372 mainly composed of nickel and connected to the surface of the first plating layer 371, and a tin-based composition and a second mineral The third layer of milk is connected to the surface of the layer 372, and the thickness of the second and third layers 372, 373 is greater than the thickness of the second, third and third layers 371, 372, 373. The thickness is greater than the distance from the back surface 311 of the substrate 31 to the surface of the protective crucible 35. This month's chip resistor 70 piece 3 is soldered to the soldering pad 4 of the laminated circuit board 100, and can be directly connected to the pad by the tin outer layer with the tin as the main material f. Contact and contact with the bright tin 3 f) h, which is the same as the smelting and smelting, and automatically and correctly positioned by the cohesive force of the liquid solder 300 WSI. Goodly welded to the material; _, because the thickness of the second ore film, 37 is relatively thin, and the main components of the first and second ore layers 37 372 are respectively excellent thermal conductivity of copper and recorded, that is It is said that after the solder pad is soldered to the pad, the resistive layer 34 of the die member 3 is not only closer to the two pads, but also by a 13 1294129 I _ through the element 3 - side of the mineral film 37, the back end electrode %, the resistance layer 200 to the other side The f-terminal electrode %, the plating film 37, and the current path and the heat conduction path formed by reaching another pad are also relatively short, so it is easier to provide a relatively stable micro-resistance value, and is also suitable for high power. The wafer resistor element 3 of the present invention can be more clearly understood after passing through the process description as shown in FIG. Referring to FIG. 5, the preparation of the above-mentioned wafer resistor element 3 of the present invention is performed in step T 501. As shown in FIG. 6 and FIG. 7, a plurality of criss-crossing rupture grooves 602 are formed on the surface of an insulating substrate. The adjacent two lateral and longitudinal rupture grooves define a component cell region 6〇3; the insulating substrate 〇1 may be, for example, a glass substrate, a ceramic substrate, or an epoxy vinegar material. Preferably, the depth of the rupture grooves 〇2 is set within a few micrometers, and the predetermined semi-finished product can be physically ruptured in a subsequent process. Referring to FIG. 5', proceeding to step 502, and referring to FIG. 8 and FIG. 9, correspondingly, each longitudinal rupture groove 6〇2 is printed in a printed manner on the lower surface of the substrate 〇1 to form a corresponding correspondence in the longitudinal rupture. The back electrode strips 6〇4 on opposite sides of the groove 602. In addition, for example, the metal foil bonding method, the vacuum saving method, and the surface gold plating method are all ways of forming the back electrode strip 6〇4. Since there are many such formation methods, and the focus of the invention is not concentrated, Detailed. Referring to FIG. 5', step 503 is followed, and with reference to FIG. 1A and FIG. 5', then each longitudinal rupture groove 602 is also printed in the same manner, and the upper surface of the plate 601 is printed with the _r isoelectric material. Two positive and negative electrodes on opposite sides of the longitudinal rupture groove 602. Similarly, the manner in which the positive electrode strips 605 can be formed, such as the metal box bonding method, is the manner in which the positive electrode strips 605 can be formed. </ RTI> Since these forms are numerous, and are not the focus of the present invention, they will not be described in detail herein. Referring to FIG. 5, proceeding to step 504, and referring to FIG. 12 and FIG. 1 = subsequently printing and forming correspondingly between the two-month end electrodes # 604 of the lower surface of the substrate - both sides and two The back electrode 604 is overlapped and connected to the resistance layer strip 6〇6. Similarly, for example, the metal box fitting method, the vacuum sputtering method, and the like are all ways of forming the resistance layer strip _, because of the numerous ways of such an ancient point, the 烕 烕, and the non-inventive focus of the invention is here. Not more detailed. " Next, step 505 is performed, and an insulating layer strip 6〇7 is printed on the surface of each of the resistive layers correspondingly in the same manner as shown in Fig. 14. Referring to Figure 5, the steps are followed, and with reference to ^16, Figure X, for example, "the energy of the surface of the beam corresponds to each element cell (10) «Cut the majority of the insulation strip 6〇7 and the resistance layer strip 6 〇6 is made to have a pre-twisted geometric shape to precisely modulate the corresponding resistance value of each element cell region (10). Referring to Figure 5, step 507 is followed, and with reference to Figure μ, Figure D Then, after the surface of the finished product strip 607, which has been subjected to the above steps, is printed, a coated slave, a second-cut insulating strip 607 and a resistive strip 606 are formed to make the cut resistive strip 606 and the outside. Isolated cladding 15 1294129 layer strip 608. Referring to Figure 5, proceed with the cattle 2!, along with step 5. 7:: 5 ° 8 ' and with reference to ® 2 〇, diagram into the entanglement + finished product Most longitudinal rupture grooves 002 directly enter the physical rupture, resulting in a majority of long strips of semi-finished products. 5', then proceed to step 5〇9 23, and then prepare a main 屮σ l 阢 翏 翏 图 图 22 22 22 22 翏 翏 609 609 609 609 609 609 609 609 609 609 609 609 609 609 609 609 609 609 609 609 609 609 609 609 609 609 609 609 609 609 609 609 a side electrode strip 61 electrically connected to the positive electrode strips 605 and 604; a silver paste is applied directly to the second broken beta surface 609 of the mother half of the finished product, and the bamboo paste is applied to the bamboo shoots. The two side electrode strips 61 〇 refer to FIG. 5, and then proceed to step 51 〇, and with reference to FIG. 24 and FIG. 25 ′ after completing the side electrode strips (10) and (4), that is, the lateral direction of the mother-strip semi-finished product which is produced through the above steps. The rupture # follows the direct physical rupture of the per-semi-finished product, that is, the majority of the two-terminal heterojunction, the two-back electrode 33, the two-side electrode 36, a resistor|34, and an insulating layer 351 and a cladding layer 352, respectively. Referring to FIG. 5, the wafer resistor element semi-finished monomer of the protective film 35 is followed by step 511, and with reference to the figure %, the figure, and finally the two positive, back and side electrodes 32, 33 of the semi-finished monomer of each of the chip resistive elements. 36 surface with copper as the main material composition, nickel Main component material, the main material component of tin plating is formed with a first money two layer 371, a second ledge 372, and the third film 373 of the ore seam 37, i.e. complete crystallization of the sheet resistance of the element 3 made. It can be seen from the above description that the present invention mainly uses a simple plating process, and 16 1294129 respectively forms a plating film 37 containing three plating layers 371, 372, and 373 with copper, nickel, and tin as main materials, so that the chip resistive element 3 can be melted. The cohesive force of the liquid solder 300 is directly fine-tuned and correctly positioned on the pad 200, and is well bonded to the solder 30 when the solder 300 is solidified; at the same time, the component 3 can be relatively reduced by the relatively thin coating 37 The electron flow path of the pad 200 and the long heat transfer path, while the component 3 has a higher power application and provides a more accurate micro-ohmic resistance value in the circuit, can indeed improve the auxiliary filling proposed in US Pat. No. 6,856,234 B2. The chip resistive element 2 of the material 27 has a complicated process and is almost impossible to implement in mass production, and also improves the element 2 because the auxiliary filler 27 is added, so that the current path is increased relatively long. It makes the component 2 difficult to dissipate heat and is not suitable for high power applications, and the resistance value provided is unstable due to the influence of temperature. The shortcomings do achieve the creative purpose of the present invention. However, the above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, that is, the simple equivalent changes and modifications made by the present invention in the scope of the invention and the description of the invention. 7 is still within the scope of the invention patent. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view illustrating a conventional chip resistor element,
明其銲黏在一積層電路板的銲墊上； WMing soldering adheres to the pads of a laminated circuit board; W
圖2是一剖視圖，說明另一習知的晶片電阻 說明其鍀黏在一積層電路板的銲墊上； W 圖3是一立體圖，說明本發明一 ^種日日片電阻元件的一 17 1294129 較佳實施例； 圖4是一剖視圖，輔助說明圖3的晶片電阻元件，並 說明其銲黏在一積層電路板的銲墊上； 圖5是一流程圖，說明圖3的晶片電阻元件的製造過 程； 圖6是一立體圖，輔助說明圖5之製造流程的一步驟 501 ; 圖7是一側視圖，配合圖6輔助說明圖5之製造流程 的步驟501 ; 圖8是一立體圖，輔助說明圖5之製造流程的一步驟 502 ； 圖9是一側視圖，配合圖8辅助說明圖5之製造流程 的步驟502 ; 圖10是一立體圖，輔助說明圖5之製造流程的一步驟 503 ; 圖11是一側視圖，配合圖10輔助說明圖5之製造流程 的步驟503 ; 圖12是一立體圖，辅助說明圖5之製造流程的一步驟 504 ； 圖13是一側視圖，配合圖12輔助說明圖5之製造流 程的步驟504 ; 圖14是一立體圖，輔助說明圖5之製造流程的一步驟 505 ； 圖15是一側視圖，配合圖14辅助說明圖5之製造流 18 1294129 程的步驟505 ; 圖16是一立體圖，輔助說明圖5之製造流程的一步驟 506 ； 圖17是一側視圖，配合圖16輔助說明圖5之製造流 程的步驟506 ; 圖18是一立體圖，輔助說明圖5之製造流程的一步驟 507 ； 圖19是一侧視圖，配合圖18輔助說明圖5之製造流 程的步驟507 ; 圖20是一立體圖，輔助說明圖5之製造流程的一步驟 508 ； 圖21是一側視圖，配合圖20辅助說明圖5之製造流 程的步驟508 ; 圖22是一立體圖，輔助說明圖5之製造流程的一步驟 509 ； 圖23是一侧視圖，配合圖22輔助說明圖5之製造流 程的步驟509 ; 圖24是一立體圖，辅助說明圖5之製造流程的一步驟 510 ； 圖25是一側視圖，配合圖24輔助說明圖5之製造流 程的步驟510 ; 圖26是一立體圖，輔助說明圖5之製造流程的一步驟 511 ;及 圖27是一側視圖，配合圖26輔助說明圖5之製造流 19 1294129 程的步驟511。Figure 2 is a cross-sectional view showing another conventional wafer resistance indicating that it is adhered to a pad of a laminated circuit board; Figure 3 is a perspective view showing a 17 1294129 of a solar resistance element of the present invention. FIG. 4 is a cross-sectional view of the wafer resistor element of FIG. 3, and is illustrated as being soldered to a pad of a laminated circuit board; FIG. 5 is a flow chart illustrating the manufacturing process of the chip resistor element of FIG. Figure 6 is a perspective view, which assists in explaining a step 501 of the manufacturing flow of Figure 5; Figure 7 is a side view, with reference to Figure 6 assisting the step 501 of the manufacturing flow of Figure 5; Figure 8 is a perspective view, and Figure 5 is a supplementary view A step 502 of the manufacturing process; FIG. 9 is a side view, with reference to FIG. 8 to assist step 502 of the manufacturing process of FIG. 5; FIG. 10 is a perspective view of a step 503 of the manufacturing process of FIG. 5; FIG. FIG. 12 is a perspective view of a manufacturing process of FIG. 5, and FIG. 13 is a side view, and FIG. Manufacturing flow Figure 144 is a perspective view of a step 505 of the manufacturing flow of Figure 5; Figure 15 is a side view, with reference to Figure 14 assisting the step 505 of the manufacturing flow 18 1294129 of Figure 5; Figure 16 is A perspective view, which assists in explaining a step 506 of the manufacturing process of FIG. 5; FIG. 17 is a side view, with reference to FIG. 16, which assists in explaining step 506 of the manufacturing flow of FIG. 5; FIG. 18 is a perspective view of the manufacturing process of FIG. Figure 19 is a side view, with reference to Figure 18, which assists in explaining step 507 of the manufacturing flow of Figure 5; Figure 20 is a perspective view of a step 508 of the manufacturing flow of Figure 5; Figure 21 is a side view, FIG. 22 is a perspective view of a manufacturing process of FIG. 5, and FIG. 22 is a side view, and FIG. 23 is a side view, which is used to assist the manufacturing process of FIG. FIG. 24 is a perspective view, which is a perspective view of the manufacturing process of FIG. 5; FIG. 25 is a side view, and FIG. 24 is used to assist step 510 of the manufacturing flow of FIG. 5; FIG. A step 511 of the manufacturing flow of FIG. 5; and FIG. 27 is a side view, with reference to FIG. 26, a step 511 of the manufacturing flow 19 1294129 of FIG.
20 129412920 1294129
【主要元件符號說明】 100 積層電路板 34 電阻層 200 銲墊 35 保護膜 300 鲜錫 351 絕緣層 1 晶片電阻元件 352 包覆層 11 基材 36 側面電極 12 正端電極 37 鍍膜 13 背端電極 371 第一鍍層 14 電阻層 372 第二鍍層 15 保護層 373 第三鍍層 16 側面電極 501 步驟 2 晶片電阻元件 502 步驟 21 基材 503 步驟 22 正端電極 504 步驟 23 背端電極 505 步驟 24 電阻層 506 步驟 25 保護層 507 步驟 26 側面電極 508 步驟 27 輔助填充物 509 步驟 28 鍍層 510 步驟 3 晶片電阻元件 511 步驟 31 基材 601 基板 32 正端電極 602 破裂槽 33 背端電極 603 元件單體區 21 1294129 604 背端電極條 608 605 正端電極條 609 606 電阻層條 610 607 絕緣層條 包覆層條 破裂面 側面電極條[Main component symbol description] 100 laminated circuit board 34 resistance layer 200 pad 35 protective film 300 fresh tin 351 insulating layer 1 chip resistive element 352 cladding layer 11 substrate 36 side electrode 12 positive electrode 37 coating 13 back electrode 371 First plating layer 14 resistance layer 372 second plating layer 15 protective layer 373 third plating layer 16 side electrode 501 step 2 wafer resistive element 502 step 21 substrate 503 step 22 positive terminal electrode 504 step 23 back end electrode 505 step 24 resistance layer 506 step 25 Protective layer 507 Step 26 Side electrode 508 Step 27 Auxiliary filler 509 Step 28 Plating layer 510 Step 3 Chip resistive element 511 Step 31 Substrate 601 Substrate 32 Positive end electrode 602 Rupture groove 33 Back end electrode 603 Element cell area 21 1294129 604 Back end electrode strip 608 605 Positive end electrode strip 609 606 Resistance layer strip 610 607 Insulation layer strip coating layer rupture surface side electrode strip
22twenty two