TW200814099A - A chip resistor component and a manufacturing process thereof - Google Patents

A chip resistor component and a manufacturing process thereof Download PDF

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Publication number
TW200814099A
TW200814099A TW95133838A TW95133838A TW200814099A TW 200814099 A TW200814099 A TW 200814099A TW 95133838 A TW95133838 A TW 95133838A TW 95133838 A TW95133838 A TW 95133838A TW 200814099 A TW200814099 A TW 200814099A
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Taiwan
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layer
electrode
resistive
strip
electrodes
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TW95133838A
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Chinese (zh)
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TWI294129B (en
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Mu-Yuan Chen
Wen-Feng Wu
Chi-Pin Chang
Kao-Po Chien
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Yageo Corp
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Publication of TW200814099A publication Critical patent/TW200814099A/en

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Abstract

This invention is a chip resistor component and a manufacturing process thereof. The resistor component has a insulating substrate, two upper-electrodes forms on the up-side of the substrate, two bottom-electrodes forms on the back-side of the substrate, a resistance layer forms between the bottom-electrodes, a cover coat forms on top of resistive element, two side-electrodes formed on the sides of the substrate and electrically connects with the upper-electrodes and bottom-electrodes, and plating films forms above the surface of the upper-electrodes, bottom-electrodes, and side-electrodes, which has a Cu plating layer, Ni plating layer, and Sn plating layer.

Description

200814099 九、發明說明: ; 【發明所屬之技術領域】 本發明是有關於一種被動元件及其製造方法,特別是 指一種具有微歐姆(micro_ Q )等級阻值的晶片電阻元件及 其製造方法。 【先前技術】 參閱圖1,晶片電阻元件是一種銲黏在積層電路板1〇〇 (PCB )上的被動元件,用於提供微歐姆尺度的電阻值。該 晶片電阻元件1包含—基材u、二正端電極12、二背端電 極13、一電阻層14、一保護層15、二側面電極16,及二 鍍層17。 该基材11是以絕緣材料構成,略成矩形板狀並具有一 月面111、一分別自該背面lu的減兩側向上延伸的侧面 112,及一連接該二側面112頂邊的正面】。 '而電極12是可導電並相間隔地形成在該正面BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a passive component and a method of fabricating the same, and more particularly to a chip resistor component having a micro-ohm (micro_Q) rating and a method of fabricating the same. [Prior Art] Referring to Fig. 1, a chip resistor element is a passive component soldered to a laminated circuit board (PCB) for providing a resistance value of a micro-ohmic scale. The chip resistive element 1 comprises a substrate u, two positive terminal electrodes 12, two back end electrodes 13, a resistive layer 14, a protective layer 15, two side electrodes 16, and a second plating layer 17. The substrate 11 is made of an insulating material and has a rectangular plate shape and has a moon surface 111, a side surface 112 extending upward from the side of the back surface lu, and a front surface connecting the top sides of the two side surfaces 112. . 'And the electrodes 12 are electrically conductive and spaced apart on the front side

113上,且每—正端電極12相對遠離另—正端電極之侧邊 與該基材11的一側面112相重合 疋1V電並相間隔地形成在該背面 m上,且該每—背端電極13相對遠離另—背端電極^之 側邊亦與祕材u的―側面112彳目M, 極12、背端電極13彼此相對稱。 而電 該電阻層14具有預定的電阻值,設置在該背面⑴之 位於該二背端電極13 ^ v 間的區域上,且其相反的兩側邊部 为區域分別與該二背端雷搞 ° 3側邊區域相疊合而與該二背 200814099 端電極13形成電連接。 该保濩層15是以絕緣 使該電阻層U與外界相隔絕成’對應包覆該電阻詹Η 該二側面電極16以可導電的 側面112上並分別與同 成”狀成在- 接觸而電連接。 ]邊之该正、背端電極丨2、13相 5亥—錢^層17分別ϋί Α上 正端I*# 12 /丨 要構成材料形成在同侧邊之 而電極12、側面電極16與背端電極13上。 偏=述晶片f阻元件1確實可以藉由兩背端電極13與二 側面電極16以及二鍍® 17 ^ 亚利用銲錫300銲固在積層電 路板_輯墊2⑽上,進㈣自積層電純_之-鲜 塾=〇經過該晶片電阻元件卜側的鍍層17、背端電極η 、電阻層14、至另一侧的背端電極13,到達另一銲墊2〇〇 所形成^電流路徑提供f路中微歐姆尺度的電阻值。 但是,由於此等晶片電阻元件1在銲固於積層電路板 7上時’該保護㉟15會直接接觸到積層電路板】⑼及/或 疋鋅墊200而造成二鍍層17相對欲銲固之銲墊挪成架空 狀態’不但不易於對應銲塾· &置正嫁的位置上,同時 ’以銲錫3GG銲㈣定時也f會造成假銲而導致電性失效 〇 參閱圖2,有鑑於此,美國專利第6856234B2號「 CHIP RESISOR」提出另一種易於銲黏固定在積層電路板 100上的晶片電阻元件2,其包含一基材21、二正端電極 22、二背端電極23、一電阻層24、一保護層25、二侧面電 200814099 極26、二輔助填充物27,及二鍍層28。 b該基材21是以絕緣材料構成,略成矩形板狀並具有- 背面211、二分別自該背面211的相反兩側向上延伸的側面 212,及一連接該二侧面212頂邊的正面ZB。 該二正端電極22是可導電並相間隔地形成在該正面 213上,且每一正端電極22相對遠離另-正端電極22之側 邊與该基材21的一側面212相重合 該二背端電極23是可導電並相間隔地形成在該背面 211上’且該每一背端電極23相對遠離另一背端電極u之 側邊亦與該基材21的-側面212相重合,使得該二正端電 極22、背端電極23彼此相對稱。 該電阻層24具有預定的電阻值,設置在該背面2ιι之 位於該二背端電⑮23之間的區域上,且其相反的兩侧邊部 分區域分別與該二背端電極23側邊區域相疊合而與該二背 端電極23形成電連接。 該保護層25是以絕緣材料構成,對應包覆該電阻層μ 使該電阻層24與外界相隔絕。 該二側面電極26以可導電的材料構成,分別形成在二 側面212上並分別與同—侧邊之該正、背端電極22、23相 接觸而電連接。 該二輔助填充物27分別以導電材料自該二背端電極23 表面向下形成且截面略成梯形。 山該二鑛層28分別以錫為主要構成材料自同側邊之該正 编電極22、側面電極26與辅助填充物27表面向上形成。 200814099 上述晶片電阻元件2遽眚开餘丄 丁义隹员可错由二輔助填充物27的形 狀,使得銲層28對應該二背端電極23的截面形狀斜向保 護層25延伸’ Μ於對應定位至積層電路板謂的薛塾 200上,進而利用以錫兔主』 的材料構成的鑛層28與銲錫 300作良好的結合,而相_ _ 了許固在積層電路板100的銲墊 200 上。113, and each of the positive electrode 12 is relatively far from the other side of the positive electrode and the side surface 112 of the substrate 11 is overlapped with 疋1V and is formed on the back surface m at intervals, and the back The side electrode 13 is relatively far from the other side of the back end electrode ^ and the side surface 112 of the secret material u is M, and the pole 12 and the back end electrode 13 are symmetrical to each other. The electric resistance layer 14 has a predetermined resistance value, and is disposed on a region of the back surface (1) between the two back end electrodes 13^v, and the opposite side edges thereof are regions respectively and the second back end Lei The 3 side regions overlap to form an electrical connection with the second back 200814099 terminal electrode 13. The protective layer 15 is insulated to insulate the resistive layer U from the outside to form a corresponding contact with the resistor. The two side electrodes 16 are electrically connected to the side surface 112 and are respectively in contact with each other. Electrical connection.] The side of the positive and the back end electrode 丨 2, 13 phase 5 hai - money ^ layer 17 respectively ϋ Α 正 upper positive end I * # 12 / 丨 to form the material formed on the same side of the electrode 12, side The electrode 16 and the back electrode 13 are biased. The wafer f resistance element 1 can be soldered to the laminated circuit board by the two back electrode 13 and the two side electrodes 16 and the second plating layer. 2(10), advance (4) self-stacking electricity pure _ _ 塾 塾 = 〇 through the resistive element side of the plating layer 17, the back end electrode η, the resistance layer 14, to the other side of the back electrode 13, to another weld The current path formed by the pad 2 provides a resistance value of the micro-ohmic scale in the f-path. However, since the chip resistive element 1 is soldered to the laminated circuit board 7, the protection 3515 directly contacts the laminated circuit board. 】 (9) and / or 疋 zinc pad 200 caused by two plating layers 17 relative to the welding pad to be moved into an overhead state 'not only It is easy to match the position of the welding 塾 & & & & & & & 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊 焊Another chip resistive element 2 which is easy to be soldered and fixed on the laminated circuit board 100 comprises a substrate 21, two positive terminal electrodes 22, two back end electrodes 23, a resistive layer 24, a protective layer 25, and two Side electricity 200814099 pole 26, two auxiliary filler 27, and two plating layers 28. b. The substrate 21 is made of an insulating material, has a rectangular plate shape and has a back surface 211, two side surfaces 212 extending upward from opposite sides of the back surface 211, and a front surface ZB connecting the top sides of the two side surfaces 212. . The two positive terminal electrodes 22 are electrically conductive and spaced apart from each other on the front surface 213, and each of the positive terminal electrodes 22 is opposite to a side surface 212 of the substrate 21 with respect to a side opposite to the other positive terminal electrode 22. The two back-end electrodes 23 are electrically conductive and spaced apart from each other on the back surface 211 and the side of each of the back-end electrodes 23 relatively away from the other back-end electrode u also coincides with the side surface 212 of the substrate 21 The second positive electrode 22 and the back electrode 23 are symmetrical to each other. The resistive layer 24 has a predetermined resistance value, and is disposed on a region of the back surface 2 ι between the two back end electrodes 1523, and opposite side portions of the two sides are respectively opposite to the side regions of the two back end electrodes 23 The electrodes are electrically connected to the two back electrodes 23 by lamination. The protective layer 25 is made of an insulating material, and the resistive layer 24 is shielded from the outside by correspondingly covering the resistive layer μ. The two side electrodes 26 are made of an electrically conductive material and are formed on the two side faces 212, respectively, and are electrically connected to the positive and back end electrodes 22, 23 of the same side. The two auxiliary fillers 27 are respectively formed downward from the surface of the two back end electrodes 23 with a conductive material and have a substantially trapezoidal cross section. The second mineral layer 28 is formed of tin as a main constituent material, and the surface of the positive electrode 22, the side electrode 26 and the auxiliary filler 27 are formed upward from the same side. 200814099 The above-mentioned chip resistor element 2 can be erroneously shaped by the shape of the second auxiliary filler 27, so that the solder layer 28 corresponds to the cross-sectional shape of the second back end electrode 23 obliquely extending toward the protective layer 25. Positioned on the multilayer circuit board of the Xueyu 200, and then the mineral layer 28 made of the material of the tin rabbit main body is well combined with the solder 300, and the phase is reinforced with the solder pad 200 of the laminated circuit board 100. on.

但是,要形成此等晶片電阻元件2截面呈梯形的辅助 填充物27, -來會多增加至少一道製程步驟,二來亦益法 於實際量產製程中’完美的成形出該等成特殊形狀態樣的 輔助填充物27,因此’該具有輔助填充物27的晶片電阻元 件2雖齡結構上確實可Μ好定位灣銲们00銲固於 知墊200上’但實際上並無法於生產線上量產實施。 此外,由於此等晶片電阻元件2於電路中的功效在於 提供微歐姆尺度等級的電阻值,也就是說,由一鲜塾綱 經過元件2 一側的背端電極23、電阻層24、至另一側的背 端電極23 ’到達另-銲塾扇所形成的電流路捏相對會嚴 ㈣響實際於電路中的電阻值;而美國專利第685623^2 號「CHIP職繼」提出之具有輔助填充物27的晶片電 阻元件3,由於增加了辅助填充物27,所以相對使得電阻 層24較為遠離積層電路板刚的銲墊細,如此—來不仁 增加了電流路徑長,同時也使得晶片電阻元件2經過鲜= 200導熱的路徑長增加而相形困難,因此,元件2本身適用 的功率不但較小,同時提供❸且值㈣溫度的 不穩定。 杈兩 200814099 所以,目前的晶片電阻亓杜 以70件1、.2需要加以改善,使盆 不但亦於定位、良好地銲固在 '、 i上 同%,也可適用於 大功率應用並提供穩定的微歐姆尺度電阻值。 、 【發明内容】 因此,本發明之目的,即, P在k供一種大功率且易於定 位銲固在積層電路板上的晶片電阻元件。However, in order to form the auxiliary filler 27 having a trapezoidal cross section of the chip resistive element 2, at least one process step is added, and the second step is also to "perfectly form" the special shape in the actual mass production process. The state-like auxiliary filler 27, therefore, the wafer resistor element 2 having the auxiliary filler 27 is structurally sturdy and can be positioned to be soldered to the known mat 200, but is not actually available on the production line. Mass production implementation. In addition, since the resistance of the chip resistive element 2 in the circuit is to provide a resistance value of a micro-ohmic scale, that is, a rear end electrode 23, a resistive layer 24, and the like from one side of the element 2 The current path formed by the back electrode 23' on one side reaches the other-welding fan is relatively strict (4) to the actual resistance value in the circuit; and the US Patent No. 685623^2 "CHIP" continues to be assisted Since the wafer resistor element 3 of the filler 27 is added with the auxiliary filler 27, the resistance layer 24 is relatively thinner than the pad of the laminated circuit board, so that the current path length is increased and the chip resistance element is also made. 2 After the path length of fresh=200 heat conduction increases, the phase shape is difficult. Therefore, the power applied to the component 2 itself is not only small, but also provides the temperature and the value (4) temperature instability.杈Two 200814099 Therefore, the current wafer resistance is improved by 70 pieces, 1.2, so that the basin is not only positioned, but also welded to the same '%, ', can also be applied to high-power applications and provide Stable micro-ohm scale resistance value. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a wafer resistor element that is high-powered and easily positioned and soldered on a laminated circuit board.

另外,本發明之另一目的,即在提供一種大功率且易 於定位銲固在積層電路板上的晶片電阻元件的製造方法。 於是,本發明一種晶片電阻元件,包含一美 一 端電極、二背端電極、一電層、— " — %㉟ 保邊膜、二側面電極 ,及二鍍膜。 該基材是絕緣並成板狀,且具有一背面、二分別自該 背面的相反兩側向上延伸的側面,及一連接該二側面頂邊 的正面0 該二正端電極是可導電並相間隔地形成在該正面上, 且該每一正端電極相對遠離另一正端電極之側邊與該基材 的一側面相重合。 該二背端電極是可導電並相間隔地形成在該背面上, 且该每一背端電極相對遠離另一背端電極之侧邊與該基材 的一側面相重合。 該電阻層是具有預定的電阻值並形成在該背面之位於 該二背端電極部之間的區域上,且相反的兩側邊區域分別 與該一背端電極部侧邊區域相連接。 該保護膜對應包覆該電阻層表面使該電阻層與外界相 200814099 隔絕。 該二側面電極是可導電並 刀別形成在二侧面上且分別 與同一侧邊之該正、背端電極相電連接。 該二鍍膜分別自同侧邊之該正端電極、侧面電極 端電極表面向上形成,該每— 與該正端電極、側面電極與背端電極表面連接的第一❹ 、-以鎳為主成分並與該第一鑛層表面連接的第二鏟声: 及一以錫為主成分並與該第二鍍層表面連接的第三鍍層: 再者,本發明-種晶片電阻元件的製造方法Further, another object of the present invention is to provide a method of manufacturing a chip resistor element which is high in power and which is easy to be soldered to a laminated circuit board. Thus, a chip resistor element of the present invention comprises a US end electrode, a second back electrode, an electrical layer, a """"""" The substrate is insulated and formed into a plate shape, and has a back surface, two sides extending upward from opposite sides of the back surface, and a front surface connecting the top sides of the two sides. The two positive electrodes are electrically conductive and phased. The front surface is formed on the front surface at intervals, and each of the positive terminal electrodes is opposite to a side of the substrate opposite to the side of the other positive electrode. The two back end electrodes are electrically conductive and spaced apart on the back surface, and each of the back end electrodes is opposite to a side of the substrate opposite to the side of the other back end electrode. The resistive layer has a predetermined resistance value and is formed on a region of the back surface between the two back electrode portions, and opposite side edge regions are respectively connected to the back electrode portion side region. The protective film covers the surface of the resistive layer to isolate the resistive layer from the external phase 200814099. The two side electrodes are electrically conductive and are formed on the two sides and electrically connected to the positive and back end electrodes of the same side, respectively. The two coatings are respectively formed upward from the front side electrode and the side electrode end electrode surface of the same side, and each of the first ❹ and - the main electrode, the side electrode and the back end electrode surface are connected with nickel as a main component And a second shovel sound connected to the surface of the first ore layer: and a third plating layer mainly composed of tin and connected to the surface of the second plating layer: Furthermore, the invention provides a method for manufacturing a chip resistive element

下步驟。 s M 先在一絕緣基板的上表面形成多數縱向間隔排列的縱 破裂槽,及橫向間隔排列的橫破裂溝,該二相鄰的縱破裂 槽與橫破裂溝共同定義出一元件單體區。 乂 _再對應每一縱破裂槽在該基板下表面以導電㈣形成 一位於該縱破裂槽相反兩側的背端電極條。 、一然後對應每—縱破裂槽在該基板上表面以導電材料形 成一位於該縱破裂槽相反兩側的正端電極條。 、接=在該基板下表面之每二相鄰之背端電極間的區域 上以預定金屬材料形成一兩侧部分別與該二背端電極 連接的電阻層條。 ' 再在該多數電阻層條上以絕緣材料分別形成一絕緣声 條。 曰 ^户繼續以高能量射束對應每一元件單體區精確切割調變 該多數絕緣層條與電阻層條的幾何形狀,以精確調變該每 10 200814099 一元件單體區的對應阻值。 然後再在製得之半成品的絕緣層條表面形成一使該具 有預定,何形狀之電阻層條與外界隔絕的包覆層條。 接著繼續沿該多數縱破裂槽破裂製得之半成品 多數條狀半成品。 、然後於該每-條狀半成品的二破裂面以導電材料形成 /刀別與該正、背端電極條電連接的側面電極條。 再沿該多數橫破裂溝破裂製得之每一條狀半成品,得 f多數分別具有二正端電極、二f端電極、二側面電極、 一電阻層’及—保護膜的晶片電阻元件半成品單體。Next step. s M firstly forms a plurality of longitudinally spaced longitudinal rupture grooves and laterally spaced transverse rupture grooves on the upper surface of the insulating substrate, and the two adjacent longitudinal rupture grooves and the transverse rupture grooves together define a component cell region.乂 _ further corresponding to each of the longitudinal rupture grooves on the lower surface of the substrate to electrically (four) form a back electrode strip on opposite sides of the longitudinal rupture groove. And then, corresponding to each of the longitudinal rupture grooves, a positive electrode strip on the opposite sides of the longitudinal rupture groove is formed on the upper surface of the substrate by a conductive material. And connecting a resistive layer strip respectively connected to the two back end electrodes on a side of each of the two adjacent back end electrodes of the lower surface of the substrate by a predetermined metal material. Further, an insulating sound bar is formed on the plurality of resistive layer strips by an insulating material.曰 户 继续 继续 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户 户. Then, on the surface of the insulating strip of the semi-finished product, a strip of the strip having the predetermined shape and shape of the resistive strip is isolated from the outside. Then continue to produce a semi-finished product of a plurality of strip-shaped semi-finished products along the majority of the longitudinal rupture grooves. Then, a side electrode strip electrically connected to the positive and negative electrode strips is formed by a conductive material on the two fracture faces of the strip-shaped semi-finished product. Then, along each of the strip-shaped semi-finished products obtained by rupturing the majority of the transverse rupture grooves, a plurality of wafer resistor element semi-finished monomers having two positive-end electrodes, two-f-terminal electrodes, two-side electrodes, a resistive layer and a protective film are respectively obtained. .

最後自該每-晶片電阻元件半成品單體的二正、背、 側面電極表面依序以銅為主要材料成分、鎳為主要材料成 分、錫主要材料成分形成二包含有—第—鍍層、—第二鑛 層’及-第三鍍層的鍍膜,製得多數晶片電阻元件。 λ 本發明的功效在於更進一步以簡易的製程以鋼、錄、 錫為主要材料形成鍍層’而使元件簡易地利用液態鋅錫正 確定位在料上,並在銲駿㈣良好的與銲錫鐸黏成一 體;並可以相對減少元件至銲墊的電子流通路徑以及熱傳 導路徑長’而使元件具有更大功率的應用以及在電路中提 供更精確的微歐姆尺度的電阻值。 【實施方式】 有關本發明之前述及其他技術内容、特點與功效,在 以下配合參考圖式之一個較佳實施例的詳細說明中,將可 清楚的呈現。 ' 200814099 在本發明被詳細描述之前,要注意的是,在以下的說 明内容中,類似的元件是以相同的編號來表示。 參閱圖3、圖4,本發明一種晶片電阻元件3的一較佳 實施例’是易於銲黏固定在積層電路板1〇〇上的銲塾2〇〇 上’並易於散熱而適用於大功率應用,其包含一基材31、 二正端電極32、二背端電極33、一電阻層34、一保護膜 35、二側面電極36,及二鐘膜37。 该基材31是以絕緣材料構成,略成矩形板狀並具有一 月面311、二分別自該背面311的相反兩側向上延伸的侧面 312 ’及一連接該二側面312頂邊的正面。 該二正端電極32是可導電,並分別成長矩形態樣相間 隔地形成在該正面313上,且每一正端電極相對遠離另一 正端電極之側邊與該基材的一侧面相312重合。 该二背端電極33是可導電,並分別成長矩形態樣相間 隔地形成在該背面311上,且該每一背端電極幻相對遠離 另一背端電極33之侧邊亦與該基材31的一側面312相重 合,使得該二正端電極32、背端電極33彼此相對稱。 該電阻層34是以例如鈕、鉻、鎳、鋁、錳、銅、銀、 =顧&此等金屬兀素之合金構成,並具有預定的幾何 態樣而具有精確的微歐姆尺度電阻i,形成在該背Φ 311之 位於該二背端電極33之間的區域上,且其相反的兩側邊部 分區域分別與該二背端電極33侧邊區域相疊合而與該二北 端電極33形成電連接。 月 該保護膜35是以絕緣材料構成,具有_形狀與該電阻 12 200814099 層34相似並與連接在該電阻層34表面的絕.)表層35ι,及— 連接在該絕緣層351上並包覆該電阻層%是其與外界相隔 絕的包覆層352。 项 該二侧面電極%分別以可導電的材料,例如銀膏、金 屬箱..等構成’分別形成在二側面312上並分別與同一側邊 之該正、背端電極32、33相接觸而電連接。Finally, the surface of the two positive, back and side electrodes of the semi-finished monomer of the per-wafer resistive element is mainly composed of copper as the main material component, nickel as the main material component, and the main material component of tin is formed to include the first-plated layer, the first The coating of the second ore layer and the third plating layer produces a plurality of chip resistive elements. λ The effect of the invention lies in that the plating layer is formed by using steel, recording and tin as main materials in a simple process, and the components are easily positioned on the material by using liquid zinc tin, and the solder is bonded to the solder. Integral; and can reduce the electron flow path of the component to the pad and the length of the thermal conduction path to make the component more powerful and provide a more accurate micro-ohmic resistance value in the circuit. The above and other technical contents, features, and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments. Before the present invention is described in detail, it is to be noted that in the following description, similar elements are denoted by the same reference numerals. Referring to FIG. 3 and FIG. 4, a preferred embodiment of a chip resistor element 3 of the present invention is easy to solder and fix on the soldering pad 2 on the laminated circuit board 1 and is easy to dissipate heat and is suitable for high power. The application comprises a substrate 31, two positive terminals 32, two back electrodes 33, a resistive layer 34, a protective film 35, two side electrodes 36, and a second film 37. The substrate 31 is made of an insulating material and has a rectangular plate shape and has a moon surface 311, two side surfaces 312' extending upward from opposite sides of the back surface 311, and a front surface connecting the top sides of the two side surfaces 312. The two positive terminals 32 are electrically conductive, and are respectively formed on the front surface 313 at intervals in a rectangular shape, and each side of the positive electrode is relatively away from the side of the other positive electrode and a side of the substrate. 312 coincides. The two back electrodes 33 are electrically conductive, and are respectively formed on the back surface 311 at intervals in a rectangular shape, and each of the back electrodes is opposite to the side of the other back electrode 33 and the substrate. One side surface 312 of 31 coincides such that the two positive terminal electrodes 32 and the back end electrodes 33 are symmetrical to each other. The resistive layer 34 is composed of an alloy of, for example, a button, chrome, nickel, aluminum, manganese, copper, silver, and metal bismuth, and has a predetermined geometrical state and has an accurate micro-ohmic scale resistance i Formed on a region of the back Φ 311 between the two back end electrodes 33, and opposite side portions of the two sides are respectively overlapped with the side regions of the two back end electrodes 33 and the north end electrodes 33 forms an electrical connection. The protective film 35 is made of an insulating material, has a shape similar to the layer 12 of the resistor 12 200814099 and is connected to the surface layer 35 of the surface of the resistor layer 34, and is bonded to the insulating layer 351 and coated. The resistive layer % is a cladding layer 352 that is isolated from the outside. The two side electrode % are respectively formed by electrically conductive materials such as silver paste, metal box, etc., respectively, formed on the two side faces 312 and respectively contacting the positive and back end electrodes 32, 33 of the same side. Electrical connection.

該二鑛膜37分別自同側邊之該正端電極32、側面電極 36與背端電極33表面向上形成,且每—錄膜π具有一以 銅為主成分並與該正端電極32、侧面電極%與背端電極 33表面連接的第一鍍層371、一以錄為主成分並與該第— 鐘層371表面連接的第二鍵層372,及—以錫為主成分並盘 該第二㈣372表面連接的第三錢層373,且該第一❹ :二的厚度大於該第二、三鍍層372、373的厚度和,同時 §亥弟^、二、三鍍層371、372、373的厚度和大於該基材 31背面311至該保護膜35表面的距離。 $本發明之晶片電阻元件3在銲固於積層電路板1〇〇的 I干墊200上的過程中’可藉由該二鍍膜37最外層以錫為主 要材料的第三鍍層373直接與銲墊細接觸,並在接觸到 成溶融狀態的銲錫_同時料,而藉著成液態之銲錫· 欲凝固的内聚力而自動正確定位,而待㈣3⑻凝固時即 可正石t且輝形良好地銲固在銲塾期同時,由於該二 鑛膜37的厚度相對極薄,且第―、二鑛層μ、仍的主 要成分分別是導熱性極佳的鋼與鎳,也就是說㈣在銲墊 2〇〇之後几件3的電阻層34不但較接近二銲墊,由一 13 200814099 鲜塾2〇0經過元件3 —侧的鑛膜37、背端電極33、電阻層 34至另一側的背端電極%、鐘膜π,而到達另一焊塾 斤开/成的路;^與導熱路徑也相對較短,因此較易於 散熱而可提供較穩定的微電阻值,同時,也適用於大功率 的應用。 、 “上述本毛明曰曰片電阻元件3在經過如圖5所示的製程 說明後,當可更加清楚的明白。 >閱® 5 ’ f備上述本發明晶片電阻元件3是先進行步 ΓΓ’如圖6、胃7所示地在一絕緣基板謝上表面形成 二數縱横交錯而成棋盤狀的破裂槽602,並由該相鄰的兩橫 向與縱向的«槽6G2定義出—元件單體區6()3;該絕緣基 A㈣1可以疋例如玻璃基板、陶^基板,或是以環氧樹酉旨 t料所構成的基板,較佳地,該等破㈣6G2的深度設 微米之内’而可於後續的製程中以物理方式破裂取 仔預定的半成品。 、多1圖5接著進行步驟502,並配合參閱圖8、圖9 矣以印刷方式對應每—縱向的破裂槽602在該基板6〇1下 ^面以導電材料印刷形成二對應位於該縱向破裂槽6〇2相 2側的^電極條_。此外,例如金屬H貼合方式、真 工濺錢方式、表面妙入 ’、 ^ 鍍至方式都是可以成形背端電極條604 的万式,由於此等形忐 成方式眾多,且非本發明創作重點所 在,在此不多加詳述。 閱圖5,接著進行步驟503,並配合參閱目 著同樣以印刷方式對應每-縱向的破裂槽602在該基 14 200814099 板601上表面以導電材料印刷形成二位於該縱向v破裂槽6〇2 相反兩侧邊的正端電極條6〇5。類似地,例如金屬箔貼合方 式、真空錢鑛方式等方式都是可以成形正端電極條6〇5的 方式,由於此等形成方式眾多,且非本發明創作重點所在 ,在此不多加詳述。 參閱圖5,接著進行步驟504,並配合參閱圖12、圖 13,接著同樣以印刷方式對應地在該基板6〇ι下表面之兩The second ore film 37 is formed upward from the surface of the positive electrode 32, the side electrode 36 and the back electrode 33 on the same side, and each film π has a copper-based component and the positive electrode 32, a first plating layer 371 having a side electrode % connected to the surface of the back end electrode 33, a second key layer 372 which is recorded as a main component and connected to the surface of the clock layer 371, and a tin-based composition a second (four) 372 surface-connected third money layer 373, and the thickness of the first ❹:2 is greater than the thickness of the second and third plating layers 372, 373, and §Hai, ^, and III plating 371, 372, 373 The thickness is greater than the distance from the back surface 311 of the substrate 31 to the surface of the protective film 35. The wafer resistive element 3 of the present invention is directly soldered to the third plating layer 373 which is tin-based as the outermost layer of the second plating film 37 during soldering to the I dry pad 200 of the laminated circuit board 1 The pad is in fine contact and is in contact with the molten solder in the molten state, and is automatically positioned correctly by the liquid-forming solder and the cohesive force to be solidified, and when the (4) 3 (8) is solidified, the normal stone t and the good shape can be welded. At the same time, the thickness of the second ore film 37 is relatively thin, and the main components of the first and second ore layers are still steel and nickel with excellent thermal conductivity, that is, (4) in the pad. After 2 几, a few 3 resistor layers 34 are not only closer to the two pads, but also pass through a 13 200814099 fresh 塾 2 〇 0 through the element 3 - side of the mineral film 37 , the back end electrode 33 , the resistance layer 34 to the other side The back electrode%, the clock film π, and the other soldering 塾 开 / 成 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ High power applications. "The above-mentioned embossed sheet resistor element 3 can be more clearly understood after passing through the process description as shown in Fig. 5. > READ® 5' f prepared above the wafer resistor element 3 of the present invention is a step ΓΓ', as shown in Fig. 6, the stomach 7 is formed on a surface of an insulating substrate to form a plurality of criss-crossing craters 602, which are defined by the adjacent two lateral and longitudinal «grooves 6G2. The monomer region 6 () 3; the insulating substrate A (four) 1 may be, for example, a glass substrate, a ceramic substrate, or a substrate composed of an epoxy resin, preferably, the depth of the broken (four) 6G2 is set to be micrometer. In the subsequent process, the predetermined semi-finished product can be physically ruptured in the subsequent process. More than FIG. 5 is followed by step 502, and corresponding to FIG. 8 and FIG. 9 矣 corresponds to each longitudinal rupture groove 602 in a printing manner. The substrate 6〇1 is printed with a conductive material to form two electrode strips corresponding to the phase 2 of the longitudinal rupture groove 6〇2. Further, for example, a metal H bonding method, a real money splashing method, and a surface fascination ', ^ plating method is a type that can form the back electrode strip 604. Since there are many ways of forming such a shape, and it is not the focus of the present invention, it will not be described in detail here. Referring to Figure 5, step 503 is followed, and the rupture groove 602 corresponding to each longitudinal direction is also printed in the same manner as the reference. The upper surface of the base 14 200814099 board 601 is printed with a conductive material to form two positive electrode strips 6〇5 on opposite sides of the longitudinal v-breaking groove 6〇2. Similarly, for example, a metal foil bonding method, a vacuum money mine The manners and the like are all ways of forming the positive electrode strips 6〇5, and since these forms are numerous, and are not the focus of the present invention, they will not be described in detail here. Referring to FIG. 5, step 504 is followed and cooperated. Referring to FIG. 12 and FIG. 13 , the two surfaces of the substrate 6 〇 ι are correspondingly printed in the same manner.

月鈿私極條604之間印刷形成一兩側邊分別與兩背端電極 604條重疊而連接的電阻層條6〇6。類似地,例如金屬羯貼 合方式、真空濺鐵方式等方式都是可以成形電阻層條_ 的方式’由於此等形成方式眾多,且非本發明創作重點所 在,在此不多加詳述。 多閱圖5接著進行步驟5〇5,並配合參閱圖14、圖 接著同樣以印刷方式對應地在該每一電阻層條嶋表 面印刷形成一絕緣層條607。 ,閱圖5’接著進行步驟應,並配合參閱_ Μ、圖 Η然後以例如鐳射之高能量射束對應每—元件單體區603 精確切割該多數絕緣層條6〇7與電阻層條_ 定的精確幾何形狀,_確 ^有預 對應電阻值。 《乂母&件早體區603的 19接^ 者進行步驟5〇7’並配合參_ 18、圖 ’接者在經過上述步驟製得之半成品經 芦 條6〇7表面印刷形成一包覆經過切割之絕緣層條咖= 阻層條6〇6而使㈣後之電阻㈣_與外界隔絕的包覆 15 200814099 層條608。 t 21翏閱圖5,接著進行步驟508,並配合參閱圖2〇、圖 I1:卿507製得之半成品的多數縱向破裂槽6〇2直接 進行物理破裂,而得到多數長條狀的半成品。 參閱圖广接著進行步驟5G9,並配合參_ U、圖 別與::::2成品的二破裂® 609以導電材料形成分 一'母一、品條上的二正、背端電極條605、604電連 的側面電極條_;在本例中,是直接在每_半成品的二 皮^面_上塗覆銀膏,待其乾燥即成該二侧面電極條_ 〇 參閱圖5,接著進行步驟51〇,並配合參閱W 24、圖 1在完錢面電極條⑽的㈣後,即沿著經過上述步 ^得之每—條狀半成品的橫向破㈣602直接物理破裂 忒每半成时’即製得多數分別具有二正端電極μ、二北 端電極33、二側面雷托^ ^ ^ 一月 , 電極36、-電阻層34,及-包括絕緣層 1與包覆層352之保護膜35的晶片電阻元件半成品單體 〇 η參閱圖5,接著進行步驟511,並配合參閱圖26、圖27 ’最後自該每-晶片電阻元件半成品單體的二正、背、側 面電極32 33、36表面依序以銅為主要材料成分、錄為主 要材㈣分、錫主要材料成分鍍覆形成二包含有第-錢層 371、第二錄層372,及第三鐘層373的鍍膜37,即完成: 片電阻元件3的製作。 日曰 由上述°兄明可知,本發明主要是以簡易的鍍覆製程, 16 200814099 」、銅錄、錫為主要材料形成包含三鍍層371、372、 3曰73的鑛膜37,而使晶片電阻元件3可以利射容融的液態 〇的内♦力直接微調後正確定位在銲墊2⑽上,並 在銲錫300凝固時良好的與銲錫3〇〇銲黏成一體;同時, 藉由鑛膜37相對較薄而可以相對減少元件3至銲墊200的 電子流通路徑以及熱傳導路徑長,而使元# 3具有更大功 率勺應用以及在電路中提供更精確的微歐姆尺度的電阻值 貝可以改進美國專利第6856234B2號提出之具有辅助 填充^ 27的晶片電阻元件2 ’其製程較為複雜,且幾乎不 可能實際實施於量產的缺點,同時也改進了其元件2因為 增力:了輔助填充物27,所以相對使得電流路徑增加長,而 吏知元件2政熱困難而不適用於大功率的應用,以及提供 的阻值因溫度的影響而較為不穩^的缺點,確實達到本發 明的創作目的。 ▲淮以上所述者,僅為本發明之較佳實施例而已,當不 :以此限定本發明實施之範圍,即大凡依本發明申請:利 乾圍及發明說明内容所作之簡單的等效變化與修飾,皆仍 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 $ 1是-剖視圖’說明一習知的晶片電阻元件,並說 明其銲黏在一積層電路板的銲墊上; 士圖2是一剖視圖,說明另一習知的晶片電阻元件,並 說明其銲黏在一積層電路板的銲墊上; 圖3是-立體圖,說明本發明一種晶片電阻元件的一 17 200814099 較佳實施例; 圖4是一剖視圖 。兒明其鲜黏在一積層電 圖5是一流程圖 程; 輔助說明圖3的晶片電阻元件,並 路板的銲墊上; ’說明圖3的晶片翁 一 片電阻兀件的製造過 圖 501 ; 是一立體圖,辅助說明圖 5之製造流程的一步驟The resistive strips 6〇6 are formed by printing between the moons and the private strips 604, and the two sides are overlapped with the two back electrodes 604. Similarly, the manner in which the metal ruthenium bonding method, the vacuum splattering method, and the like are all possible to form the resistive layer strip _ is complicated by the manner in which these forms are formed, and will not be described in detail herein. Referring to Figure 5, the steps 5〇5 are followed, and an insulating layer strip 607 is printed on each of the strips of the resistive layer in a manner similar to that of Fig. 14 and Fig. 14 . 5) Next, the steps should be followed, and with reference to _ Μ, Η, and then, for example, a high-energy beam of laser corresponding to each of the element cell regions 603, the majority of the insulating layer strips 6〇7 and the resistive layer strips are accurately cut_ The precise geometry of the set, _ sure ^ has a pre-corresponding resistance value. The 19th member of the 乂 mother & early body area 603 performs step 5〇7' and cooperates with the reference _ 18, and the splicer of the semi-finished product obtained through the above steps is printed on the surface of the reed strip 6〇7 to form a package. Covering the insulating layer of the bar = the barrier layer 6〇6 and the resistance after the (4) (4)_enclosed cladding 15 200814099 layer strip 608. Referring to Fig. 5, step 508 is followed, and the majority of the longitudinal rupture grooves 6〇2 of the semi-finished product obtained by the 507 is directly physically ruptured with reference to Fig. 2, Fig. I1: a plurality of long semi-finished products. Referring to the figure, the process proceeds to step 5G9, and the second rupture® 609 of the finished product is formed with a conductive material to form a two-positive, back-end electrode strip 605 on the strip. 604 electrically connected side electrode strips _; in this example, the silver paste is applied directly to the bismuth surface of each _ semi-finished product, and is dried to form the two side electrode strips _ 〇 see FIG. 5, followed by Step 51 〇, and with reference to W 24, Figure 1 after the (4) of the surface electrode strip (10), that is, along the transverse step of each of the strip-shaped semi-finished products obtained through the above steps (four) 602 direct physical rupture 忒 each half-time' That is, the majority of the plurality of positive-electrode electrodes μ, the two-north-end electrode 33, the two-side retort y ^ ^ ^ , the electrode 36 , the resistive layer 34 , and the protective film 35 including the insulating layer 1 and the cladding layer 352 are respectively formed. The chip resistive element semi-finished monomer 〇n is shown in FIG. 5, and then step 511 is performed, and referring to FIG. 26 and FIG. 27 'finally, the two positive, back and side electrodes 32 33, 36 of the semi-finished monomer of the per-wafer resistive element. The surface is sequentially composed of copper as the main material component, recorded as the main material (four), and the main material composition of tin is plated. Is formed with two - of money layer 371, 372, and coating the second layer of the third recording layer 373 of the bell 37, i.e., complete: making the sheet resistance of the element 3. According to the above-mentioned brothers, the present invention mainly uses a simple plating process, 16 200814099 ”, copper recording, tin as a main material to form a mineral film 37 containing three plating layers 371, 372, 3曰73, and the wafer is made. The resistive element 3 can be directly adjusted on the pad 2 (10) after being directly fine-tuned by the inner force of the liquid helium, and is well bonded to the solder 3 when the solder 300 is solidified; at the same time, by the mineral film The relatively thin 37 can relatively reduce the electron flow path of the component 3 to the pad 200 and the long heat conduction path, so that the #3 has a higher power scoop application and provides a more accurate micro-ohmic scale resistance value in the circuit. The improved wafer resistive element 2 with auxiliary filling 27 proposed in U.S. Patent No. 6,856,234 B2 has a complicated process and is almost impossible to actually implement in mass production, and also improves its component 2 because of the boosting force: auxiliary filling 27, so the relative current path is increased, and the component 2 is difficult to apply to high-power applications, and the resistance provided is less stable due to the influence of temperature. Point, indeed achieve the creative purpose of the present invention. The above description of the present invention is only a preferred embodiment of the present invention, and does not: limit the scope of the practice of the present invention, that is, the simple equivalent of the application of the present invention: Li Ganwei and the description of the invention Variations and modifications are still within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS [1] is a cross-sectional view illustrating a conventional chip resistor component and illustrating its soldering on a pad of a laminated circuit board; Figure 2 is a cross-sectional view showing another conventional chip resistor FIG. 3 is a perspective view showing a preferred embodiment of a wafer resistor element of the present invention; FIG. 4 is a cross-sectional view. It is clear that it is freshly adhered to a laminated electric circuit. 5 is a flow chart; the description of the chip resistive component of FIG. 3 is applied to the pad of the circuit board; 'illustrating the fabrication of the chip of the chip of FIG. 3 is shown in FIG. 501; Is a perspective view that assists in explaining a step in the manufacturing process of Figure 5.

圖7是一侧視圖 的步驟501 ; 圖8是一立體圖 502 ; 配合圖6輔助說明圖5之製造流程 輔助說明圖5之製造流程的—步驟 圖9是一側視圖,配合圖8輔助說明圖5之製造流程 的步驟502 ; 圖10是一立體圖,辅助說明圖5之製造流程的—步驟 503 ;Figure 7 is a side view of the step 501; Figure 8 is a perspective view 502; with the accompanying Figure 6 to assist the description of the manufacturing process of Figure 5 to assist in the description of the manufacturing process of Figure 5 - steps Figure 9 is a side view, with the Figure 8 auxiliary explanatory diagram Step 502 of the manufacturing process of FIG. 5; FIG. 10 is a perspective view, which assists in explaining the manufacturing process of FIG. 5 - step 503;

圖11是一側視圖,配合圖10輔助說明圖5之製造流程 的步驟503 ; 圖12是一立體圖,辅助說明圖s之製造流程的一步驟 504 ; 圖13是一側視圖,配合圖12辅助說明圖5之製造流 程的步驟504 ; 圖14是一立體圖,輔助說明圖5之製造流程的一步驟 505 ; " 圖15是一側視圖,配合圖14辅助說明圖5之製造流 18 200814099 程的步驟505 ; ’ 圖16是一立體圖,辅助說明圖5之製造流程的一步驟 506 ; 圖17是一侧視圖,配合圖16辅助說明圖5之製造流 程的步驟506 ; 圖18是一立體圖,辅助說明圖5之製造流程的一步驟 507 ; 圖19是一侧視圖,配合圖18輔助說明圖5之製造流 程的步驟507 ; 508 ; 圖20是一立體圖,輔助說明圖5之製造流程的一步驟Figure 11 is a side view, with reference to Figure 10, which assists in explaining step 503 of the manufacturing flow of Figure 5; Figure 12 is a perspective view of a step 504 of the manufacturing process of Figure s; Figure 13 is a side view, with the assistance of Figure 12 FIG. 14 is a perspective view, which is a perspective view of a manufacturing process of FIG. 5; FIG. 15 is a side view, and FIG. 14 is a supplementary view of the manufacturing flow 18 of FIG. Step 505; 'FIG. 16 is a perspective view, which assists in explaining a step 506 of the manufacturing flow of FIG. 5; FIG. 17 is a side view, with reference to FIG. 16 to assist step 506 of the manufacturing flow of FIG. 5; FIG. 18 is a perspective view. A step 507 of the manufacturing process of FIG. 5 is assisted; FIG. 19 is a side view, with reference to FIG. 18, which assists in explaining step 507 of the manufacturing flow of FIG. 5; 508; FIG. 20 is a perspective view, which assists in explaining one of the manufacturing processes of FIG. step

圖21是一側視圖,配合圖2〇輔助說明圖5之製造流 程的步驟508 ; ;,L 509 ; 圖22是一立體圖,辅助說明圖 5之製造流程的一步驟 圖23是一侧視圖, 矛呈的步驟509 ; 圖24是一立體圖, 510 ; 圖25是一側視圖, 矛呈的步驟510 ; 配合圖22辅助說明圖 5之製造流 輔助說明圖5之製造流程的—步驟 配合圖24輔助說明圖5 之製造流 圖26是一立體圖,輔助說明圖5 之製造流程的 步驟Figure 21 is a side view, with reference to Figure 2, which assists in explaining step 508 of the manufacturing flow of Figure 5; ;, L 509; Figure 22 is a perspective view, which is a step-by-step illustration of the manufacturing flow of Figure 5, Figure 23 is a side view, Step 509; Fig. 24 is a perspective view, 510; Fig. 25 is a side view, step 510 of the spear; and Fig. 22 is used to assist the manufacturing flow of Fig. 5 to explain the manufacturing process of Fig. 5 EMBODIMENT DESCRIPTION The manufacturing flow diagram 26 of Figure 5 is a perspective view that assists in the steps of the manufacturing process of Figure 5.

26輔助說明圖5 之製造流 19 511 ; 200814099 程的步驟511。26 Auxiliary description of the manufacturing flow of Figure 5, 19 511; step 511 of 200814099.

20 20081409920 200814099

【主要元件符號說明】 100 積層電路板 34 電阻層 200 鲜塾 35 保護膜 300 鲜錫 351 絕緣層 1 晶片電阻元件 352 包覆層 11 基材 36 侧面電極 12 正端電極 37 鍍膜 13 背端電極 371 第一鑛層 14 電阻層 372 第二鍍層 15 保護層 373 第三鍍層 16 側面電極 501 步驟 2 晶片電阻元件 502 步驟 21 基材 503 步驟 22 正端電極 504 步驟 23 背端電極 505 步驟 24 電阻層 506 步驟 25 保護層 507 步驟 26 側面電極 . 508 步驟 27 輔助填充物 509 步驟 28 鑛層 510 步驟 3 晶片電阻元件 511 步驟 31 基材 601 基板 32 正端電極 602 破裂槽 33 背端電極 603 元件單體區 21 200814099 604 背端電極條 608 包覆層條 605 正端電極條 609 破裂面 606 電阻層條 610 侧面電極條 607 絕緣層條 22[Main component symbol description] 100 laminated circuit board 34 resistance layer 200 fresh 塾 35 protective film 300 fresh tin 351 insulating layer 1 chip resistive element 352 cladding layer 11 substrate 36 side electrode 12 positive electrode 37 coating 13 back electrode 371 First ore layer 14 resistive layer 372 second plating layer 15 protective layer 373 third plating layer 16 side electrode 501 step 2 chip resistive element 502 step 21 substrate 503 step 22 positive terminal electrode 504 step 23 back end electrode 505 step 24 resistive layer 506 Step 25 Protective layer 507 Step 26 Side electrode. 508 Step 27 Auxiliary filler 509 Step 28 Mineral layer 510 Step 3 Chip resistive element 511 Step 31 Substrate 601 Substrate 32 Positive terminal electrode 602 Rupture groove 33 Back end electrode 603 Element cell area 21 200814099 604 Back end electrode strip 608 Cladding strip 605 Positive end electrode strip 609 Rupture surface 606 Resistance layer strip 610 Side electrode strip 607 Insulation strip 22

Claims (1)

200814099 十、申請專利範圍··’ 1 · 一種晶片電阻元件,包含: 基材,是絕緣並成板狀,且具有一背面、二分別 自該背面的相反兩側向上延伸的側面,及—連接該二侧 面頂邊的正面; -正端電極’是可導電並相間隔地形成在該正面上200814099 X. Patent Application Scope·· 1 · A chip resistor component, comprising: a substrate, insulated and plate-shaped, having a back surface and two sides extending upward from opposite sides of the back surface, and - connecting a front side of the top side of the two sides; - a positive terminal electrode 'is electrically conductive and spaced apart on the front side ,且該每-正端電極相對遠離另—正端電極之侧邊與該 基材的一側面相重合; 二背端電極’是可導電並相間隔地形成在該背面上 ,且該每-㈣電極相對遠離另—f端電極 基材的一側面相重合; ^ :電阻層,是具有預定之微歐姆尺度的阻值並形成 在'月面之位於該二背端電極部之間的區域,且相反的 兩側达區域为別與該二背端電極部側邊區域相連接; …-保護膜,對應包覆該電阻層表面使其與外界相隔And the side of each of the positive-side electrodes is opposite to the side of the substrate, and the side of the substrate is electrically conductive and spaced apart on the back surface, and each of the (4) the electrode is relatively distant from one side of the other-f-terminal electrode substrate; ^: the resistive layer is a resistance having a predetermined micro-ohmic scale and is formed on the region of the lunar surface between the two back-end electrode portions And the opposite side regions are not connected to the side regions of the two back electrode portions; ...-protective film corresponding to the surface of the resistive layer to be separated from the outside 二侧面電極,是可導電並分別形成在二側面上且分 別/、同一側邊之該正、背端電極相電連接;及 背端:=,分別自同側邊之該正端電極、側面電極與 :::表面向上形成,該每-鑛膜具有-以銅為主成 ::人該正端電極、側面電極與背端電極表面連接的第 鍍層、一以鎳為主成分並與 n订 茨弟鍍層表面連接的第 又_ 及一以錫為主成分並盘該第 第三_。 …以-鎮層表面連接的 23 200814099 2.依據申請專利範圍第1項所述之晶片電阻元件、其中, 該第一、二' 三鍍層的厚度總和大於該基材背面至該保 護膜表面的距離。 3 ·依據申請專利範圍第2項所述之晶片電阻元件,其中, 該第一鏡層的厚度大於該第二、三鍍層的厚度和。 4 ·依據申明專利範圍第3項所述之晶片電阻元件,其中, 該電阻層具有預定幾何形狀,且該保護膜包括一形狀與 該電阻層相似並與連接在該電阻層表面的絕緣層,及一 與連接在該絕緣層表面上的包覆層。 5. 依據申請專利範圍第4項所述之晶片電阻元件,其中, 該電阻層是選自由下列所構成的群組為材料形成:鈕、 鉻、鎳、鋁、錳、鋼、銀、鈀、鉑,及此等之組合。 6. —種晶片電阻元件的製造方法,包含: (a )在絶緣基板的上表面形成多數交錯縱橫間隔排 列的破裂槽,該二相鄰的橫、縱向破裂槽共同定 義出一元件單體區; (b)對應每一縱向破裂槽在該基板下表面以導電材料 形成二對應位於該縱破裂槽相反兩侧的背端電極 條; (c )對應每一縱向破裂槽在該基板上表面以導電材料 形成二位於該縱破裂槽相反兩側的正端電極條; ()在4基板下表面之每二相鄰之背端電極間的區域 上以預定金屬材料形成一兩側部分別與該二背端 電極條相連接的電阻層條; 24 200814099The two side electrodes are electrically conductive and are respectively formed on the two sides and respectively, and the positive and back end electrodes of the same side are electrically connected; and the back end: =, respectively, the positive end electrode and the side of the same side The electrode and the ::: surface are formed upward, and the per-mineral film has - mainly composed of copper: a human first positive electrode, a side plating electrode and a back electrode surface connected to the first plating layer, a nickel-based composition and n The first layer of the plating surface of the zizi plate is _ and the tin is the main component and the third _. The wafer resistor element according to claim 1, wherein the sum of the thicknesses of the first and second 'three plating layers is greater than the back surface of the substrate to the surface of the protective film. distance. The wafer resistor element according to claim 2, wherein the thickness of the first mirror layer is greater than the thickness of the second and third plating layers. 4. The wafer resistive element according to claim 3, wherein the resistive layer has a predetermined geometry, and the protective film comprises an insulating layer having a shape similar to the resistive layer and connected to a surface of the resistive layer, And a cladding layer attached to the surface of the insulating layer. 5. The chip resistive element according to claim 4, wherein the resistive layer is formed of a material selected from the group consisting of: a button, chromium, nickel, aluminum, manganese, steel, silver, palladium, Platinum, and combinations of these. 6. A method of manufacturing a chip resistive element, comprising: (a) forming a plurality of staggered longitudinally and horizontally spaced rupture grooves on an upper surface of the insulating substrate, the two adjacent lateral and longitudinal rupture grooves collectively defining a component cell region (b) corresponding to each of the longitudinal rupture grooves, a conductive material is formed on the lower surface of the substrate to correspond to the back electrode strips on opposite sides of the longitudinal rupture groove; (c) corresponding to each longitudinal rupture groove on the upper surface of the substrate The conductive material forms two positive electrode strips on opposite sides of the longitudinal rupture groove; () forming a two-sided portion with a predetermined metal material on a region between each two adjacent back-end electrodes of the lower surface of the substrate a resistor strip connected to the second back electrode strip; 24 200814099 在該多數電阻層條上w絕緣材料分別 層條; 形成一絕緣 ⑴ (g) 以高能量射束對應每一元件單體區精確切割調變 該多數絕緣層條與電阻層條的幾何形狀,以精確 調變該每一元件單體區的對應阻值· 在該步驟⑴製得之半成品的絕緣層條表面形成 一使該具有預定幾何形狀之電阻層條與外界隔絕 的包覆層條;On the plurality of resistive layer strips, the w insulating material is respectively laminated; forming an insulation (1) (g) to precisely cut and modulate the geometry of the plurality of insulating strips and the resistive strips with a high energy beam corresponding to each of the element regions; To precisely modulate the corresponding resistance value of the monomer region of each component. The surface of the insulating layer strip of the semi-finished product obtained in the step (1) forms a cladding layer strip which isolates the resistance layer strip having the predetermined geometry from the outside; ⑴沿該多數縱向破裂槽破裂該步驟(g)製得之半成 品,得到多數條狀半成品;(1) rupturing the semi-finished product obtained in the step (g) along the plurality of longitudinal rupture grooves to obtain a plurality of strip-shaped semi-finished products; (1)於該每一條狀半成品的二破裂面以導電材料形成 刀別與δ亥正、背端電極條電連接的侧面電極條; ⑴沿該步驟⑴製得之每—條狀半成品的橫向破裂 槽破裂該多數條狀半成品,得到多數分別具有二 i端電極、二背端電極、二側面電極、一電阻層 ,及一保護膜的晶片電阻元件半成品單體;及 ⑴自該每一晶片電阻元件半成品單體的二正、背、 侧面龙極表面依序以銅為主要材料成分、鎳為主 要材料成分、錫主要材料成分形成二包含有一第 一鍍層、一第二鍍層,及一第三鍍層的鍍膜,製 得多數晶片電阻元件。 依據申請專利範圍f 6 ,員所収晶片轉元件的製造方 法,其中,該正端電極條是以印刷方式成形。 依據申请專利範圍第6項所述之晶片電阻元件的製造方 25 200814099 法°亥月^電極條是以印刷方式成形。 9.依據申請專利範圍第6項所述之 法,其中’該背端電極侔〜AS ^件的製造方 保疋U金屬箔貼合方 ιο·依據申請專利範圍第6 '成形。 ,^t,,,,b _ 員所述之晶片電阻元件的f造方 法其中§亥背端電極條是以真空_方式^製 丨!.依射請專利範圍第6項所述之 >。 法,其中,該背端電極侔是以#㈣卩70件的製造方 法,其中,該電阻層條9 電阻凡件的製造方 幻層條疋以印刷方式成形。 -依據申請專利範圍第6_以 法,其中:該電阻層條是以…々電阻兀件的製造 乂金屬治貼合方式 if 14. 依據申請專利範圍第6 '成形。 法,豆中,4 士 a 、斤述之日日片電阻元件的製造 法其中,该電阻層條是以真展 15. 依據申請專利範圍第之又"形。 法,其中,該步驟⑺之二=電阻元件的製# -依據申請專利範圍帛6項=^束是錯射。 法,其中,該側面電極條是^^ /阻兀件的製瓜 _申請相I圍第6項=覆心方式成形。 法,其中,該側面電極侔是=…阻元件的製造方 认依料請專利_第6項_;^❹式成形。 法’更包含-步驟⑴,是在,:_片電阻元件的製造方 覆層上對應形成多數供辨識之字巧母—晶片電阻元件之包 26(1) forming a side electrode strip electrically connected to the δ hai positive and back electrode strips on the two rupture surfaces of each strip of the semi-finished product; (1) transverse direction of each strip-shaped semi-finished product obtained along the step (1) The rupture groove ruptures the plurality of strip-shaped semi-finished products, and obtains a plurality of wafer resistor element semi-finished monomers each having two i-terminal electrodes, two back-end electrodes, two-side electrodes, a resistive layer, and a protective film; and (1) from each of the wafers The second positive, back and side surface of the semi-finished monomer of the resistive element is mainly composed of copper as the main material component, nickel as the main material component, and the main material component of tin is formed to include a first plating layer, a second plating layer, and a first A three-plated coating produces a majority of chip resistive elements. According to the patent application scope f 6 , a method for manufacturing a wafer-transferring element received by a member, wherein the positive-end electrode strip is formed by printing. The manufacturer of the chip resistor element according to claim 6 of the patent application scope is disclosed. 9. The method according to claim 6, wherein the manufacturing of the back electrode 侔 〜 AS 件 疋 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属, ^t,,,, b _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ According to the > described in item 6 of the patent scope. The method, wherein the back electrode 侔 is a manufacturing method of #(四)卩70 pieces, wherein the manufacturing layer strip of the resistor layer strip 9 is formed by printing. - According to the scope of application of the patent No. 6_, wherein: the resistance layer is made of ... 々 resistance 兀 乂 if if if if 14. According to the scope of the patent application of the sixth 'form. Method, bean, 4 士 a, 斤述日日片片电阻元件 manufacturing method, wherein the resistance layer is based on the real exhibition 15. According to the scope of the patent application. The method, wherein the second step (7) = the manufacturing of the resistive element - according to the scope of the patent application 帛 6 = ^ beam is a misalignment. The method, wherein the side electrode strip is a melon of the ^^ / barrier member _ application phase I around the sixth item = core forming. The method, wherein the side electrode 侔 is a manufacturing element of the ...... resistance element, the patent _6 item _; The method further includes the step (1) of forming a plurality of packets for identifying the type of the chip-resistive component on the manufacturing layer of the :--resistive resistor element.
TW95133838A 2006-09-13 2006-09-13 A chip resistor component and a manufacturing process thereof TWI294129B (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
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TWI478643B (en) * 2012-12-21 2015-03-21 Inpaq Technology Co Ltd Electronic structure and electronic package component for increasing the bonding strength between inside and outside electrodes
TWI556403B (en) * 2014-05-09 2016-11-01 佳邦科技股份有限公司 Electronic structure and method of manufacturing the same, and electronic package component
TWI824431B (en) * 2021-03-12 2023-12-01 日商Koa股份有限公司 Mounting structure of chip components

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TWI582799B (en) * 2014-10-01 2017-05-11 Metal plate micro resistance
TWI632835B (en) * 2016-12-05 2018-08-11 健鼎科技股份有限公司 Circuit board structure and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI478643B (en) * 2012-12-21 2015-03-21 Inpaq Technology Co Ltd Electronic structure and electronic package component for increasing the bonding strength between inside and outside electrodes
TWI556403B (en) * 2014-05-09 2016-11-01 佳邦科技股份有限公司 Electronic structure and method of manufacturing the same, and electronic package component
TWI824431B (en) * 2021-03-12 2023-12-01 日商Koa股份有限公司 Mounting structure of chip components

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