TWI293139B - Array substrate for liquid crystal display device and method of manufacturing the same - Google Patents

Description

1293139 _ case number five, invention description (1) monthly correction [invention of the technical field of the invention] The present invention relates to a liquid crystal display (LCD) device, and more specifically, "there is a kind of liquid crystal display Array substrate and manufacturing method therefor 0 [Prior Art] A liquid crystal display (LCD) device comprises two substrates separated by a substrate, and a liquid crystal material layer interposed between the two substrates. Each substrate includes an electrode, and the electrical terminals of each substrate are also opposite each other with a voltage applied to each electrode. The collimation of the liquid crystal molecules is changed by changing the intensity or direction of the above electric field. Such an LCD device displays an image by changing its transmittance in accordance with the arrangement of liquid crystal molecules. A conventional technical LCD device will be described in detail below with reference to the drawings. Fig. 1 is an enlarged perspective view showing a conventional LCD device 11 of the prior art. The conventional LCD device 11 of the prior art has a substrate 15 and a lower substrate 22' facing each other and a liquid crystal 15 interposed between the upper substrate 5 and the lower substrate 2 2 . The upper substrate 5 includes a black matrix 6, a color filter layer 7, and a common electrode 9 which are formed on the inner side thereof (that is, the side facing the lower substrate 22), and the common electrode 9 has Some openings. The color filter layer 7 corresponds to the opening of its black matrix 6, and includes three sub-filter layers of red (R), green (g), and blue (B). The common electrode 9 is formed on the color filter layer 7 and is transparent.

Page 10 1293139 --m. 92131310_One month B Amendment 5, invention description (2) 'One' - there is at least one gate line 12, and at least one data line 34 is formed on its lower substrate 22 The inner surface (i.e., facing the side of the upper substrate 5 thereof). The gate lines 12 and the data lines 34 intersect each other to define a pixel region P. A thin film transistor as an exchange element τ is formed at the intersection of the gate electrode 12 and the data line 34. The thin film transistor includes a gate, a source, and a drain. Most of the thin film transistors are The pixels are arranged in a matrix form so as to correspond to the parent switch points of the other gate lines and the data lines, and the pixel electrodes 65 connected to the thin film transistor τ are formed in the pixel region 。. The pixel electrodes 5 6 Corresponding to its sub-color film 'and a transparent conductive material having a relatively good transparency, such as indium tin oxide (ΙΤ〇). It includes some thin film transistors and pixels arranged in a matrix form. The lower substrate 22 of the electrode 56 can be generally referred to as an array substrate. 'A scanning pulse is applied to the gate of its thin film transistor through its gate line 12, and a data signal is applied to its thin film transistor through its Gongke line 34. The LCD device 11 is driven to X by the electrical and optical effects of the liquid crystal germanium 5. The liquid crystal 15 is a dielectric anisotropic material having a property of spontaneous polarization. When a voltage is applied, the liquid crystal 15 will form a dipole due to its spontaneous polarization, and thus its liquid crystal molecules will be arranged by an electric field. The optical properties of the liquid crystal will produce optical modulation. It is changed according to the arrangement of the liquid crystals. The image of the L c D device can be generated by controlling the transmittance of the optical modulation. Since such an LCD device is manufactured through a complicated process, there has been one

Page 11 1293139

Fixed some trials to reduce the manufacturing time and cost by simplifying the JL a process. The sequence of the substrate of the LCD device is manufactured by using a four-mask process, which is called a four-mask process, and is different. Then, use the process of five to seven masks. Fig. 2 is a plan view showing an array of substrates according to the process of the four masks according to the conventional technique. In Fig. 2, a gate line ^ and a data line 34 intersect each other and define a pixel area ^ P. A thin film transistor T is formed as an exchange element at its gate line and data lines 12 and 34. A gate pad 10 is formed at one end of its gate line 12 and a data pad 3 6 is formed at one end of the data line 34. The gate pad terminal 58 and the material pad terminal 6〇, which are island-shaped and made of a transparent conductive material, overlap with the gate pad 1 〇 and the material pad 36, respectively. ^傅, transistor T, includes: a gate connected to its gate line 12, a gate of the scanning nickname 1 4, a source connected to its data line 3 4 and a source of data #4 And a drain 4 2 separated from the source 4 。. The thin film transistor T further includes an active layer 32 between its gate 丨4 and the source and drain electrodes 4 〇 and 42. The island-shaped metal pattern 38 has an overlap with its gate line 12. A pixel electrode 56 is formed in its pixel region p and is connected to its drain 4 2 . The pixel electrode 526 extends above its gate line 12 and thus also to its metal pattern 38. The idler line 1 2 and the metal pattern 38 function as the first and second storage capacitor electrodes ', respectively, and the gates disposed between the gate lines 12 and the metal patterns 38

Page 12 Milk 3139 Wide description of the invention -------- Β The insulating layer h I 噌 (not shown), and 42 ^ are not shown in the figure, at J: storage capacitor CsT. A between, the system is formed with ~^^/tongue layer Μ with its source and bungee 4 0::, made by ίί 欧;;:: layer. Its live... is with - and . It includes an amorphous lanthanide-doped amorphous yttrium and a second-in-one pattern 209, respectively, below the first pattern 3 5 of the doped amorphous yttrium. μ is formed in its data line 34 and metal pattern 38 as described above, in Figure 2, and in the fabrication of the array of substrates, the process of using four masks to cover the soil, will be lost in the following The attached figures are used to illustrate. Μ

Figures 3A to 3G, 4A to 4G, and 5th to 8th are cross sections of the discs - Η ', IV - iv, and v - V, respectively, along the second drawing. Figures, which illustrate a method for fabricating an array substrate in accordance with conventional techniques. As shown in Figures 3, 4, and 5, a gate line 12, a gate 1 4, and a gate pad are shown. The sheet 10 is patterned by depositing a first metal layer and through a first lithography process using a first mask, that is, a first masking process. To form a transparent insulating substrate

twenty two. These gate lines 1 2, gates 1 4, and gate dies 10 0 ' are made of a metal such as Ming (Α1), Ming alloy, Mo (Mo), Crane (W), and He (Cr). Made of materials. The gate line 2, the gate 14 and the gate pad 10, which are made of aluminum or an aluminum alloy, may be formed of a double layer comprising molybdenum or chromium. Secondly, a gate insulating layer 16 , an amorphous germanium layer 18 , a doped amorphous germanium layer 20 , and a second metal layer 24 are included thereon along with the subsequent deposition.

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^^^92131310 V. DESCRIPTION OF THE INVENTION (5) The gate insulating layer 12, the gate electrode 14, and the gate insulating layer 16' function as a first insulating layer. Its ruthenium telluride (SiNx) and bismuth oxide (Si material, made by the factory similar to a metal layer 24, Sun Yiqi 2, ..., machine, and Bayuan material 。, which is made of chrome, turn, tungsten And 钽 (Ta) 中成. "As illustrated in Figures 4, 4B, and 5B, one of them is a fine photoresist, so that it can be formed in the ruthenium layer 26, the layer 26 can be a Positive class brother: ί is on the top of layer 24. Its photoresist ^ m Ik and its exposure to light opacity are eight ί: ft to remove. • And, its photoresist layer 26 makes exposure. Shooting = branching, blocking part 8, and semi-transmission - the first part with the seam part), the waste s 7 η total you * 1 , AJ is the upper part of the narrow. Feng Feng,: 'cover system and its photoresist The layers 26 are arranged in phase with each other at a recombination; the / portion corresponds to its idle pole 14. It corresponds to a semi-transparent, = as illustrated in the 3C, 4C, and 5C diagrams, 3B, 4B, and 2r * ▲ The photoresist layer 26 is developed, and is formed by a photoresist pattern L, which is caused by different light-transmitting portions of the second mask 7 ,, and the photoresist pattern i has different thicknesses. a thickness of the photoresist pattern 26a, which is ^3B, 4B And the barrier portion B of the 5B diagram. The photoresist pattern 26a of the thickness of the first thicker voice corresponds to the third Β, 4 Β, : 5 鸠 = semi-transmissive portions Ce β and # are also like 3D, 4D, And the second metal layer 24, the doped amorphous stone pattern " and the amorphous layer 18 exposed by the '3C, 4C, and 5cm 々 々 pattern 26a exemplified in the 5D diagram will be removed Thus will form a

1293139 ------ Case No. 92313310_ Year of the month revised five, invention said ^ ^ -------- pole and no pole pattern 28, the second figure of the data line 34, data gasket 36, blend The impurity $ amorphous stone pattern 32a, and the active layer 3〇. The 3C, 4C, and % diagrams of a metal layer 2 4 ' are engraved with a wet money engraving method, and the doped amorphous enamel layers 2 c and 2 of the 3 c, 4 C, and 5 C patterns The crystalline layer ι8 is etched by a dry etching process. The source and drain patterns 28 are formed over their gates 14 and are connected to the data lines 3 4 of Figure 2, which in the case of the figures extend vertically. The doped amorphous stellite pattern, 32 active layer 3 〇, has the same shape as its source and drain pattern 28 and data line 34. At this time, there is an island-shaped metal pattern 38 which is also formed above its gate 1 2 . A first pattern 35 and a second pattern 209 are formed to include an amorphous germanium layer and a doped amorphous germanium layer. Its first pattern 35 is located below its data line 34 and the material spacer 36, and its second pattern 209 is located below its metal pattern 38. Secondly, as illustrated in Figures 3E, 4E, and 5E, the second thickness of the photoresist pattern 26a is removed by an ashing process, and thus the source and drain patterns 28 are exposed. Out. Wherein, the photoresist pattern 2 6 a ' of the first thickness is also partially removed, and the first thickness of the photoresist pattern 263 is thinned. Further, the edges of the photoresist pattern 206 are removed, and the metal patterns 28, 36, and 38 are exposed. As exemplified in FIGS. 3F, 4F, and 5F, the source and the gate pattern 28 and the doped amorphous slab pattern 32a exposed by the photoresist pattern 269a in FIG. 3E will be etched. . Therefore, its source and drain electrodes 4 and 42 and the ohmic contact layer 32 will be formed, and its active layer 30 will be exposed. This is in its source

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1293139 Case No. 92131310 V. INSTRUCTIONS (7) MONTHLY MODIFICATION The exposed active layer 3 汲 between the bungee 40 and 42 will become a thin film electricity: the channel CH of life. Its source and drains 40 and 42 are separated from each other. The region between the source dipoles 40 and 42 corresponds to the semi-transmissive portion C of the second mask 7A of Fig. 3B. The source and drain patterns 28 of the right 3E image are formed of molybdenum (M〇), the source and drain patterns 28 and the doped amorphous germanium pattern 32a, which can be applied once by a total of two etching methods. Remove. However, if the source and drain patterns are + formed to form their source and gate patterns 28, they are etched using wet etching, and then removed by dry etching. Sister Hangcheng, as described above, its source and immersion 4 0 and 4 2, data line 34, capital = sheet 36, metal pattern 38, ohmic contact layer 32, and active layer 3 〇, system = use 3B The second lithography process of the second mask 70 of '4B, and 5B is formed. ^ Its photoresist pattern 2 6 & will be removed, and its passivation layer read day 'day ίί by coating a similar phenylcyclobutene (BCB) and acrylic resin, etc., or Depositing a material similar to Shiyang Nitride (SiNx) and Shih Oxide $2...the material is formed as a second on its data line 34, source and unread, ®f, and spacer 36 Insulation. The passivation layer 46 is a third lithography process using a third mask, relative to its gate til, cilla, gate pad contact hole 52, and data pad contact hole 54. The M fy! hole 48, the storage contact hole 5〇, the gate pad contact hole 52, and the 8, the gate ^" 54, will expose the drain 42, the metal pattern 38, and the gate pad 1 respectively. 〇, and data spacer 36.

Page 16 1293139 __ Case No. 92313310 V. Description of the invention (8) Year J--^ As in the 3G, 4G, and 5G diagrams, by depositing a similar tin oxide (IT 0 ) and a transparent conductive material such as indium oxide (I z 0 ), and a fourth lithography process using a fourth mask, patterning the transparent conductive material, and forming a passivation layer 46 thereon The pixel electrode 56, the gate pad terminal 58 and the data chip terminal 60. The pixel electrode 526 is connected to its drain 4b via its drain contact hole 48, and also through its storage contact hole 50, to its metal pattern 38. The idle pad terminal 58 is connected to its gate pad 10 and its data pad terminal 60 via its gate pad contact hole 52, through its data pad 36, to connect to Its material gasket contact hole 5 4 . As mentioned above, the array substrate is fabricated by a lithography process using a mask, i.e., a masking process. The lithography process includes several steps of cleaning, coating the photoresist layer, exposing through the mask, developing the photoresist layer, and etching. Therefore, by reducing the number of lithographic processes, the manufacturing time, cost, and failure can be reduced. SUMMARY OF THE INVENTION Accordingly, the present invention is directed to a yoke for a liquid crystal display device and a method of fabricating the same, which substantially obviate one or more problems caused by the prior art. ^,,, £ This is an advantage to provide a liquid crystal display: substrate and = method 'which can increase its productivity due to the shorter one. Flat and low additional features and advantages of the present invention will be listed in the following description.

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And some of the abilities are available. Ming and its application to achieve and achieve the achievement of the current and include: a board above the resources can define a sum of the data line and the passivation area on the bungee surface in the bun, and the data section Contacting the phase contacts to form a masking process on the manufacturing of the present invention, forming a data area on the surface, the source of which is apparently added to the patent range of the present invention plus this and other broad descriptions in one The substrate upper material line and the data pixel area; at the intersection point, a layer is disposed on the layer, wherein the substrate, the gasket terminal portion including the passivation layer, and the gate pad and the other method method thereof include "Inter-polar line, this includes the gate data line, the capital line, the extension of the system and its advantages, and other excellent features, as well as the gate line gasket of a liquid crystal display. The thin film electro-crystal and the system include a thin film purification layer plus a drain electrode, a pixel electrode pad terminal on the gate substrate, a tab terminal, a system, a liquid: through a gate The gasket, the wire, the gate material gasket, the source electrode line intersect the data line, 'or the point can be specified by the device according to the invention and the gate gasket wire and gate body' It is engraved on the base of a gate and a live transistor, so that the pole pad and the pixel electrode are directly exposed to a masking process and gate with the data pad crystal display device; the film and the gate are Extremely pole, immersed, and more, and the purpose of the invention is that the structure of the 汲 系 与 与 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列 阵列The entire surface is exposed to the image pad; the gate pad of the gate pad is exposed to the exposed pad. The array substrate is disposed on a substrate over a second mask and the active layer, and a pixel is defined.

Page 18 1293139 Amendment f No. 9213131η V. Description of invention (10) The 3J jf active layer is arranged between its closed pole and its source and drain, and the sensitive = 三 three mask process, including the data line, The source, and the bungee layer...the layer of the purification layer is engraved, so that the substrate in the pixel area, the portion of the non-polar pad; and the force ian , n 4 on the shell, % # - 1 1 + ', the entire surface of the substrate including the passivation layer ΐ - 4: Π: : material 1:: into - pixel electrode, gate pad direct contact, and basin data 』: = chip terminal, with its gate Pole gasket contact. , /, shellfish gasket tweezers, the main reason for its data gasket is that the former Li Xi, both are exemplary and;;: a detailed description of the following. Zhang further explained. Illustrating the present invention, and the intention is to provide the present invention, such that it is included in the present invention for the purpose of ^^^^^, and the Japanese and the Japanese, and the use of the skin: the fourth embodiment of the present invention. The system is used to explain the principles of the invention. Implementation Mode] The details of Taigong Day + attached to the map will be explained in detail. Some embodiments of the present invention are exemplified in a plan view of an array substrate of a liquid crystal display device (LCD) according to an embodiment of the present invention. i As shown in FIG. Your 1st pick-up line 132 is such that the gate line 102 and the majority of the gates are formed on a transparent insulating substrate 100. These gates

Page 19 1293139 A case of 9213131 Π _ _ _ _ _ _ _ 5, invention description (11) Line 1 0 2 and data line 1 3 2 are intersecting each other, and can define a pixel area Ρ. A thin film transistor 作为, which is an exchange element, is formed at each of the intersections of the gate lines 1 0 2 and the data lines 1 3 2 . A gate pad 106 is formed at one end of its gate line 1 〇 2, and a data pad 1 4 2 is formed at one end of its data line 133 . The gate pad terminal 164 and the data chip terminal 1 6 6 ', which are island-shaped and made of a transparent conductive material, are overlapped with the gate pad 1 〇 6 and the material pad i 4 2, respectively. The thin film transistor T is a gate 104 capable of receiving a scan signal connected to its gate line 1 〇2, a source 163 connected to its data line 132 and capable of receiving a data k, and a It consists of a poleless 1 3 8 separated from the source 1 36. The thin film transistor τ further includes an active layer 126 between its gate 104 and the source and the drains 136 and 138. One of the island-shaped metal patterns 丨 3 4 overlaps with its gate line 1 0 2 . Its metal pattern 134 can be made of the same material as its data line 133. There is a pixel electrode 162 formed in each pixel region ρ. The pixel electrode 162 is directly connected to its drain 138 and metal pattern 134 without contacting the hole. The gate line 1 〇 2 and the metal pattern 134 are respectively applied to a first and second storage capacitor electrode, and to a gate disposed between the gate line 1 0 2 and the metal pattern 134 An insulating layer (not shown) forms a storage capacitor CST. Although not shown in the drawings, an ohmic contact layer is formed between its active layer 126 and its source and drains 136 and ι38. The active layer 12^ is made of an amorphous germanium, and its ohmic contact layer is made of a doped non-

1293139

The crystalline form is formed. There is an amorphous 矽 ^ - - case 130 and a second pattern m will be formed. 2 is located at the edge of its tributary line 132 and data slab 142: two 3 second patterns 13 〇 and 131 (==, if f i26 and the first 131 and 131 amorphous 矽 layer) are exposed. And the second pattern 13 〇 and = exposed the pixel electrode 162, the gate pad terminal 164, and the solid slope = ϋ mu so that the formation of the substrate along the entire table of the life of the terminal 166 price 1A to 7H map , 8th 8th to 8th thief, and 9th to 9thth, the system is based on the manufacturing method of the array substrate according to the embodiment of the present invention, and the line / 痤 respectively along the line of Fig. 6 YU - vn, boron - Shan, and Han-Han, a cross-sectional view. ^ First, as illustrated in Figures 7A, 8A, and 9A, by depositing/first metal layer, and through a first lithography process using a first mask, ie, the first mask process To pattern the first metal layer, a gate line 1 0 2, a gate 1 〇 4, and a gate pad 1 〇 6 are formed on a transparent insulating substrate 1 。. As described above, its gate 1 〇 4 extends from its gate line 1 0 2 and its gate 1 1 〇 6 is located at one end of its gate line 1 0 2 . The gate line 1 0 2, the gate 1 04, and the gate pad 106 are made of a metal material such as aluminum (A1), molybdenum (M〇), tungsten (w), and chromium (Cr). to make. In order to avoid its resistance-capacitance (RC) delay, a relatively low resistance (A 1 ) is widely used as a gate material. However, pure aluminum is susceptible to acid corrosion and may be due to subsequent high temperatures.

1293139 ----92131310 Car month and day Yongzheng V. Invention description (13) """" '~' — Cheng Yuzhi #丘, caused some lines. Therefore, an aluminum alloy or a double layer including aluminum and other metal materials such as molybdenum may be used. As illustrated in Figures 7B, 8B, and 9B, a gate insulating layer I 〇 8 , an amorphous germanium layer 11 掺杂 , a doped amorphous germanium layer 1 丨 2 , and a second metal layer 114 are provided The substrate 1 is deposited on the substrate 1 including the gate line i2, the gate 1/04, and the gate pad 106. Its gate insulating layer 1〇8 is made of an inorganic insulating material similar to urethane (s i N x) and yttrium oxide (s i 〇 2). The gate insulating layer 1 〇8 may be formed of an organic insulating material such as phenylcyclobutene (BCB) and acrylic resin. Its second metal layer 11 4 ' is made of one of chromium, ruthenium, crane, and group (Ta). Next, a photoresist layer 116 is formed on the second metal layer 11 4 by coating a photoresist. A second mask 17 having a transmissive portion E, a barrier portion F, and a semi-transmissive portion G is disposed above and spaced apart from the photoresist layer II 6 . The semi-transmissive portion G may include a plurality of slits ' and a channel corresponding to a thin film transistor. The photoresist layer 1丨6 can be of a positive type and thus a portion exposed to the light wave can be developed and removed. Then, the photoresist layer 1 6 is exposed, and the photoresist layer 6 corresponding to the transmissive portion E is exposed less than the photoresist layer 1 16 corresponding to the portion E. As exemplified in Figures 7C, 8C, and 9C, the 7B, 8B, and 9 photoresist layers 11 are developed, and a " photoresist pattern 120a having a different thickness will be formed. The photoresist pattern 120a of the first thickness corresponds to the barrier portion F of the layers J > JB, 8B, and 9B, and the photoresist pattern 12〇a which is thinner than the first thickness and has a second thickness. Corresponding to the semi-transmission part of the 7B figure

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G 〇 , as exemplified in the 7D, 8D, and 9D drawings, the second metal layer 114 exposed by the photoresist pattern 120a in the 7C, 8C, and 9C patterns, and the doped amorphous slab layer 11 2 . And the amorphous layer 1 will be removed. Thus, a source and drain pattern 124, a data line 132, a material spacer 142, a doped amorphous pattern 128a, and an active layer 126 are formed. At this time, an island-shaped metal pattern 1 3 4 is also formed above its gate line i 〇 2 . Secondly, the second thickness photoresist pattern 1 2 0 a will be removed by an ashing process, and thus the central portion of the source and drain patterns i 2 4 will be exposed. The photoresist pattern 120a of the first thickness thereof is also partially removed/and the photoresist pattern 1 2 〇 a of the first thickness thereof will be thinned. In addition, the edge of the photoresist pattern 120 will be removed, and its metal patterns i 2 4, 3, 134, and 14 2 will be exposed. Further, there is formed a first pattern 130 and a second pattern 131_? including the amorphous terracotta layer 130 咏1 3 1 of the doped non-negative ruthenium layers 130b and 131b. The first pattern 130 is located below the data line 132 and the material spacer 742, and the second pattern 1 31 is located in the second metal layer 114 of the metal pattern 1 3 4, 7C, 8C, and 9C. , can be engraved with ^7/', and the doped non-crystalline layer 11 2 and the amorphous layer 11 第 of the 7C, 8C, and 9C patterns can be patterned by a dry etching method. . The source and immersion patterns 1 24 are formed on its gates 1 &<RTIgt;</RTI> and to be connected to its data line 132, which in the case of this figure extends vertically. Its data spacer 1 42 is disposed at one end of its data line 1 32 as previously mentioned. Its doped amorphous 矽 pattern 丄 28_ ^ two

1293139 ___ j No. 92113310 rev. 5, invention description (15) ' ------ layer 1 2 6, with its source and bungee pattern 丨 2 4 and data line 丨 3 2, have the same shape . Next, as illustrated in FIGS. 7E, 8E, and 9E, the source and drain patterns 丨24 and the doped amorphous shi pattern 128a exposed by the photoresist pattern 1 2 0 a of the 7D pattern are as shown in FIGS. 7E, 8E, and 9E. Will be etched. Thus, its source and drain electrodes 136 and 138 and ohmic contact layer 128 will be formed, and its active layer 126 will be exposed. The active layer 126 exposed between the source and the drains 136 and 138 will become the channel of the thin film transistor T, and the semi-transmissive portion G corresponding to the second mask 170 of FIG. 7B. . The gate 1 〇 4, the active layer 126, the source 136, and the drain 138 constitute the thin film transistor τ. The source and drain electrodes 1 3 6 and 1 3 8 are separated from each other. The active layer 丄26 has the same shape as its source and drain electrodes 136 and 138, and includes an additional between its source and drains 136 and 138. section. At this time, the edges of the amorphous germanium layers 126, i3〇a, 131a disposed under the source and the tips 136 and 138, the data link 132, the data spacer 142, and the metal pattern 134 will also be exposed. . If the source and drain patterns 124 of FIG. 7D are formed of molybdenum (M〇), the source and drain patterns of FIG. 7D and the doped amorphous germanium pattern 1 2 8 a ' It was removed once using dry etching. However, if the source and the electrode pattern 1 2 4 are formed of chromium (C r ), the source and the gate pattern 1 24 are etched using wet remnant, and then the doping The amorphous Shi Xi pattern 1 2 8 a can be removed by dry money engraving. As described above, its source and immersions 136 and 138, data line 132, data pad 142, metal pattern 134, ohmic contact layer 128, and live

1293139 Case No. 92131310 修正 Amendment V. Description of Invention (16) The layer 126 is formed by a second mask process using the 7B. Secondly, in the 7th D, 8D, and 9D diagrams, a passivation layer 160 is transferred by a pattern 120 and a photosensitive organic material such as an acrylic resin. (BCB) into the source and drain electrodes 1 3 6 and 1 3 8 , the thickness i is formed on the substrate 1 〇〇 142, and the metal pattern 134 of the entire table ^ 32, the data pad electrode as the first 7 F, 8 F, and 9 F maps - ^ A third lithography using a third mask "= makes the 2 J layer on the 60 line through m, the metal pattern pole and the poleless 136 and Europe Above the spacer portion, the sheet 106, and the material spacer 142. Among them, a portion of the immersion 138^^ = pattern 134 is also exposed. The gate is thermally κ a 4 ◎ layer i 〇 8 covered. The closed-pole gasket l〇6 will still be subjected to its gate insulation 8B, and the second mask of the 9B diagram 1 70

The remaining passivation layer 16 6 is hardened at some fixed temperature, and its passivation layer 160 thus has a circular arc-shaped surface. At this time, the side of the passivation layer 160 should be gradually reduced on the reverse side, and

An angle less than 90 degrees. This can be obtained by performing the hardening process of its passivation layer 160 on several times instead of once. a As illustrated in Figures 7G, 8G, and 9G, the gate insulating layer 1 〇 8 exposed by the purification layer 160 will be removed, thereby exposing its spacer pad 106. At this time, the substrate 1 〇 in the pixel region will also be exposed. As illustrated in Figures 7H, 8H, and 9H, by depositing a similar indium

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Case No. 92113310 V. Description of the Invention (17) A transparent conductive material such as tin oxide (ITO) and bismuth zinc oxide (IZ〇) may form a pixel electrode 162 and a gate pad terminal on the substrate 100. 1 6 4, and the mating gasket terminal i 6 6. The pixel electrode i 6 2 is disposed in its pixel region and does not need to contact the hole to be connected not only to its drain 138 but also to its metal pattern 134. The metal pattern 134 is a gate insulating layer between the gate line 1 0 2 and the gate line 1 〇 2 and the metal pattern 134 to form a storage capacitor. The pixel electrode 丨6 2 is in contact with the substrate 1 〇 in the pixel region. The gate electrode terminal 164 and the data chip terminal 166 are respectively covered with the gate pad 1〇6 and the data pad ι42, and are in contact with each other. Since the passivation layer 丨6 〇 is patterned, the pixel electrode 16 2, the gate pad terminal 164, and the data chip terminal 166 are disposed in the middle of the pattern of the purification layer 160. The pixel electrode 1 6 2, the gate pad terminal 1 6 4 , and the material pad terminal 16 6 are caused by the passivation layer on the side which is gradually reduced on the reverse side, and the lithographic process is not required, but in the respective Formed in the pattern. Among them, some transparent conductive patterns 163 are also formed on the passivation layer 16 6 。. In the above embodiments, the passivation layer of the organic material is 16 〇 formed directly on the thin film transistor T thereof, and the passivation layer 160 is the active layer of the thin film transistor T 1 2 6 Contact. In order to enhance the contact characteristics between the active layer 1 26 and the passivation layer 160, a germanium inorganic insulating pattern can be formed between the passivation layer 160 and the thin film transistor τ. Hereinafter, another embodiment of the present invention will be described with reference to Figs. 10, 11, and 12. 10th, 11th, and 12th, illustrating an embodiment of the present invention

Page 26 1293139 - - 銮 3131 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ' νπι -vm ', and ]X - Han's cross-sectional view. As shown in the figure, there is an inorganic insulating pattern 14 3 formed between the thin film transistor T and the organic passivation layer 160. The inorganic insulating pattern 14 3 is formed by a patterning process using its organic purification layer 16 0 as a residual mask. In particular, after the source and the immersion of the thin film transistor 形成 and the data line 133 are formed, by depositing one selected from the group consisting of: ε 氮化 nitride (si ν χ) And the cerium oxide (the inorganic insulating material group of Si 0 D, an organic insulating layer will be formed. Next, the above-described patterned organic purification layer 160 is made by the method described in the previous embodiment. Formed on the inorganic insulating layer thereof. The inorganic insulating layer and the gate insulating layer exposed by the passivation layer 160 are removed by using the patterned organic purification layer 160 as an etch mask. The inorganic insulating pattern 143 is formed. Therefore, the inorganic insulating pattern 1 4 3 ' has the same shape as the above-described patterned organic purification layer 16 。. Then, by deposition on the entire surface of the substrate 10 〇 a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (ΙΖ0), which can form the pixel electrode 1 6 2, the gate pad terminal 164 on the substrate 100, and Data pad terminal 166. Its pixel electrode 162 is arranged in In the pixel region, the contact hole is not only directly connected to its step 138, but also connected to its metal pattern ι34. Its pixel electrode 162 is in contact with the substrate 100 in its pixel region. End 1293139 V. Inventive Note (19) = 164 and data pad terminal 166, which are covered by their gate pads 1〇6 and tributary pads 1 4 2 ', respectively, and are in contact with them. In the embodiment in which the layer 160 includes the inorganic insulating pattern 143 between the thin film transistor τ, the data line 132, and the gate line 102, since the bean helmet insulating pattern 143 is opposite to the thin film transistor anti-active layer 126, Γ6. It is a good contact characteristic, its thin film transistor; it can be improved in terms of transport properties. In addition, its inorganic insulating pattern 3 ' prevents its organic passivation layer i 6 剥离 from its gate and 132 stripped 々贝竹绿1U2 Among them, due to the height of its organic passivation layer 160, the spring is crying ^ ^ t ^ ^ ^ ^ ^ ^ lJ ^ ^ ^ ^ ^ ^ ^ "- short circuit. Households, remove Organic purification layer under = f blood 1. This organic passivation layer 16〇 can be stripped In addition, the basin: the array substrate is immersed in the organic purification layer 16 〇 "the organic passivation layer 160, and the transparent conductive pattern t is stripped off the substrate. The electric "back tea U3, also from its array, the same The array substrate of the present invention is manufactured by making two. Therefore, the manufacture of the array substrate according to the present invention f', the process and cost are reduced, and the productivity thereof can be increased. It will be apparent that the spirit and scope of the invention are the same as those of the invention. Accordingly, the present invention is intended to be in a singular and modified form, as long as they are within the scope of the appended claims and their equivalents. Shenyan patent

Page 28 1293139 _ Case No. 92113310_年月日日 Revision _ BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an enlarged perspective view showing a conventional technical liquid crystal display device (LCD); FIG. 2 is based on this conventional knowledge. A plan view of an array substrate of a technical LCD; FIGS. 3A to 3G, 4A to 4G, and 5A to 5G are cross-sectional views illustrating a method of fabricating an array substrate according to the prior art, 6 is a plan view showing an array substrate of a liquid crystal display device (LCD) according to an embodiment of the present invention; FIGS. 7A to 7H, FIGS. 8A to 8H, and 9A to 9H are some examples A cross-sectional view of a method of fabricating an array substrate according to an embodiment of the present invention; and FIG. 10, FIG. 11, and FIG. 2 are diagrams showing an array according to another embodiment of the present invention. A cross-sectional view of the substrate. [Component Symbol Comparison Table] C st Storage Capacitor P Pixel Region T Thin Film Electromorph 5 Substrate 6 Black Matrix 7 Filter Layer 9 Common Electrode 10 Gate Pad

Page 29 1293139 _ Case No. 92313310_Yearly and Moon Correction Schematic Description 11 LCD device 12 Gate line 14 Gate 15 Liquid crystal 16 Gate insulating layer 18 Amorphous germanium layer 20 Doped amorphous germanium layer 22 Lower substrate 24 second metal layer 26 photoresist layer 2 6a photoresist pattern 28 source and drain pattern (metal 29 second pattern 30 active layer 32 active layer 32 ohmic contact layer 3 2 a alternating amorphous pattern 34 data line 3 5 First pattern 36 Data spacer (metal pattern) 38 Metal pattern 40 Source 4 2 Deuterium 46 Purification layer

Page 30 1293139 ___ Case No. 9231310 Year of the month correction diagram Simple description 48 Gate contact hole 50 Storage contact hole 52 Gate pad contact hole 54 Data pad contact hole 5 6 Pixel electrode 58 Gate pad terminal 60 Data pad terminal 7 0 second mask 100 transparent insulating substrate

102 gate line 10 4 gate 106 gate pad 108 gate insulating layer 110 amorphous germanium layer 112 doped amorphous germanium layer 114 second metal layer 116 photoresist layer 12 0a photoresist pattern 124 source and germanium Polar pattern (metal pattern)

12 6 active layer 128 ohm contact layer 128a doped amorphous 矽 pattern 130 first pattern (metal pattern) 1 3 0 a amorphous layer

Page 31 1293139_One-heart diagram simple description 130b Amorphous germanium layer 131 Second pattern 131a Doped amorphous germanium layer 131b Doped amorphous germanium layer 132 Data line 134 Metal pattern 136 Source 138 Bungee 142 Data pad Sheet (metal pattern 143 inorganic insulating pattern 160 purification layer 162 pixel electrode 163 transparent conductive pattern 164 gate 塾 terminal 166 data pad terminal 170 second mask

Page 32

Claims (1)

β iiJ2 93 § ft (more) original ^ 茔 〇〇 1 SS_92lhl310 VI. Patent application scope 1. One use one in one base The data on the gate plate above the liquid crystal display panel is defined as an image where the base line intersects, the thin film transistor is tied thereto, and the gate includes a gate, which is disposed in a thin film electrical passivation layer. The base pad of the gate electrode including the passivation layer, the gate pad and the data padding layer thereof, wherein the substrate, the partial terminal, and the exposed portion of the data contact piece Contact, touch, set the line and the gate line and the qualifier layer, the lining of the crystal, the gasket, the pixel terminal on the board, the terminal, the column substrate, the pole gasket; The pole line and the resource pole, and the substrate are exposed and the pixel electrode of the data pad is directly exposed to its exposed system and its resources include: the intersection of the data line and the gate line is bungee; the pure pixel area on the surface The inner piece; and the pole and the gate pad are connected to the gate of the drain electrode of the drain electrode. The pixel electrode is surrounded by the passivation layer. 2. The array substrate of claim i, wherein the passivation layer has a side portion which is gradually reduced on the opposite side. 3. The array substrate of claim i, wherein the passivation layer has a circular arc-shaped surface. 4. The array substrate of claim 1, wherein the passivation layer is patterned, and the pixel electrode, the gate pad end, and the material pad terminal are disposed in the middle of the pattern of the passivation layer. 5. The array substrate of claim i, wherein the pixel electrode is in contact with the substrate exposed in the pixel region. 1293139 Emperor 9213LS10 VI. Application for Patent Scope 6. If the scope of application for patents is not the same as the barrier matrix of the stone scorpion, the non-Japanese-style stone layer and the doped amorphous squeak data gasket Below. (3) The system is made to expose the amorphous layer and the seventh layer of the amorphous layer. As early as the substrate, it is an island-shaped metal pattern on the array substrate of the first item of the patent range. purification! Array of 8 items of arrays" m: a part of the metal pattern exposes the array substrate of the ninth item of the pixel bungee, wherein the erecting: belongs to the y-yellow contact with the exposed portion of the metal pattern, Forming a storage capacitor - an array substrate on its pure side, further comprising an electrical pattern of a iv 德 iv, wherein the conductive pattern ' is made of the same material as its pixel electrode. The array substrate of the first aspect of the patent, wherein the active layer has the same shape as the basin JJ5 ± ΊΤ ^ ^ - -V . Β , the original pole and the drain pole, and between the source and the pole, including —The extra part. 4 4 The array substrate of the range f 1 item, including the machine insulation diagram •, the J::;, the idle line. There is no identical shape between the data lines. Having a passivation layer 14. A method of manufacturing an array substrate for a liquid crystal display device, package modification Among them, including: 1293139 Through the second gate spacer The "cover process" forms a gate and a gate on a substrate; a pixel region is defined by a second mask process chip, and a gate electrode, a drain electrode, and an active layer, a line of the gate The drain line is separated from the source and the source and between the source and the pole. The 'in the above-mentioned gate line and gate pad' form a data line, a data pad, and a source line of the source. The more the gate's source extends from its data line, 'and its active layer is placed in its gate through the second mask process, over the entire substrate including the data line, source, and drain Forming a passivation layer on the surface, the passivation layer is etched to expose the substrate in the pixel region, the portion of the gate, the gate pad, and the material spacer; and by including the above-mentioned purification layer A transparent conductive material is deposited on the entire surface of the substrate to form a pixel electrode, a gate pad terminal, and a material pad terminal, and the pixel electrode thereof is in direct contact with the exposed portion of the electrodeless portion thereof. Shim terminal, So that its direct contact with the gate pad and data pad terminal thereof, so that its data lines in direct contact with the spacer. The method of claim 14, wherein the second masking process comprises: forming a gate insulating layer over the substrate including the gate line and the gate; above the gate insulating layer Depositing an amorphous germanium layer, a doped amorphous germanium layer, and a metal layer; above the metal layer, providing a photoresist having first and second thicknesses Page 35 1293139 Sixth, apply for a patent garden pattern; According to the photoresist pattern, selectively remove the second part, the metal layer, and remove the above-mentioned second thick, 移除The amorphous germanium selectively etches the metal layer exposed by the photoresist pattern portion; the portion of the knife is exposed; the above-mentioned second thickness is selectively etched by the selected thickness and the thickness of the pattern The photoresist pattern portion is exposed to the above-described dopant pattern which is removed by removing the metal layer having the second amorphous germanium layer; and the remaining photoresist pattern is removed. 16. If the patented range of photoresist patterns is of a positive type, it is removed by the method of the item. The portion exposed to the light wave is developed. 7. The method of making the passivation of the pixel electrode before forming the pixel electrode further includes gradually reducing (three) hardening with some reverse sides, thereby making the passivation layer, angle. The side portions of 1 are such that they have a smaller than > 0 1 8 · As claimed in the patent application, the purification layer has a circular arc-shaped surface. And the method, wherein the method is as follows: the patent application scope of the first item of the Xi Shi L廿 #晶形矽 layer and the doped amorphous form, wherein the data is under the gasket. The y layer ' is a method for forming an edge of the edge line of the data line and the 〇 如 如 如 如 129 129 129 129 129 129 129 129 129 129 129 129 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 Scope 2 1. The method of claim 14, wherein the island-shaped metal pattern is formed over its gate line through its second masking process. 22. The method of claim 21, wherein the purification layer further exposes a portion of the metal pattern. 23. The method of claim 22, wherein the pixel electrode is in direct contact with the exposed portion of the metal pattern, thereby forming a metal capacitor with its gate line and gate insulating layer to form a storage capacitor. 2. The method of claim 14, wherein the mask of the second masking process comprises a transmissive portion, a barrier portion, and a semi-transmissive portion. 2 5. The method of claim 24, wherein the semi-transmissive portion comprises a plurality of slits. 2. The method of claim 14, wherein the active layer has the same shape as its source and drain, and is between its source and drain, including an additional portion. 2 7. The method of claim 14, wherein the method further comprises forming an inorganic insulating layer on the entire surface of the substrate including the data line, the source, and the drain, wherein the inorganic insulating layer is It is patterned by using its passivation layer as an etch mask to form an inorganic insulating pattern having the same shape as its passivation layer. 28. The method of claim 27, further comprising forming a pixel electrode, a gate pad terminal, and a data pad terminal Page 37 1293139 1293139 _ Case No. 92113310 _ dd/yyyyyyyyy 6. Designated representative figure VII. Designated representative figure: (1) The designated representative figure of this case is: (6). (2) A brief description of the component symbols of this representative figure: 100 transparent insulating substrate 102 gate line 10 4 gate 1 0 6 gate spacer 126 active layer 130 first pattern (metal pattern) 131 second pattern 132 data line 134 metal pattern 13 6 source 138 drain 142 data spacer (metal pattern) 160 passivation layer 162 pixel electrode 16 4 gate terminal 166 data pad terminal Page 8