1322507 » * f 0610075ITW 21I〇5twf.doc/e 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種晝素結構及其製作方法，特別是 有關於一種使用四道光罩（four-photomask)製程之書素名士 構及其製作方法。 【先前技術】 薄膜電晶體液晶顯示器（thin film transistor liquid Φ crystal dlsplay，TFT-LCD)主要由薄膜電晶體陣列基板、彩 色濾光陣列基板和液晶層所構成，其中薄膜電晶體陣列基 板是由多數個以陣列型式排列之薄膜電晶體，以及與每一 薄膜電晶體對應配置之一晝素電極(pixel electr〇de)所組 成而上述之薄膜電晶體包括閘極、通道層、沒極與源極， 且薄膜電晶體與畫素電極構成一畫素結構。其中，薄膜電 晶體用來作為液晶顯示單元的開關元件。 習知薄膜電晶體製程中，較常見的是五道光罩製程。 弟道光罩製程是用來定義第一導電層，以形成掃 擊 描配線以及薄膜電晶體之閘極等構件。第二道光罩製程是 疋義出薄膜電晶體之通道層以及歐姆接觸層。第三道光罩 製私是用來定義第二導電層，以形成資料配線以及薄膜電 晶體之源極與没極等構件。第四道光罩製程是用來將保護 層圖案化。而第五道光罩製程是用來將透明導電層圖案 化，而形成晝素電極。 然而’隨著薄膜電晶體液晶顯示器朝大尺寸製作的發 展趨勢’薄膜電晶體陣列基板的製作將會面臨許多的問題 5 0610075ITW 21105twf.doc/e 與，戰，例如良率降細及產能下降料。因此若是能 少薄膜電晶體製程的料數，即降低薄膜電晶航件製作 之曝光製程次數’即可以減少製造時間、增加產能， 降低製造成本且亦可提高製作良率。 【發明内容】 本發明之-目的是提供一種畫素結構之製作方法，以 降低晝素結構製財所使狀光罩數目，進而降低其製作 明，另—目的是提供-種晝素結構，此晝素結構 並使其愈資料配』 貢料配線輔助圖案， 之二貝枓配線並聯，以降低資料配線之電阻值。同樣 ί二;可於掃描配線上方配置-與其並聯之掃 描己t辅助圖案，以達到降低掃描配線之電阻值的目的。 製作=上i 3明提出—種晝素結構的 案化第-導電層，此圖宰化第一導c々形成-圖 描西？綠廿山，茶化第導電層包括一閘極與一掃 板上仿^中閘極與掃触線電性連接。之後，於基 料層^及絕緣層、—通道材料層、—歐姆接觸材 it:- 光層°接著’利用一灰階光罩對上述光阻層 材顯影製程，並以_化之光阻層為罩幕對通道 極上接觸材料層進行—背通道#刻製程，以於間 上形S i:通道層以及—歐姆接觸層。再來，於基板 搞^ 於保護層中形成-源極接觸孔及一沒 孔’以暴露出上述之歐姆接觸層。最後，於保護層 0610075ITW 2ll〇5twf.d〇c/( 上形成-圖案化第二導電層，此圖案化第 源極與一汲極、一資料配線以及一晝素電極。复胃L括〜 與及極分別透獅極獅孔以及祕 =中’振极 電性連接’而祕與資料配線電性連接 ’接觸層 極電性連接。 揉从極與晝素電 在本發明之一實施例中，圖案化第一 屬材料。 Μ層包括〜金 在本發明之一實施例中，圖案化第一導電層 共用配線，此共用配線是作為一晝素儲存電容^包括〜 而後續形成於共用配線上方之晝素電極即作為全電極， 谷之上電極。更進一步而言，共用配線可呈Η型”啫存電 在本發明之-實施例中，於保護層中形成源接 及汲極接觸孔時，更包括於保護層中形成至少一拱躅孔 此接觸孔是位於後續形成之資料配線的下方。 觸孔， 在本發明之一實施例中，圖案化第一導電層 少一資料配線輔助圖案，此資料配線輔助圖案l括至 觸孔與資料配線並聯。 k上述接 在本發明之-實施例中，於保護層中形成源極接 及及極接觸孔時’更包括於保護層中形成至少一接觸 此接觸孔是位於掃描配線的上方。 ’ 在本發明之一實施例中，圖案化第二導電屬更包括至 少一掃描配線辅助圖案，此掃描配線辅助圖案是透^ 、 接觸孔與掃描配線並聯。 ° % 在本發明之一實施例中，灰階光罩包括—半色調光 0610075ITW 21105twf.doc/e 罩。 在本發明之一實施例中 明導電材料。更進一步而言 化物或銦鋅氧化物。 圖案化第二導電層包括一透 此透明導電材料包括銦錫氧 =士述或是其他目的，本發明另提出 基板、—圖案化第—導電層…間絕緣層、 二、一歐姆接觸層、一保護層以及一圖案化第二導 ί二t案化第—導電層是配置於基板上，其包括一閘 性連接之—掃描配線。閘絕緣層是配置於基板 ^蓋上述之圖案化第一導電層。通道層是配置於閘 之嶋緣層上。歐姆_層是配置於通道層上。保 接二配置ΐ閘絕緣層上，其具有一源極接觸孔及-汲極 於保仰以露出歐姆接觸層。圖案化第二導電層是配置 欠ί包括一源極與一沒極、-資料配線以及- 。原極與沒極分別透過源極接觸孔及沒極 ;觸2;姆接觸層電性連接，而源極與資料配線電性連 接且旦素電極與沒極電性連接。 在本㈣之—實施财，㈣化第-導電 ，、用配線。此共用配線是作為—畫素齡電容- :後續:成於共用配線上方之晝素電極即作為 谷之上電極。更進一步而言，共用配線可呈^素儲存電 在本發明之一實施例中，保護層更具有$小° 孔，此接觸孔是位於資料配線的下方。 一接觸 在本發明之一實施例中’圖案化第一導電層更勺括 0610075ITW 21105twf.doc/e 少一資料配線輔助圖案，此資料配線輔助圖案透過上述接 觸孔與資料配線並聯。 在本發明之一實施例中，保護層中更具有至少一接觸 孔’此接觸孔是位於掃描配線的上方。 在本發明之一實施例中，圖案化第二導電層更包括至 少一掃描配線輔助圖案，此掃描配線輔助圖案透過上述接 觸孔與掃描配線並聯。 在本發明之一實施例中，圖案化第二導電層是由一透 明導電材料所組成。更進一步而言，透明導電材料句括 錫氧化物或銦鋅氧化物。 乡示上所述’在本發明所揭露之畫素結構的製作方法 中’是於第二導電層（透明導電層）中同時定義出源極、汲 極、資料配線以及晝素電極，如此，不需像傳統的晝素結 構之製程中需利用第二金屬層以形成源極與汲極，以有效 地降低其製作成本。 此外’由於本發明在資料配線下方配置一與其並聯之 資料配線辅助圖案，以藉由資料配線輔助圖案之配置而降 低資料配線之電阻值。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 、。 【實施方式】 圖1Α〜1D繪示為根據本發明一較佳實施例之一種薄 膜電晶體_基板之其中—晝素結構的製作方法之上視示 1322507 » t 0610075ITW 21105twf.doc/e 意圖；圖2A〜2D繪示分別為沿著圖1A〜1D中，剖面線 所繪之剖面示意圖。首先，請同時參考圖丨入及2A，於一 基板110上形成一第一金屬層(Metai〗)(圖中未示），並且進 行第一道光罩製程，以形成一圖案化第一導電層12〇，此 圖案化第-導電層12G主要包括i極121以及與其相連 接之一掃描配線122。除了上述之閘極121與掃描配線122 之外’圖案化第-導電層12〇更可包含一共用配線123以1322507 » * f 0610075ITW 21I〇5twf.doc/e IX. Description of the Invention: [Technical Field] The present invention relates to a halogen structure and a method of fabricating the same, and more particularly to a four-mask (four-) Photomask) The book's famous book and its production methods. [Previous technology] A thin film transistor liquid crystal display (TFT-LCD) is mainly composed of a thin film transistor array substrate, a color filter array substrate, and a liquid crystal layer, wherein the thin film transistor array substrate is composed of a majority a thin film transistor arranged in an array pattern, and a pixel electr electrode corresponding to each of the thin film transistors, wherein the thin film transistor includes a gate, a channel layer, a gate and a source And the thin film transistor and the pixel electrode form a pixel structure. Among them, a thin film transistor is used as a switching element of a liquid crystal display unit. In the conventional thin film transistor process, a five-mask process is more common. The reticle process is used to define the first conductive layer to form components such as the wiper trace and the gate of the thin film transistor. The second mask process is the channel layer of the thin film transistor and the ohmic contact layer. The third mask is used to define the second conductive layer to form the data wiring and the source and the electrode of the thin film transistor. The fourth mask process is used to pattern the protective layer. The fifth mask process is used to pattern the transparent conductive layer to form a halogen electrode. However, with the development trend of thin-film transistor liquid crystal displays toward large-size fabrication, the fabrication of thin-film transistor array substrates will face many problems. For example, yield reduction and yield reduction . Therefore, if the number of materials for the thin film transistor process can be reduced, that is, the number of exposure processes for thin film crystal wafer manufacturing can be reduced, manufacturing time can be reduced, productivity can be increased, manufacturing cost can be reduced, and production yield can be improved. SUMMARY OF THE INVENTION The present invention is directed to providing a method for fabricating a pixel structure, which is to reduce the number of masks used in the structure of a halogen structure, thereby reducing the fabrication thereof, and further, to provide a structure of a halogen. The structure of the halogen element is such that the more it is matched with the auxiliary wiring pattern of the tributary, and the wiring of the second wire is connected in parallel to reduce the resistance value of the data wiring. Similarly, it can be arranged above the scanning wiring - in parallel with the scanning of the auxiliary pattern to achieve the purpose of reducing the resistance value of the scanning wiring. Production = Shang i 3 Ming proposed - the case of the structure of the bismuth structure - the conductive layer, this figure is the first guide c 々 formation - picture description? In the green mountain, the tea-based conductive layer includes a gate and a scanning plate electrically connected to the scanning gate and the scanning line. Thereafter, in the base layer and the insulating layer, the channel material layer, the ohmic contact material it: - the light layer, then the 'photolithographic layer developing process using a gray scale mask, and the photoresist is _ The layer is a mask to the back contact material layer of the channel pole - the back channel # etch process to form the S i: channel layer and the ohmic contact layer. Further, a source contact hole and a non-hole are formed in the protective layer to expose the ohmic contact layer. Finally, on the protective layer 0610075ITW 2ll〇5twf.d〇c/ (formed and patterned second conductive layer, the patterned source and the drain, a data wiring and a halogen electrode. And the poles are respectively connected to the lion's lion hole and the secret = medium 'electrostatic connection' and the data connection is electrically connected to the contact layer. The 揉 揉 昼 昼 昼 昼 昼 昼 昼 在 在 在 在 在 在 在 在 在The first genus material is patterned. The ruthenium layer comprises ~ gold. In one embodiment of the invention, the patterned first conductive layer shares the wiring, and the shared wiring is used as a nucleus storage capacitor. The halogen electrode above the wiring is used as the whole electrode and the upper electrode of the valley. Further, the common wiring can be of the Η type. In the embodiment of the present invention, the source and the drain are formed in the protective layer. When the contact hole is formed, at least one arched hole is formed in the protective layer. The contact hole is located below the subsequently formed data wiring. The contact hole, in one embodiment of the present invention, the patterned first conductive layer is less than one data. Wiring auxiliary pattern, this data is equipped with The auxiliary pattern l is connected to the contact hole and the data wiring in parallel. In the embodiment of the present invention, when the source connection and the contact hole are formed in the protective layer, the contact layer is further included in the protective layer to form at least one contact. The contact hole is located above the scan wiring. In an embodiment of the invention, the patterned second conductive genus further includes at least one scan wiring auxiliary pattern, the scan wiring auxiliary pattern being transparent, and the contact hole being connected in parallel with the scan wiring. In one embodiment of the invention, the gray scale reticle comprises a halftone light 0610075ITW 21105 twf.doc/e hood. In one embodiment of the invention a conductive material is provided. Further, a compound or indium zinc oxide The patterned second conductive layer comprises a transparent conductive material comprising indium tin oxide or other purposes, and the present invention further provides a substrate, a patterned first conductive layer, an insulating layer, and a second ohmic contact layer. a protective layer and a patterned second conductive layer are disposed on the substrate, and include a gate connection - scan wiring. The gate insulating layer is disposed on the substrate The first conductive layer is patterned. The channel layer is disposed on the edge layer of the gate. The ohmic layer is disposed on the channel layer. The second layer is disposed on the insulating layer of the gate, and has a source contact hole and The 汲 于 于 以 以 露出 露出 。 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案 图案Touch 2; the contact layer is electrically connected, and the source is electrically connected to the data wiring and the dendrite electrode is electrically connected to the non-polarity. In the present (4) - the implementation of the financial, (4) - conductive, and wiring. The wiring is used as a picture-capacity capacitor: - subsequent: a halogen electrode formed above the common wiring, that is, an electrode above the valley. Further, the shared wiring can be stored in an embodiment of the present invention, The protective layer has a $° hole, which is located below the data wiring. One contact In one embodiment of the present invention, the patterned first conductive layer further includes a data wiring auxiliary pattern, and the data wiring auxiliary pattern is connected in parallel with the data wiring through the contact hole. In one embodiment of the invention, the protective layer further has at least one contact hole. The contact hole is located above the scan wiring. In an embodiment of the invention, the patterned second conductive layer further includes at least one scan wiring auxiliary pattern, and the scan wiring auxiliary pattern is connected in parallel with the scan wiring through the contact hole. In one embodiment of the invention, the patterned second conductive layer is comprised of a transparent conductive material. Further, the transparent conductive material includes tin oxide or indium zinc oxide. In the method for fabricating the pixel structure disclosed in the present invention, the source, the drain, the data wiring, and the halogen electrode are simultaneously defined in the second conductive layer (transparent conductive layer). There is no need to use a second metal layer in the process of a conventional halogen structure to form a source and a drain to effectively reduce the manufacturing cost. Further, since the present invention arranges a data wiring auxiliary pattern connected in parallel with the data wiring, the resistance value of the data wiring is reduced by the arrangement of the data wiring auxiliary pattern. The above and other objects, features and advantages of the present invention will become more <RTIgt; ,. 1A to 1D are diagrams showing a method for fabricating a germanium structure of a thin film transistor according to a preferred embodiment of the present invention. 1322507 » t 0610075ITW 21105twf.doc/e is intended; 2A to 2D are schematic cross-sectional views, respectively, taken along the section line in Figs. 1A to 1D. First, please refer to the drawing and 2A, form a first metal layer (Metai) on a substrate 110 (not shown), and perform a first mask process to form a patterned first conductive The layer 12A, the patterned first conductive layer 12G mainly includes an i-pole 121 and a scan wiring 122 connected thereto. In addition to the gate 121 and the scan wiring 122 described above, the patterned first conductive layer 12 may further include a common wiring 123.
及至；一資料配線辅助圖案124。此共用配線123是作為 :晝素儲存電容之下電極；在此實_中，共用配線123 疋呈Η型，然而，本發明對於共用配線123之型態不作任 何限制。此外’資料配線辅助圖案124絲成於後續形成 之資料配線的下方，以藉由資料配線輔助圖案124之配置 而降低資料配線的電阻值。再者，#料配線獅圖案124、 共用配線123以及掃她線122三者間是彼此電性絕緣。 在-較佳實施例中，圖案化第一導電層12〇包含一金屬材 料，例如鉻(Cr)、_、鈕(Ta)、鈦⑼、鉬(Μ〇)、鋁⑽ 或是其合金。 接下來，請同時參考圖汨與泷，於基板11〇上依續 形成一閘絕緣層130，以覆蓋上述之圖案化第-導電層 120 ^在—較佳實施例中’閘絕緣層130之材質可為氮/匕 t、乳化⑦、氮氧切或其他絕緣㈣。之後，於閘絕緣 二:上依續形成一通道材料層（圖中未示）、一歐姆接觸 ^曰（圖中未示）以及一光阻層（圖中未示），並利用一灰階 先罩(圖中未示)對光阻層進行第二道光罩製程，以形成一 1322507. • « 0610075ITW 211〇5twf.doc/e 圖案化之光阻層，之後，以圖案化之光阻層為罩幕對通道 材料層與歐姆接觸材料層進行一背通道蝕刻(Back Channd Etching, BCE)製程，以於閘極121上方定義出一通道層142 以及一歐姆接觸層144。此通道層142之材質可為非晶矽 (amorphous silicon)’而歐姆接觸層144之材質可為n+摻雜 非晶矽。此外，在第二道光罩製程中所使用之灰階光罩可 為一半色調光罩(Half tone mask)。 之後，請同時參考圖1C與2C，於基板11〇上形成一 保護層i5〇，並且進行第三道光罩製程，以聽護層15〇 中形成一源極接觸孔152、一汲極接觸孔154以及至少一 接觸孔156。其中，源極接觸孔152及汲極接觸孔154是 暴路出上述之歐姆接觸層144，而此接觸孔156是暴露出 部份之資料配線辅助圖案124。在此實施例中，保護層15〇 之材質可為氧化矽、氮化矽、氮氧化矽或是有機材質。 、最後’於保護層150上形成一透明導電層（圖中未示）， 並且進行第四道光罩製程，以形成一圖案化第二導電層 160 ’此圖案化第二導電層16〇包括一源極161與一及極 162、一貧料配線163以及一畫素電極164。此圖案化第二 導電層160包含透明導電材料，例如銦錫氧化物、銦辞氧 化物或其他合適之透明導電材料。其中，源極161與汲極 162分別透過源極接觸孔152以及汲極接觸孔154與歐姆 接觸層144電性連接，而源極161會與資料配線163電性 連接，且汲極162與晝素電極164電性連接。此外，資料 配線163會透過保護層15〇中之接觸孔156與資料配線辅 11 1322507 * · 0610075ITW 21105twf.doc/e 助圖案124電性連接，如此，具有高阻抗之資料配線163 與資料配線辅助圖案124會形成並聯之結構，以有助於將 低資料配線163之電阻值。如此，即完成一晝素結構之 作流程。 另外，先前所形成之共用配線123是作為畫素儲存電 ，之下電極，而形成於共用配線123上方之晝素電極16^ 疋作為畫素儲存電容之上電極，而形成於共用配線123與 畫素電極164之間之閘絕緣層13〇與保護層15〇即作為 • 容介電層來使用。 在上述實施例中，是在資料配線下方配置一與其並聯 之資料配線辅助圖案，以藉由資料配線辅助圖案之配置而 降低資料配線之電阻值。同樣地，使用者亦可於掃描配線 上方的第二導電層中形成一掃描配線輔助圖案，並於保護 層中形成相對應之接觸孔，使掃描配線可透過保護層中之 接觸孔與掃描配線輔助圖案並聯，如此，同樣可以達到降 低掃描配線之電阻值的目的。 • 综上所述，在本發明所揭露之晝素結構的製造方法 中，僅需使用四道光罩製程，即可形成所需之晝素結構。 其中’第-光罩是用來定義由金屬材料所組成之第一導電 層’以形成閘極、掃描配線、共用配線以及資料配線輔助 圖案。第二道光罩製程是用以定義通道層以及歐姆接觸 層。第二道光罩製程是用來定義保護層中的接觸孔，以形 成暴露出歐姆接觸層之源極接觸孔與汲極接觸孔，以及暴 露出資料配線辅助圖案的接觸孔。而第四道光罩是用以定 義由透明導電材料所組成之第二導電層，以形成源極與沒 1322507 0610075ITW 21105twf.doc/e 極、資料配線以及畫素電極《如此，不需像傳統的書素、续 構之製程中需利用第二金屬層以形成源極與汲極，^有效 地降低其製作成本。 此外，由於本發明在資料配線下方配置—與其並聯之 資料配線輔助圖案，以藉由資料配線輔助圖案之配置而降 低資料配線之電阻值。同樣地，本發明亦可於掃描配線上And; a data wiring auxiliary pattern 124. This common wiring 123 is used as a lower electrode of a halogen storage capacitor; in this case, the common wiring 123 is of a Η type, however, the present invention does not impose any limitation on the type of the common wiring 123. Further, the data wiring auxiliary pattern 124 is formed under the subsequently formed data wiring to reduce the resistance value of the data wiring by the arrangement of the data wiring auxiliary pattern 124. Furthermore, the #料 wiring lion pattern 124, the common wiring 123, and the sweeping line 122 are electrically insulated from each other. In a preferred embodiment, the patterned first conductive layer 12A comprises a metal material such as chromium (Cr), _, (Ta), titanium (9), molybdenum (ruthenium), aluminum (10) or alloys thereof. Next, please refer to the drawings 泷 and 泷, and a gate insulating layer 130 is formed on the substrate 11 , to cover the patterned first conductive layer 120. In the preferred embodiment, the gate insulating layer 130 The material can be nitrogen / 匕t, emulsified 7, oxynitride or other insulation (four). Thereafter, a channel material layer (not shown), an ohmic contact (not shown), and a photoresist layer (not shown) are formed on the gate insulating layer 2, and a gray scale is utilized. A first mask (not shown) performs a second mask process on the photoresist layer to form a 1322507. • « 0610075ITW 211〇5twf.doc/e patterned photoresist layer, followed by a patterned photoresist layer A back pass etch (BCE) process is performed on the via material layer and the ohmic contact material layer for the mask to define a channel layer 142 and an ohmic contact layer 144 over the gate 121. The material of the channel layer 142 may be amorphous silicon and the material of the ohmic contact layer 144 may be n+ doped amorphous germanium. In addition, the gray scale mask used in the second mask process can be a half tone mask. After that, referring to FIGS. 1C and 2C, a protective layer i5 is formed on the substrate 11A, and a third mask process is performed to form a source contact hole 152 and a drain contact hole in the hearing layer 15A. 154 and at least one contact hole 156. The source contact hole 152 and the drain contact hole 154 are violently exiting the ohmic contact layer 144, and the contact hole 156 is an exposed portion of the data wiring auxiliary pattern 124. In this embodiment, the material of the protective layer 15〇 may be tantalum oxide, tantalum nitride, hafnium oxynitride or an organic material. Finally, a transparent conductive layer (not shown) is formed on the protective layer 150, and a fourth mask process is performed to form a patterned second conductive layer 160. The patterned second conductive layer 16 includes a The source 161 and the one and the ends 162, a poor wiring 163, and a pixel electrode 164. The patterned second conductive layer 160 comprises a transparent conductive material such as indium tin oxide, indium oxide or other suitable transparent conductive material. The source 161 and the drain 162 are electrically connected to the ohmic contact layer 144 through the source contact hole 152 and the drain contact hole 154, respectively, and the source 161 is electrically connected to the data line 163, and the drain 162 and the drain are connected. The element electrode 164 is electrically connected. In addition, the data wiring 163 is electrically connected to the data wiring auxiliary 11 1322507 * · 0610075ITW 21105 twf.doc / e auxiliary pattern 124 through the contact hole 156 in the protective layer 15 , so that the data wiring 163 with high impedance and the data wiring auxiliary The pattern 124 will form a parallel structure to help the resistance value of the low data wiring 163. In this way, the process of completing a monolithic structure is completed. In addition, the previously formed common wiring 123 is a pixel storage electric and a lower electrode, and the halogen electrode 16 形成 formed on the common wiring 123 is used as the upper electrode of the pixel storage capacitor, and is formed on the common wiring 123 and The gate insulating layer 13A and the protective layer 15A between the pixel electrodes 164 are used as a dielectric layer. In the above embodiment, a data wiring auxiliary pattern connected in parallel is disposed under the data wiring to reduce the resistance value of the data wiring by the arrangement of the data wiring auxiliary pattern. Similarly, the user can also form a scan wiring auxiliary pattern in the second conductive layer above the scan wiring, and form a corresponding contact hole in the protective layer, so that the scan wiring can penetrate the contact hole and the scan wiring in the protective layer. The auxiliary patterns are connected in parallel, and the same can be achieved for reducing the resistance value of the scanning wiring. • In summary, in the method of fabricating the halogen structure disclosed in the present invention, only four mask processes are required to form the desired pixel structure. The 'photo-mask is used to define a first conductive layer composed of a metal material' to form a gate, a scan line, a common line, and a data wiring auxiliary pattern. The second mask process is used to define the channel layer as well as the ohmic contact layer. The second mask process is used to define contact holes in the protective layer to form source contact holes and drain contact holes exposing the ohmic contact layer, and contact holes exposing the data wiring auxiliary pattern. The fourth mask is used to define a second conductive layer composed of a transparent conductive material to form a source with no 1322507 0610075ITW 21105twf.doc/e pole, data wiring, and pixel electrode "so, no need to be like traditional In the process of the book element and the continuation, the second metal layer is required to form the source and the drain, and the manufacturing cost is effectively reduced. Further, since the present invention is disposed under the data wiring, the data wiring auxiliary pattern is connected in parallel with the data wiring auxiliary pattern to reduce the resistance value of the data wiring. Similarly, the present invention can also be used on scan wiring.
方形成一與其並聯之掃描配線輔助圖案，以藉由掃描配線 辅助圖案之配置而降低掃描配線之電阻值。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何所屬技術領域中具有通常知識者，在不 脫離本發明之精神和範圍内’當可作些許之更動與捫飾 因此本發明之㈣翻當視後附之申請專利翻^定者 為準。 【圖式簡單說明】 圖1Α〜1D繪示為根據本發明—較佳實施例之 ^電晶體陣列基板之其中—畫素結構的製作方法之示 思、圖。 1 圖2A〜2D繪示分別為沿著圖1A 繪之剖面示意圖。 1D中W剖面線所 【主要元件符號說明】 110 ·基板 120:圖案化第一導電層 121 :閘極 122 .掃描配線 13 1322507 0610075ITW 21105twf.doc/e 123 :共用配線 124 :資料配線輔助圖案 130 :閘絕緣層 142 :通道層 144 :歐姆接觸層 150 :保護層 152 :源極接觸孔 154 :汲極接觸孔 156 :接觸孔 160 :圖案化第二導電層 161 :源極 162 :汲極 163 :資料配線 164 :晝素電極The square forms a scan wiring auxiliary pattern connected in parallel to reduce the resistance value of the scan wiring by the arrangement of the scan wiring auxiliary pattern. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is to be understood by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the application of the invention (4) is subject to the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1D are diagrams and diagrams showing a method of fabricating a pixel structure of a transistor array substrate according to the present invention. 1A to 2D are schematic cross-sectional views taken along line 1A, respectively. 1D W cross-hatching [Main component symbol description] 110. Substrate 120: Patterned first conductive layer 121: Gate 122. Scanning wiring 13 1322507 0610075ITW 21105twf.doc/e 123: Common wiring 124: Data wiring auxiliary pattern 130 : gate insulating layer 142 : channel layer 144 : ohmic contact layer 150 : protective layer 152 : source contact hole 154 : drain contact hole 156 : contact hole 160 : patterned second conductive layer 161 : source 162 : drain 163 : Data Wiring 164: Alizarin Electrode