JP3967709B2 - Array substrate for liquid crystal display device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a liquid crystal display device, and more particularly to an array substrate for a liquid crystal display device and a method for manufacturing the same.

  FIG. 1 is a plan view schematically showing a general liquid crystal display device. As shown in the drawing, a general liquid crystal display device 11 includes a black matrix 6, a color filter 7, an upper substrate 5 on which a common electrode 9 is formed as a transparent electrode deposited on the color filter 7, and a pixel region. A pixel electrode 56 formed on P and a lower substrate 22 on which an array wiring including a switching element T is formed. A liquid crystal 15 is filled between the upper substrate 5 and the lower substrate 22.

  The lower substrate 22 is also referred to as an array substrate. The thin film transistors T as switching elements are positioned in a matrix form, and the gate wiring 12 and the data wiring 34 are formed through the plurality of thin film transistors.

  The pixel area P is an area defined by intersecting the gate line 12 and the data line 34. The pixel electrode 56 formed on the pixel region P is made of a transparent conductive metal having a relatively excellent light transmittance, such as indium-tin-oxide (ITO).

  The liquid crystal display device configured as described above displays an image by the thin film transistor T and the pixel electrodes 56 connected to the thin film transistor being present in a matrix form.

  The gate line 12 transmits a pulse voltage that drives a gate electrode that is a first electrode of the thin film transistor T, and the data line 34 transmits a signal voltage that drives a source electrode that is a second electrode of the thin film transistor T. It is means to do.

  The driving of the liquid crystal panel having the above-described configuration results from the electro-optical effect of the liquid crystal. More specifically, the liquid crystal layer 15 is a dielectric anisotropy material having spontaneous polarization characteristics. When a voltage is applied, the liquid crystal layer 15 forms a dipole by spontaneous polarization, thereby depending on the direction of electric field application. It has the characteristic that the arrangement direction of molecules can be changed. Therefore, electrical light modulation occurs when the optical characteristics are changed by such an arrangement state. Due to the light modulation phenomenon of the liquid crystal, an image is realized by a method of blocking or passing light.

  Since the liquid crystal display device that operates as described above has a very complicated manufacturing process, efforts are being made to reduce process time and manufacturing cost by simplifying the process. As a part of this, a manufacturing method has been proposed that can complete the manufacturing process of the thin film transistor array part in 5 to 7 mask processes to 4 mask processes.

  FIG. 2 is an enlarged plan view schematically showing a part of an array substrate for a liquid crystal display device manufactured by a conventional four-mask process. As shown in the figure, the gate wiring 12 and the data wiring 34 are orthogonal to define a pixel region P, and a thin film transistor T is disposed as a switching element at the intersection of the gate wiring 12 and the data wiring 34. A gate pad 10 is formed at one end of the gate line 12, and a data pad 36 is formed at one end of the data line 34.

  Each of the pads 10 and 36 is configured to contact a gate pad terminal 58 and a data pad terminal 60 which are island-like transparent electrode patterns. The thin film transistor T includes a gate electrode 14 connected to the gate line 12 to receive a scanning signal, a source electrode 40 connected to the data line 34 to receive a data signal, and a drain electrode spaced apart from the source electrode 40 by a predetermined distance. 42. The active layer 32 is formed on the gate electrode 14 and is in contact with the source electrode 40 and the drain electrode 42.

  Further, a transparent pixel electrode 56 in contact with the drain electrode 42 is formed on the pixel region P, and a part of the transparent pixel electrode 56 is formed to extend above the gate wiring 12. An island-like metal pattern 38 is formed on the gate line 12, and the metal pattern 38 is in contact with the transparent pixel electrode 56 extending on the gate line 12.

  In the configuration as described above, a part of the gate wiring 12 is used as the first storage electrode, and the metal pattern 38 in contact with the pixel electrode 17 is used as the second storage electrode. A storage capacitor Cst is formed in which a gate insulating film (not shown) disposed in a dielectric is used as a dielectric.

  At this time, although not shown, an ohmic contact layer (not shown) is formed between the active layer 32 and the source electrode 40 and the drain electrode 42, and a pure line is formed below the data line 34 and the data pad electrode 36. A first pattern 35 composed of amorphous silicon and impurity amorphous silicon is formed, and a second pattern composed of pure amorphous silicon and impurity amorphous silicon is formed below the metal pattern 38. 29 is formed.

  The configuration of the array substrate as described above is manufactured by a conventional four-mask process, and the manufacturing process of the array substrate using the conventional four-mask process will be described with reference to the drawings. 3A to 3G, FIGS. 4A to 4G, and FIGS. 5A to 5G are cross-sectional views illustrating a conventional four-mask process sequence cut along lines III-III, IV-IV, and VV in FIG. FIG. 3A to 3G show a switching element, a pixel region, and an auxiliary capacitance part, FIGS. 4A to 4G show a gate pad part, and FIGS. 5A to 5G show a data pad part.

  First, as shown in FIGS. 3A, 4A, and 5A, after forming a first metal layer on a transparent insulating substrate 22, a gate wiring 12 including a gate pad 10 at one end in a first mask process; A gate electrode 14 protruding from the gate line 12 is formed.

  As the gate electrode material, various conductive metals such as aluminum (Al), aluminum alloy, molybdenum (Mo), tungsten (W), and chromium (Cr) can be used. In particular, aluminum (Al) and aluminum are used. When an alloy is used, it is composed of a double layer using molybdenum (Mo), chromium (Cr) or the like.

  A gate insulating film 16 that is a first insulating film, a pure amorphous silicon layer 18, an impurity amorphous silicon layer 20, and a substrate 22 on which the gate wiring 12, the gate pad 10, and the gate electrode 14 are formed. Then, the second metal layer 24 is laminated.

At this time, the gate insulating layer 16 is formed by depositing one selected from an inorganic insulating material group including silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ), and the second metal layer 24. Is formed by depositing one selected from conductive metal materials such as chromium (Cr), molybdenum (Mo), tungsten (W), and tantalum (Ta).

  Next, as shown in FIGS. 3B, 4B, and 5B, a photoresist (photo-resist: hereinafter referred to as “PR” layer) is applied on the second metal layer 24 to form a PR layer 26. To do. At this time, the PR layer 26 uses a positive type in which a portion receiving light is exposed and developed. A mask 70 including a transmission region A, a blocking region B, and a semi-transmission region (slit region) C is disposed on the substrate 22 on which the PR layer 26 is formed.

  The semi-transmissive region C is disposed corresponding to the upper portion of the gate electrode 14, and the blocking region B corresponds to a position where data wiring, source and drain electrodes, data pads, and storage capacitor electrodes are formed. . At this time, the PR layer 26 corresponding to the semi-transmissive region C has a characteristic that only a part is exposed as compared with the transmissive region A.

  Subsequently, an exposure process for irradiating light on the mask 70 and a development process for removing the exposed portion are performed. If the process as described above is performed, the PR pattern 26a is formed as shown in FIGS. 3C, 4D, and 5D. Here, the PR pattern 26a has a first thickness corresponding to the blocking region B and a second thickness corresponding to the semi-transmissive region C of the mask (70 in FIGS. 3B, 4B, and 5B).

  Subsequently, after the second metal layer 24 exposed between the PR patterns 26a is etched by a wet etching method, the lower impurity amorphous silicon layer 20 and the pure amorphous silicon layer 18 are removed by dry etching. 3D, 4D, and 5D, the source / drain electrode pattern 28, the data wiring (34 in FIG. 2) extending from the source / drain electrode pattern 28, and one end of the data wiring 34 are formed. The data pad 36, the impurity semiconductor pattern 32a, and the active layer 30 to be disposed are formed. At the same time, an island-shaped metal pattern 38 is formed on a part of the gate wiring 12.

  On the other hand, the first pattern 35 is formed of the patterned pure amorphous silicon layer and the impurity amorphous silicon layer, and extends below the data line 34 and the data pad 36. The island pattern is formed below the metal pattern 38. A second pattern 29 having a shape is formed.

  Next, as shown in FIGS. 3E, 4E, and 5E, an ashing process is performed to remove the PR pattern 26a having the second thickness. If the ashing process is performed, the PR pattern 26a having the second thickness above the gate electrode 14 is removed, and the source / drain electrode pattern 28 is exposed. At this time, the edge of the PR pattern 26a is also scraped to expose the lower metal patterns 28, 38, and 36.

  Subsequently, the source / drain electrode pattern (28 in FIG. 3E) which is a metal layer exposed between the PR patterns 26a and the impurity semiconductor pattern (32a in FIG. 3E) which is an impurity amorphous silicon layer thereunder are dry-etched. A process of removing the active layer 30 is performed by performing a process of removing through the active layer 30.

  At this time, when the metal layer exposed between the PR patterns 26a is molybdenum (Mo), as described above, the metal layer exposed by dry etching and the impurity amorphous silicon layer underneath are removed at once. However, when the metal layer is chromium (Cr), the metal layer exposed between the PR patterns is first removed through wet etching, and then dry etching is performed to remove the impurity amorphous silicon below the metal layer. A step of removing the layer is performed. Here, the edge of the metal layer and the impurity amorphous silicon layer is also removed, and the lower pure amorphous silicon layer appears.

  Through these steps, as shown in FIGS. 3F, 4F, and 5F, the source electrode 40 and the drain electrode 42 that are separated from each other are formed, and the ohmic contact layer 32 is formed to expose the active layer 32. . The exposed active layer 32 becomes a channel CH of the thin film transistor.

  As described above, the island-like metal pattern 38 is formed on the active layer 32, the source electrode 40, the drain electrode 42, the data wiring 34, the data pad 36, and the gate wiring 12 through the second mask process.

Subsequently, benzocyclobutene (BCB) and acrylic resin (acrylic resin) are formed on the entire surface of the substrate 22 on which the source electrode 40, the drain electrode 42, the data wiring 34, the data pad 36, and the island-shaped metal pattern 38 are formed. selected from the group of transparent organic insulating materials including resin, and selected from the group of inorganic insulating materials including silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ). The protective film 46, which is a second insulating film, is formed by depositing one of them.

  Next, the protective film 46 is patterned in a third mask process, and a drain contact hole 48 exposing a part of the drain electrode 42, a storage contact hole 50 exposing a part of the metal pattern 38, A gate pad contact hole 52 and a data pad contact hole 54 exposing a part of the gate pad 10 and the data pad 36 are formed.

3G, 4G and 5G, a transparent conductive metal material containing indium-tin-oxide (ITO) and indium-zinc-oxide (IZO) on the protective layer 46 is formed. A transparent pixel electrode 56 that is in contact with the island-like metal pattern 38 through the pixel region P while contacting the drain electrode 42 while depositing a selected one of them and patterning in a fourth mask process; A gate pad terminal 58 in contact with the gate pad 10 and a data pad terminal 60 in contact with the data pad 36 are formed.
An array substrate for a liquid crystal display device according to a conventional method can be manufactured by the process as described above (for example, see Patent Document 1) .
Korean Patent Publication 2000-34859

  The present invention has been devised for the purpose of further simplifying the above-described four-mask process to secure an improved process yield and reduce material costs, and the array substrate manufacturing method according to the present invention is a half-process. While using a halftone mask, a step of patterning a protective film for protecting the thin film transistor into a predetermined shape and using the mask as a mask to etch the lower gate insulating film, the pixel electrode, the gate pad terminal, and the data A process for forming pad terminals is performed, and an array substrate for a liquid crystal display device is manufactured in a three-mask process.

An array substrate for a liquid crystal display device according to the present invention for achieving the object as described above is configured on a substrate and includes a gate wiring including a gate pad at one end; and the gate wiring is perpendicular to an insulating film. A data line including a data pad at one end; defining a pixel region by intersecting; a thin film transistor including an active layer, a gate electrode, a source electrode, and a drain electrode formed at an intersection of the gate line and the data line; A part of the drain electrode, the gate pad, the data pad, a protective film exposing the substrate corresponding to the pixel region; and a contact with the exposed drain electrode. While the transparent pixel electrode configured in the pixel region, the transparent gate pad terminal in contact with the exposed gate pad, and the exposed A transparent data pad terminal contacting the data pad; and a said protective layer upper to consist of the pixel electrode and the same material conductive pattern.

  Here, the protective film may have a reverse tapered side surface, and the surface of the protective film may have an arc shape.

  The protective film is patterned, and the pixel electrode, the gate pad terminal, and the data pad terminal are disposed between the patterns of the protective film.

  The pixel electrode may be in contact with a substrate located in the pixel region.

  An amorphous silicon layer and an amorphous silicon layer containing impurities are stacked below the data line and the data pad. At this time, the data wiring and the amorphous silicon layer under the data pad are formed with exposed edges.

  An island-shaped metal pattern may be further included on a part of the gate wiring, and the protection film is configured to expose a part of the island-shaped metal pattern. The pixel electrode is in contact with the exposed metal pattern, and the metal pattern forms a storage capacitor together with the gate wiring.

  The active layer may have the same shape as the source and drain electrodes, and may further include a portion corresponding to the source and drain electrodes.

  The array substrate for a liquid crystal display according to the present invention may further include an inorganic insulating pattern disposed between the thin film transistor, the gate line and the data line and the protective film, and having the same shape as the protective film.

A method of manufacturing an array substrate for a liquid crystal display device according to the present invention includes: a first mask process for forming a gate wiring including a gate pad on one end; and a gate electrode extending from the gate wiring; A pixel region is defined by vertically intersecting with a film interposed therebetween, a data line including a data pad at one end, a source electrode extending from the data line, a drain electrode spaced apart from the source electrode, and a source and drain electrode A second mask process for forming an active layer underneath the substrate; forming a protective film on the entire surface of the substrate on which the source and drain electrodes and the data wiring are formed, and patterning to form a part of the drain electrode, a pixel region, and a gate; step side of the protective film is fired so attached inversely tapered; third mask process to expose the pad and data pad and is the patterned Mamorumaku entire surface by depositing a transparent conductive metal, which is constituted by the pixel electrode and the same substance, a pixel electrode formed in the pixel region while being in contact with the drain electrode the exposed, a gate pad the exposed Forming a gate pad terminal in contact with the exposed data pad and a data pad terminal in contact with the exposed data pad;

  Forming a gate insulating film on the entire surface of the substrate on which the gate wiring and the gate electrode are formed; a pure amorphous silicon layer and an impurity amorphous silicon layer on the gate insulating film; Forming a metal layer sequentially; forming a photoresist pattern having a first thickness and a second thickness smaller than the first thickness on the metal layer; and Selectively etching the impurity amorphous silicon layer and the pure amorphous silicon layer; removing the photoresist pattern having the second thickness; and a photoresist pattern having the second thickness. Selectively etching away the exposed metal layer and the impurity amorphous silicon layer; and removing the remaining photoresist pattern Including that stage.

Before Symbol protective film can have a surface of the arc (circular arc) form.

  A pure amorphous silicon layer and an amorphous silicon layer containing impurities may be stacked under the data line and the data pad. At this time, the edge of the data wiring and the pure amorphous silicon layer below the data pad may be exposed.

  The second mask process may further include a step of forming an island-shaped metal pattern on a part of the gate line, and the protective layer is formed to expose a part of the island-shaped metal pattern. Is done. The pixel electrode is in contact with the exposed metal pattern, and the metal pattern forms a storage capacitor together with the gate wiring and the gate insulating film.

  The second mask process may use a mask including a blocking part, a semi-transmissive part, and a transmissive part, and the semi-transmissive part may include a slit.

  The photoresist pattern may be a positive type in which a portion exposed to light is removed after development.

  The active layer has the same form as the source and drain electrodes, and further includes a portion corresponding to the source and drain electrodes.

The method for manufacturing an array substrate for a liquid crystal display according to the present invention further comprises forming an inorganic insulating film on the entire surface of the substrate including the data wiring and the source and drain electrodes. Thus, it can be patterned to have the same form as the protective film. In this case, the method may further include a step of removing the protective film after the step of forming the pixel electrode, the gate pad terminal, and the data pad terminal, and the protective film may be removed by a lift-off method.

  If the array substrate is manufactured by the three-mask process according to the present invention, the material cost can be reduced and the process time can be shortened to increase the price competitiveness. Since the process error can be reduced to the maximum, the process yield is improved.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
-Examples-
A feature of the present invention is that an array substrate for a liquid crystal display device is manufactured by a three-mask process.

  FIG. 6 is a plan view schematically showing a part of an array substrate for a liquid crystal display device according to the present invention. As shown in the drawing, a gate line 102 and a data line 132 are orthogonally defined on the substrate 100 to define a pixel region P, and a thin film transistor T is formed as a switching element at the orthogonal point between the gate line 102 and the data line 132.

  A gate pad 106 is formed at one end of the gate wiring 102, a data pad 142 is formed at one end of the data wiring 132, and the pads 106 and 142 are gate pad terminals 164, which are island-shaped transparent electrode patterns. The data pad terminals 166 are configured to overlap each other in a planar manner.

  The thin film transistor T includes a gate electrode 104 that is connected to the gate line 102 and receives a scanning signal, a source electrode 136 that is connected to the data line 132 and receives a data signal, and is separated from the source electrode 136 by a predetermined distance. A drain electrode 138 is used. On the other hand, an active layer 126 made of pure amorphous silicon is located between the gate electrode 104 and the source electrode 136 and drain electrode 138.

  A pixel electrode 162 that contacts the drain electrode 138 is formed in the pixel region P, and an island-shaped metal pattern 134 is formed on a part of the gate wiring 102 that defines the pixel region P.

  The metal pattern 134 forms a storage capacitor Cst together with the lower gate wiring 102, and the gate wiring 102 has a role as a first electrode of the storage capacitor. The metal pattern 134 is in contact with the pixel electrode 162. It becomes a role as the second electrode of the storage capacitor.

  In the above-described configuration, the impurity amorphous silicon layer and the pure amorphous silicon layer are patterned in the patterning process of the source electrode 136 and the drain electrode 138, the metal pattern 134, the data wiring 132, and the data pad 142. Accordingly, a first pattern 130 extending under the data line 132 and the data pad 142 and a second pattern 131 formed under the metal pattern 134 are formed.

  At this time, the edges of the pure amorphous silicon layers of the first pattern 130 and the second pattern 131 are exposed.

  In the structure as described above, the present invention is characterized in that the protective film 160 is formed on the entire surface of the substrate 100 with only the positions where the pixel electrode 162, the data pad terminal 164, and the gate pad terminal 166 are formed exposed. Is.

  In this process, the pixel electrode 162, the data pad terminal 164, and the gate pad terminal 166 are formed using the protective film as a mask, thereby fabricating an array substrate in a three mask process. Hereafter, it can explain through a process. The manufacturing process of the liquid crystal display device according to the present invention will be described with reference to FIGS. 7A to 7H, FIGS. 8A to 8H, and FIGS. 9A to 9H.

  7A to 7H, FIG. 8A to FIG. 8H, and FIG. 9A to FIG. 9H show the process sequence of the present invention cut along the lines VII-VII, VIII-VIII, and IX-IX of FIG. It is sectional drawing. 7A to 7H are cross-sectional views of the switching region, the pixel region, and the auxiliary capacitance region. FIGS. 8A to 8H are cross-sectional views of the gate pad portion. FIGS. 9A to 9H are data pad portions. FIG.

  As shown in FIGS. 7A, 8A, and 9A, a conductive metal such as aluminum (Al), tungsten (W), molybdenum (Mo), and chromium (Cr) is deposited on the substrate 100 to form the first metal. After the layer is formed, the layer is patterned, and a gate pad 106 is formed at one end of the gate wiring 102 and the gate wiring 102 that protrudes in one direction from the gate wiring 102 in the first mask process.

  At this time, the material of the gate electrode 104, which is important for the operation of the active matrix liquid crystal display device, is mainly formed of aluminum having a low resistance in order to reduce the RC delay, but pure aluminum is chemically resistant to corrosion. In the case of aluminum wiring, it is used in the form of an alloy or a laminated structure is applied because it causes a wiring defect problem due to hillock formation in a subsequent high-temperature process.

Next, as shown in FIGS. 7B, 8B, and 9B, silicon oxide (SiO ₂ ), silicon nitride (SiN) is formed on the entire surface of the substrate 100 on which the gate wiring 102, the gate electrode 104, and the gate pad 106 are formed. _x )) and an organic insulating material such as benzocyclobutene (BCB) and an acrylic resin are deposited to form a gate insulating film 108.

  Subsequently, a pure amorphous silicon layer (a-Si: H) 110, an impurity amorphous silicon layer (n + a-Si: H) 112, and a second metal layer 114 are formed on the gate insulating film 108. . Subsequently, a photoresist (photo-resist: hereinafter referred to as PR) is applied on the second metal layer to form a PR layer 116. The second metal layer 114 is formed by depositing one selected from a conductive metal group such as chromium (Cr), molybdenum (Mo), tungsten (W), and tantalum (Ta).

  Subsequently, a mask 170 including a transmissive portion E, a blocking portion F, and a semi-transmissive portion G is disposed on the separated upper portion of the substrate 100. At this time, the blocking portion F of the mask 170 corresponds to a position where data wiring, source and drain electrodes, data pads, and storage capacitor electrodes are formed, and the transflective portion G is located above the gate electrode 104. It arranges corresponding to.

  A process of exposing and developing the PR layer 116 formed on the substrate 100 by irradiating light from above the mask 170 is performed. As a result, as shown in FIGS. 7C, 8C, and 9C, PR patterns 120a having different first and second thicknesses are formed. The second thickness corresponding to the semi-transmissive portion G of the mask 170 is formed to be thinner than the first thickness.

  Next, after the second metal layer 114, the impurity amorphous silicon layer 112, and the pure amorphous silicon layer 110 exposed between the PR patterns 120a are removed, an ashing process is performed.

  Thus, as shown in FIGS. 7D, 8D, and 9D, the data wiring 132, the source / drain metal pattern 124, the data pad 142, the impurity semiconductor pattern 128a, and the active layer 126 are formed. At this time, an island-shaped metal pattern 134 remains on the gate wiring 102.

  Meanwhile, the second thickness PR pattern 120a is removed by the ashing process, and the lower source / drain metal pattern 124 appears. Here, the first thickness of the PR pattern 120a is also partially removed to be thinned, and the PR pattern 120a at the edge is also removed to expose the lower metal layers 124, 134, and 142.

  At this time, the first pattern 130 is formed below the data line 132 and the data pad 142, and the second pattern 131 is formed below the metal pattern 134. Each of the first pattern 130 and the second pattern 131 includes lower pure amorphous silicon layers 130a and 131a and upper impurity amorphous silicon layers 130b and 131b.

Subsequently, after removing the metal exposed between the PR patterns 120a and the impurity amorphous silicon layer therebelow, a process of removing the remaining PR patterns 120a is performed.
In this way, as shown in FIGS. 7E, 8E, and 9E, the source electrode 136 and the drain electrode 138 that are spaced apart from each other by a predetermined distance are formed, and the ohmic contact layer 128 is completed. Since the metal pattern 134 serves as one electrode of the storage capacitor, it is referred to as a storage electrode.

  At this time, the lower amorphous silicon layers 130a, 126, and 131a are exposed around the data lines 132, the data pads 142, the source electrode 136, the drain electrode 138, and the storage electrode 134.

  Next, a photosensitive organic insulating film is applied on the entire surface of the substrate 100 on which the source electrode 136 and the drain electrode 138, the data wiring 132, the data pad 142, and the storage electrode 134 are formed to form a protective film 160. Examples of the photosensitive organic film include benzocyclobutene (BCB) and acrylic resin.

  Subsequently, the protective film 160 is exposed and developed in a third mask process, and covers the data wiring 132, the source electrode 136, the drain electrode 138, and the storage electrode 134 as shown in FIGS. 7F, 8F, and 9F. The gate insulating film 108 and the data pad 142 above the pixel region and the gate pad 106 are exposed. At this time, the protective film 160 also exposes part of the drain electrode 138 and the storage electrode 134.

  At this time, the patterned protective film 160 is cured at a predetermined temperature so that the surface of the protective film 160 has a round cross section (arc). That is, it should be formed so that one side of the patterned protective film 160 has an angle of less than 90 degrees, that is, a reverse taper. In order to do this, the curing may be performed separately rather than at once.

  7G, 8G, and 9G, a process of exposing the gate pad 106 by etching the gate insulating layer 108 exposed between the patterned protective layers 160 is performed. At this time, the gate insulating film 108 in the pixel region is also removed to expose the lower substrate 100.

  7H, 8H, and 9H, indium-tin-oxide (ITO) and indium-zinc-oxide (IZO) are formed on the entire surface of the substrate 100 on which the patterned protective layer 160 is formed. A gate having a shape that covers the exposed gate pad 106 and the pixel electrode 162 disposed in the pixel region while being in contact with the exposed drain electrode 138 and the storage electrode 146 by depositing a transparent conductive metal containing A pad terminal 164 and a data pad terminal 166 having a shape covering the data pad 142 are formed.

  At this time, since the side surface of the protective film 160 is formed to be reverse-tapered, the transparent electrode is cut off due to the reverse taper of the protective film even though the transparent electrode is deposited on the entire surface of the substrate 100. Each can be formed in an independent pattern without the photo-etching step. On the other hand, a transparent conductive pattern 163 made of the same material as the pixel electrode 162 is also formed on the protective film 160.

  Therefore, as described above, if it is used as a protective film mask which is a photosensitive organic film, an array substrate for a liquid crystal display device can be manufactured in three mask processes.

  In the process described above, the protective film 160 made of an organic film is directly formed on the thin film transistor T. In order to improve the contact characteristics between the protective film 160 and the active layer 126a of the thin film transistor T, An inorganic insulating film pattern can be further formed between the thin film transistors.

  Hereinafter, a description will be given with reference to FIG. 10, FIG. 11, and FIG. 10, FIG. 11, and FIG. 12 are cross-sectional views taken along lines VII-VII, VIII-VIII, and IX-IX in FIG. As shown, an inorganic insulating pattern 143 is formed between the thin film transistor T and the organic protective layer 160. The inorganic insulating pattern 143 is formed through a patterning process using the organic protective layer 160 as an etching prevention layer.

More specifically, after the source and drain electrodes 136 and 138 of the thin film transistor T and the data wiring 132 are formed, the thin film transistor T is selected from an inorganic insulating material group including silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ). One of them is deposited to form an inorganic insulating film.

  Next, as described in the above-described embodiment, the patterned organic protective film 160 is formed on the inorganic insulating film, and then the inorganic insulating film exposed between the protective films is formed using the protective film 160 as an anti-etching film. A step of etching the film and the lower gate insulating film may be performed.

  Subsequently, a transparent conductive metal containing indium-tin-oxide (ITO) and indium-zinc-oxide (IZO) is deposited on the entire surface of the substrate 100 on which the protective film 160 is formed, and the exposed drain electrode 138 is exposed. In addition, the pixel electrode 162 disposed in the pixel region P while being in contact with the storage electrode 146, the gate pad terminal 164 having a shape that covers the exposed gate pad 106, and the data pad having a shape that covers the data pad 142 A terminal 166 is formed.

  As described above, the inorganic insulating pattern 143 is further formed between the thin film transistor T, the data wiring 132, the gate wiring 102, and the protective film 160, and the inorganic film insulating film pattern 143 is more active than the organic film. Since the interface characteristic with the layer 126a is good, there is an advantage that the operation characteristic of the thin film transistor T is improved.

  Further, the inorganic insulating pattern 143 can prevent the organic protective layer 160 from being lifted above the gate and data lines 102 and 132.

Here, when the driving circuit is subsequently attached to the pads of the array substrate, a short circuit may occur between adjacent pads due to the thickness of the organic protective layer 160. Therefore, it is desirable to remove the organic protective film 160 in order to prevent such a short circuit. The organic passivation layer 160 can be removed by a liftoff method. That is, the organic protective film 160 is removed by immersing the array substrate in a stripper for the organic protective film 160, and the transparent conductive pattern 163 on the organic protective film 160 is removed because the organic protective film 160 is removed. Will come off the array substrate.
The array substrate for a liquid crystal display device according to the present invention can be manufactured through the processes as described above.

It is the top view which showed the general liquid crystal display device schematically. It is the enlarged plan view which showed a part of conventional array substrate for liquid crystal display devices roughly. It is process sectional drawing explaining the conventional process sequence cut | disconnected along the III-III line of FIG. It is process sectional drawing explaining the process sequence following FIG. 3A. It is process sectional drawing explaining the process sequence following FIG. 3B. It is process sectional drawing explaining the process sequence following FIG. 3C. It is process sectional drawing explaining the process sequence following FIG. 3D. It is process sectional drawing explaining the process sequence following FIG. 3E. It is process sectional drawing explaining the process sequence following FIG. 3F. It is process sectional drawing explaining the conventional process sequence cut | disconnected along the IV-IV line of FIG. It is process sectional drawing explaining the process sequence following FIG. 4A. It is process sectional drawing explaining the process sequence following FIG. 4B. It is process sectional drawing explaining the process sequence following FIG. 4C. It is process sectional drawing explaining the process sequence following FIG. 4D. It is process sectional drawing explaining the process sequence following FIG. 4E. It is process sectional drawing explaining the process order following FIG. 4F. It is process sectional drawing explaining the conventional process sequence cut | disconnected along the VV line | wire of FIG. It is process sectional drawing explaining the process sequence following FIG. 5A. It is process sectional drawing explaining the process sequence following FIG. 5B. It is process sectional drawing explaining the process sequence following FIG. 5C. It is process sectional drawing explaining the process sequence following FIG. 5D. It is process sectional drawing explaining the process sequence following FIG. 5E. It is process sectional drawing explaining the process sequence following FIG. 5F. It is the enlarged plan view which expanded a part of array substrate for liquid crystal display devices by this invention. It is process sectional drawing explaining the process sequence of this invention cut | disconnected along the VII-VII line of FIG. It is process sectional drawing explaining the process sequence following FIG. 7A. It is process sectional drawing explaining the process sequence following FIG. 7B. It is process sectional drawing explaining the process sequence following FIG. 7C. It is process sectional drawing explaining the process sequence following FIG. 7D. It is process sectional drawing explaining the process sequence following FIG. 7E. It is process sectional drawing explaining the process sequence following FIG. 7F. It is process sectional drawing explaining the process sequence following FIG. 7G. It is process sectional drawing explaining the process order of this invention cut | disconnected along the VIII-VIII line of FIG. It is process sectional drawing explaining the process sequence following FIG. 8A. It is process sectional drawing explaining the process sequence following FIG. 8B. It is process sectional drawing explaining the process sequence following FIG. 8C. It is process sectional drawing explaining the process sequence following FIG. 8D. It is process sectional drawing explaining the process sequence following FIG. 8E. It is process sectional drawing explaining the process sequence following FIG. 8F. It is process sectional drawing explaining the process sequence following FIG. 8G. It is process sectional drawing explaining the process sequence of this invention cut | disconnected along the IX-IX line of FIG. It is process sectional drawing explaining the process sequence following FIG. 9A. It is process sectional drawing explaining the process sequence following FIG. 9B. It is process sectional drawing explaining the process sequence following FIG. 9C. It is process sectional drawing explaining the process sequence following FIG. 9D. It is process sectional drawing explaining the process order following FIG. 9E. It is process sectional drawing explaining the process sequence following FIG. 9F. It is process sectional drawing explaining the process sequence following FIG. 9G. FIG. 7 is a cross-sectional view taken along the line VII-VII of FIG. 6, showing an array substrate for a liquid crystal display device according to another embodiment of the present invention. FIG. 8 is a cross-sectional view taken along the line VII-VIII of FIG. 6 showing an array substrate for a liquid crystal display device according to another embodiment of the present invention. FIG. 7 is a cross-sectional view taken along the line IX-IX of FIG. 6 showing an array substrate for a liquid crystal display device according to another embodiment of the present invention.

Explanation of symbols

  100: substrate, 102: gate wiring, 104: gate electrode, 106: gate pad, 134: storage, 136: source electrode, 138: drain electrode, 132: data wiring, 142: data pad, 160: protective film, 162: Pixel electrode, 164: gate pad terminal, 166: data pad terminal.

Claims (27)

Gate wiring configured on a substrate and including a gate pad at one end;
A data line including a data pad at one end, defining a pixel region perpendicularly intersecting the gate line with an insulating film in between;
A thin film transistor including an active layer, a gate electrode, a source electrode, and a drain electrode configured at an intersection of the gate wiring and the data wiring;
A protective film that is formed on the entire surface of the substrate on which the thin film transistor is formed, and that exposes a portion of the drain electrode, the gate pad, the data pad, and the substrate corresponding to the pixel region;
A transparent pixel electrode configured in a pixel region while being in contact with the exposed drain electrode; a transparent gate pad terminal in contact with the exposed gate pad; and a transparent data pad terminal in contact with the exposed data pad; ;
An array substrate for a liquid crystal display device, comprising a conductive pattern made of the same material as the pixel electrode on the protective film .   The array substrate for a liquid crystal display device according to claim 1, wherein the protective film has a reverse tapered side surface.   The array substrate for a liquid crystal display device according to claim 1, wherein the protective film has an arc-shaped surface.   The array substrate for a liquid crystal display device according to claim 1, wherein the protective film is patterned, and the pixel electrode, the gate pad terminal, and the data pad terminal are disposed between the patterns of the protective film.   The array substrate for a liquid crystal display device according to claim 1, wherein the pixel electrode is in contact with a substrate located in the pixel region.   2. The array for a liquid crystal display device according to claim 1, wherein an amorphous silicon layer and an amorphous silicon layer containing impurities are laminated below the data line and the data pad. substrate.   7. The array substrate for a liquid crystal display device according to claim 6, wherein the amorphous silicon layer under the data line and the data pad is configured with an exposed edge.   2. The array substrate for a liquid crystal display device according to claim 1, wherein an island-shaped metal pattern is further formed on a part of the gate wiring.   9. The array substrate for a liquid crystal display device according to claim 8, wherein the protective film is configured to expose a part of the island-shaped metal pattern.   The array substrate of claim 9, wherein the pixel electrode is in contact with the exposed metal pattern, and the metal pattern forms a storage capacitor together with the gate wiring.   2. The array substrate for a liquid crystal display device according to claim 1, wherein the active layer has the same form as the source and drain electrodes, and further includes a portion corresponding to the source and drain electrodes.   2. The array for a liquid crystal display device according to claim 1, further comprising an inorganic insulating pattern disposed between the thin film transistor, the gate line and the data line and the protective film, wherein the protective film has the same shape. substrate. A first mask process for forming a gate wiring including a gate pad at one end and a gate electrode extending from the gate wiring on the substrate;
The gate line defines a pixel region that intersects perpendicularly with an insulating film in between, a data line including a data pad at one end, a source electrode extending from the data line, and a drain electrode spaced apart from the source line by a predetermined distance And a second mask process for forming an active layer under the source and drain electrodes;
Forming a protective film on the entire surface of the substrate on which the source and drain electrodes and the data wiring are formed, and patterning to expose a part of the drain electrode, the pixel region, the gate pad, and the data pad;
Baking the side surfaces of the protective film so as to be reverse-tapered; and depositing a transparent conductive metal made of the same material as the pixel electrode on the entire surface of the patterned protective film to expose the exposed drain. Forming a pixel electrode formed in a pixel region in contact with the electrode, a gate pad terminal in contact with the exposed gate pad, and a data pad terminal in contact with the exposed data pad. A method for manufacturing an array substrate for a liquid crystal display device. Forming a gate insulating film on the entire surface of the substrate on which the gate wiring and the gate electrode are formed; a pure amorphous silicon layer and an impurity amorphous silicon layer on the gate insulating film; Forming a metal layer sequentially; forming a photoresist pattern having a first thickness and a second thickness smaller than the first thickness on the metal layer; and Selectively etching the impurity amorphous silicon layer and the pure amorphous silicon layer; removing the photoresist pattern having the second thickness; and a photoresist pattern having the second thickness. Selectively etching away the exposed metal layer and the impurity amorphous silicon layer; and removing the remaining photoresist pattern The liquid crystal display device for an array substrate manufacturing method according to claim 13, characterized in that it comprises a that step. The method for manufacturing an array substrate for a liquid crystal display device according to claim 13 , wherein the protective film has an arc-shaped surface. 14. The method according to claim 13 , wherein a pure amorphous silicon layer and an amorphous silicon layer including impurities are stacked under the data lines and the data pads. Method. 17. The method according to claim 16 , wherein edges of the pure amorphous silicon layer below the data lines and the data pads are exposed. The method of claim 17 , wherein the second mask process further includes a step of forming an island-shaped metal pattern on a part of the gate line. 19. The method of manufacturing an array substrate for a liquid crystal display device according to claim 18 , wherein the protective film is formed so as to expose a part of the island-shaped metal pattern. The array substrate of claim 19 , wherein the pixel electrode is in contact with the exposed metal pattern, and the metal pattern forms a storage capacitor together with the gate wiring and the gate insulating film. Production method. The method of claim 13 , wherein the second mask process uses a mask including a blocking part, a semi-transmissive part, and a transmissive part. The method for manufacturing an array substrate for a liquid crystal display device according to claim 21 , wherein the semi-transmissive portion includes a slit. The method according to claim 13 , wherein the photoresist pattern is a positive type in which a portion exposed to light is removed after development. 14. The method of claim 13 , wherein the active layer has the same shape as the source and drain electrodes, and further includes a portion corresponding to the source and drain electrodes. Method. The method further includes forming an inorganic insulating film on the entire surface of the substrate including the data wiring and the source and drain electrodes, and the inorganic insulating film is patterned using the protective film as an etching prevention film to have the same form as the protective film. 14. The method for manufacturing an array substrate for a liquid crystal display device according to claim 13 , further comprising: 26. The method of claim 25 , further comprising removing the protective film after forming the pixel electrode, the gate pad terminal, and the data pad terminal . 27. The method of manufacturing an array substrate for a liquid crystal display device according to claim 26 , wherein the protective film is removed by a lift-off method.

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