1293015 (1) 九、發明說明 【發明所屬之技術領域】 本發明有關一種多層印刷配線板’其係應用於不同的 電子電路，以及有關一種多層印刷配線板之製造方法。 【先前技術】 由交替堆疊之多數絕緣層（樹脂片）及核心板（銅箔 披覆積層板）所形成之多層印刷配線板係經常使用於包含 資訊處理器之不同的小型電子裝置中。除了配線圖案之外 ，此形式之多層印刷配線板具有延伸穿過該堆疊之印刷配 線板的貫穿孔，並未延伸穿過該印刷配線板之盲導孔’及 類似物。 用以於多層印刷配線板中形成肓導孔之傳統技術實例 包含如日本專利申請案公開公告第8 — 3 223 3號中所揭示 者，亦即，用以形成導體層於導孔形成部分周圍（包圍孔 形成部分）之技術以及使包圍該導孔形成部分之絕緣層薄 化之技術。該技術針對當從絕緣層朝向核心板構件鑽孔且 使孔之末端鄰接抵頂著核心板構件中所形成之內層焊墊（ land )以形成盲導孔時，由於電鍍層之熱膨脹係數與絕緣 層之熱膨脹係數間之差異所產生之熱應力，而降低在肓導 孔內壁上之電鍍層中所造成的破裂。如上述，傳統技術之 目的在於藉由使絕緣層之膜厚度小於從絕緣層朝向核心板 構件鑽孔所形成之盲導孔而降低由於電鍍層之熱膨脹係數 與絕緣層之熱膨脹係數間之差異，所產生之熱應力在盲導 -4- (2) (2)1293015 孔內壁上之電鍍層中所造成的破裂。 然而，並沒有用以改善藉鑽孔及使鑽孔方向中之孔的 末端鄰接抵頂核心板構件中所形成之焊墊以形成具有預定 直徑之盲導孔的傳統盲導孔處理技術中之產能的有效技術 〇 尤其，近年來，高密度配線漸增地使印刷配線板之信 號圖案薄化。爲形成薄的信號圖案（配線圖案），企望於 就有關圖案形成及產能來降低該配線圖案之厚度（導體厚 度）。通常，在盲導孔襯裡之焊墊係藉圖案蝕刻法或類似 法同時地隨著同一層之配線圖案形成。爲此理由，配線圖 案之厚度降低會導致相對應之導孔襯裡焊墊的導體厚度降 低，假設盲導孔襯裡焊墊之導體厚度減少於用以藉鑽孔於 核心板構件中及使鑽孔方向中之孔的末端鄰接抵頂核心板 構件中所形成之焊墊以形成孔之盲導孔處理技術中，則在 此例子中，鑽孔深度控制大大地影響正常的盲導孔形成， 且產能會減少。更特別地，若核心板構件中所形成之孔係 淺的時候，故障會由於未連接之電路而發生；另一方面， 若孔係深的時候，故障會由於電路圖案在鑽孔方向中之末 端處與另一層連接而發生。現今地，通常使用一種利用絕 緣層當作表面層之堆疊結構，在各絕緣層之深度方向中之 尺寸的準確性會低於各核心板之尺寸的準確性，因而，上 述問題將呈顯著。 如上述，根據用以藉鑽孔及使鑽孔方向中之孔的末端 鄰接抵頂核心板構件所形成之焊塾以形成盲導孔之形成孔 -5- (3) (3)1293015 的傳統盲導孔處理技術，鑽孔深度控制會大大地影響正常 的盲導孔形成，且因此已成爲有關肓導孔處理之產能及促 成中之問題。 【發明內容】 本發明已顧及上述情況而完成，且具有目的在於提供 一種多層印刷配線板，其中形成可靠的肓導孔，以及提供 一種多層印刷配線板之製造方法，其可易於形成可靠的盲 導孔。 根據本發明，提供有一種多層印刷配線板，其中盲導 孔係藉鑽孔及使鑽孔方向中之孔的末端鄰接抵頂核心板構 件中所形成之焊墊而形成孔於該核心板構件中，包含：核 心板；配線圖案，形成於該核心板中；焊墊，用以襯裡盲 導孔，其係形成於該核心板中，以便自該配線圖案之表面 突出且具有大的厚度；以及盲導孔，其係形成於以一表面 相對於該焊墊的核心板之中，使得在鑽孔方向中之該盲導 孔之末端鄰接抵頂著該襯裡焊墊。 此外，根據本發明，提供有一種印刷電路板之製造方 法，包含：形成一襯裡盲導孔之焊墊及一配線圖案於一核 心板構件中；藉由從一相對於其中形成該焊墊之該核心板 構件的一表面之表面鑽孔形成一具有預定直徑之孔，電鑛 所形成之孔的內壁及鄰接抵頂該孔之焊墊的表面；以及形 成一盲導孔於該核心板構件中貫穿一絕緣層，其中襯裡以 一鑽孔方向形成於該盲導孔之末端中的盲導孔之焊墊的導 -6- (4) (4)1293015 體厚度係製成比該配線圖案之厚度更大。 此安排可容易地且高產能地實現一種多層印刷配線板 ，其中一具有預定之孔藉鑽孔而形成於一核心板構件中， 在鑽孔方向中之孔的末端係製成鄰接抵頂一形成於該核心 板構件中之焊墊，以及一盲導孔形成，其中形成一可靠的 盲導孔。 本發明之另外的目的及優點將呈明於隨後之說明書中 ，且部分將呈明顯於說明書，或可藉本發明之實施而習得 。尤其，本發明之目的及優點可利用下文中所指出之手段 及組合而予以實現及達成。 【實施方式】 本發明之實施例將參照附圖圖式予以說明。 在本發明中，當盲導孔藉鑽孔及使鑽孔方向中之孔的 末端鄰接抵頂核心板構件中所形成之焊墊，而形成一具有 預定直徑於該核心板構件中之孔而形成時，該核心板構件 之該焊墊（盲導孔襯裡焊墊）係形成以具有一比該核心板 構件中所形成之配線圖案之厚度更大的厚度。此安排可增 加深度方向中之孔所需之尺寸準確性，以及確保一足夠大 的接合區域於該盲導孔與該襯裡焊墊之間，本發明可易於 以高的產能形成可靠的盲導孔。 第1圖顯示根據本發明第一實施例之多層印刷配線板 1 A中之盲導孔的結構。該多層印刷配線板1 A包含^層， 該η層藉在一壓力與溫度下交替堆疊多數絕緣層（樹脂片 -7- (5) (5)1293015 漬）1 8及多數核心板構件（銅箱披覆積層板）i 〇而形成 ，具有η層結構之多層印刷配線板1 A具有延伸穿過所有 層之貫穿孔13，各僅延伸至一預定層之盲導孔11，以及 配線圖案1 4。 第1圖中所示之多層印刷配線板1 A具有焊墊1 2 (# 1 )及12 ( #2 )，其分別襯裡盲導孔1 1 ( #1 )及1 1 ( #2 ) 於一安排於第二層L ( 2 )與第三層L ( 3 )間之核心板構 件10(2)中以及一安排於第（η — 1)層L(n-l)與第 (η — 2 )層L ( η — 2 )間之核心板構件1 0 ( η — 2 )中，該 盲導孔1 1 ( # 1 )及1 1 ( #2 )分別電路連接第一層L ( 1 ) 與第三層L(3)以及第η層L(n)與第（η — 2)層L(n —2 )。 襯裡盲導孔1 1 (# 1 )及1 1 ( #2 )之各該等焊墊1 2 ( #】）及1 2 ( #2 )(下文稱爲”導孔襯裡焊墊”）係形成以具 有一大於相對應配線圖案1 4之厚度，例如使Th ( 3 )爲 第三層L ( 3 )之配線圖案1 4 ( 3 )之導體厚度，在此例子 中，具有導體厚度TH(#1)大於導體厚度Th(3)之導 孔襯裡焊墊1 2 (# 1 )係形成於相對應層之核心板構件1 〇 (3 )中；相類似於第三層 L ( 3 )，具有導體厚度 TH ( #2 )大同一層之相對應配線圖案1 4之導體厚度Th ( η — 2 )的導孔襯裡焊墊1 2 ( #2 )則形成於第（η — 2 )層L ( η —1 )對應層中。 該配線圖案1 4之導體厚度Th之實例爲1 8微米（// m )或3 5微米。較佳地，導孔襯裡焊墊1 2之導體厚度約爲 -8- (6) (6)1293015 1 . 5至3.0倍大於配線圖案1 4之導體厚度Th。若一配線圖 案14之導體厚度Th爲1 8微米，則相對應之盲孔襯裡焊 墊之導體厚度TH較佳地爲35微米；另一方面’若一配線 圖案1 4之導體厚度Th爲3 5微米，則相對應之盲孔襯裡 焊墊之導體厚度TH較佳地爲7 0微米。在此例子中，相對 應層L之厚度爲1〇〇至200微米，藉堆疊該10層L所形 成之多層印刷配線板1A具有1.2毫米（mm)至1.4毫米 之厚度。該等値僅係實例，而本發明並未受限於此。 具有預定直徑之孔係藉分別鑽孔於核心板構件1 〇 ( 2 )及1 0 ( η - 2 )中至大的深度以便到達導孔襯裡焊墊1 2 (# 1 )及1 2 ( #2 )而形成，其分別具有導孔襯裡焊墊1 2 (#1)及12( #2)，穿過平面方向中之絕緣層18(1)及 1 8 ( η )而相對於導孔襯裡焊墊1 2 ( # 1 )及1 2 ( #2 )，該 等孔之內壁覆蓋有預定之電鍍部分19(#1)及19(#2) 。具有此安排，可形成分別連接第一層L(l)與第三層L (3)以及第n層L(n)與第（η — 2)層之盲導孔11 (#1 )及1 1 ( #2 )。第8圖描繪所鑽孔之配線板的剖面之實例 ;第9圖描繪在鑽孔之後接受電鍍步驟之配線板的剖面實 例。 如上述，該等導孔焊墊1 2 ( #〗）及1 2 ( #2 )之導體 厚度ΤΗ ( #1 )及ΤΗ ( #2 )係製成大於相對應層之配線圖 案14(3)及Ι4(η— 2)的導體厚度Th(3)及Th(n — 2 )，[Th ( 3 ) <TH ( #1 ) ，Th(n— 2)<TH(#2)〕。具 有此安排’可增加鑽孔所需深度方向中之尺寸準確性的公 -9- (7) (7)1293015 差，且可一直以局產能來製造具有可靠肓導孔之多層印刷 配線板。 如上述，各導孔襯裡焊墊1 2之導體厚度TH係製成比 相對應層之配線圖案14的導體厚度Th更大（Th<TH )。 此增加了盲導孔1 1中之導孔襯裡焊墊1 2的接合區域，及 可形成具有低電阻且係穩定的盲導孔電路。同時，可降低 各配線圖案1 4之導體厚度Th而無需任何考慮於相對應導 孔襯裡焊墊1 2之導體厚度TH，此造成該多層印刷配線板 1 A之厚度中的降低。在根據此實施例之盲導孔結構中， 各盲導孔係形成於核心板構件1 0中所形成之孔中，爲此 理由’可不似先前技術地形成免於由於該盲導孔內壁上之 電鍍部分1 9的熱膨脹係數與絕緣層1 8之熱膨脹係數間的 差異所造成之熱應力之電鍍部分1 9破裂的可靠盲導孔。 第3至7圖顯示形成具有導體厚度TH大於配線圖案 1 4之導體厚度Th的導孔襯裡焊墊1 2中之處理的實例。 第3至7圖中所示之步驟描繪其中如上述之厚的導孔襯裡 焊墊形成於作用爲核心板構件1 0之銅包覆疊層3 0之兩面 上的例子。 在處理導孔襯裡焊墊之步驟中，如第3圖中所示，蝕 刻該銅包覆疊層30之兩表面上之各表面的銅箔31;如第 4圖中所示，配線圖案3 i 一 }，3 ! — 2，3 1 — 3，及3 1 — 4 以及作用爲如上述之導孔襯裡焊墊之基底的焊墊3 2 - 1及 3 2— 2係同時形成於各表面；如第5圖中所示，一足台40 印刷導電糊4 1 一 1於焊墊3 2 — 1上；如第6圖中所示，該 -10- (8) (8)1293015 足台40印刷導電糊41 — 2於焊墊32 — 2上；如第7圖中 所示，使印刷之導電糊4 1 — 1及4 1 一 2硬化。透過此系列 之步驟，僅襯裡相對應盲導孔1 1之各導孔襯裡焊墊1 2的 導體厚度可增加。 第2圖顯示根據本發明第二實施例之多層印刷配線板 1 B中之盲導孔的結構。不似第一實施例地，該多層印刷 配線板1 B具有表面層之核心板構件2 0以及包含η層，該 η層藉交互堆疊絕緣層（預浸漬）2 8及核心板構件2 〇而 形成，具有η層結構之多層印刷配線板丨Β具有延伸穿過 所有層之貫穿孔2 3，形成於作用爲表面層之核心板構件 20中之盲導孔21 ( #1 )及21 ( #2 )，以及配線圖案24 ( 1 )至 24 ( η)。 第2圖中所示之多層印刷配線板！ β具有焊墊2 2 (# 1 )及22 ( #2 )，其分別襯裡盲導孔21 ( #1 )及21 ( #2 ) 於一安排於作用爲表面層之第一層L(l)與一第二層L( 2)間之核心板構件2 0 ( 1 )中以及一安排於一作用爲表面 層之第η層L ( η )與一第（η — 1 )層L ( η — 1 )間之核心 板構件20 ( η — 1 )中，該盲導孔21 ( #1 )及21 ( #2 )分 別電路連接第一層L(l)與第二層L(2)以及第η層L (η)與第 η— 1 層 L(n— 1)。 同樣地，在第二實施例中，相似於第一實施例，襯裡 盲導孔21 (#1)及21 (#2)之各該等焊墊22(#1)及22 (#2 )係形成以比同一層之相對應內壁配線圖案24之厚 度更厚’此可增加形成盲導孔2 1 ( # 1 )及2 1 ( #2 )中之 -11 - (9) (9)1293015 鑽孔所需之尺寸準確性的公差，可製造具有可靠盲導孔之 多層印刷配線板。因爲各導孔襯裡焊墊22之導體厚度係 製成比相對應配線圖案24之導體厚度更大，故可增加盲 導孔2 1中之導孔襯裡焊墊22的接合區域，及可形成具有 低電阻且係穩定的盲導孔電路。同時，可降低各配線圖案 24之導體厚度而無需任何考慮於相對應導孔襯裡焊墊22 之導體厚度，此造成該多層印刷配線板1 B之厚度中的降 低。在根據此實施例之盲導孔結構中，各盲導孔2 1係形 成於核心板構件20中所形成之孔中，爲此理由，可不似 先前技術地形成免於由於該盲導孔內壁上之電鍍部分1 9 的熱膨脹係數與絕緣層之熱膨脹係數間的差異所造成之熱 應力之電鍍部分1 9破裂的可靠盲導孔。 額外的優點及修正將立即產生於該等熟習於本項技術 中之人士，因此，在其廣義觀點中之本發明並未受限於本 文中所顯示及說明之特定細節及代表性之實施例。因此， 種種修正可予以完成而不會背離如附錄申請專利範圍及其 等效例所界定之全部發明觀點的精神及範疇。 【圖式簡單說明】 結合上述槪略說明及下文較佳實施例詳細說明之結合 及建構一部分本說明書之附圖將描繪本發明之現行較佳例 且作用爲解說明本發明之原理，其中 第1圖係剖視圖，顯示根據本發明第一實施例之多層 印刷配線板之安排的實例； -12 - (10) (10)1293015 第2圖係剖視圖，顯示根據本發明第二實施例之多層 印刷配線板之安排的實例； 第3圖係圖式，用以解說根據本發明實施例之形成導 孔襯裡焊墊中之蝕刻步驟的觀念； 第4圖係圖式，用以解說根據本發明實施例之形成導 孔襯裡焊墊中之焊墊形成步驟的觀念； 第5圖係圖式，用以解說根據本發明實施例之形成導 孔襯裡焊墊中之導電糊印刷步驟的觀念； 第6圖係圖式，用以解說根據本發明實施例之形成導 孔襯裡焊墊中之導電糊印刷步驟的觀念； 第7圖係圖式，用以解說根據本發明實施例之形成導 孔襯裡焊墊中之導電糊硬化步驟的觀念； 第8圖係剖視圖，顯示其中根據本發明實施例之導孔 襯裡焊墊係藉鑽孔形成之一狀態的實例；以及 第9圖係剖視式，顯示其中根據本發明實施例之鑽孔 式導孔襯裡焊墊接受電鍍之一狀態的實例。 【主要元件之符號說明】 TH ( #1 ) ，TH ( #2 ) ，TH :導體厚度 14(3) ，1 4，3 1 — 1 〜3 1 — 4，2 4 :配線圖案[Technical Field] The present invention relates to a multilayer printed wiring board which is applied to different electronic circuits, and to a method of manufacturing a multilayer printed wiring board. [Prior Art] A multilayer printed wiring board formed by alternately stacking a plurality of insulating layers (resin sheets) and core sheets (copper foil-coated laminated sheets) is often used in different small electronic devices including information processors. In addition to the wiring pattern, the multilayer printed wiring board of this type has a through hole extending through the stacked printed wiring board, and does not extend through the blind via hole ' of the printed wiring board and the like. An example of a conventional technique for forming a via hole in a multilayer printed wiring board includes those disclosed in Japanese Laid-Open Patent Publication No. 8-3223, that is, a conductor layer is formed around a via hole forming portion. A technique of surrounding the hole forming portion and a technique of thinning the insulating layer surrounding the via forming portion. The technique is directed to the thermal expansion coefficient and insulation of the electroplated layer when drilling from the insulating layer toward the core plate member and abutting the end of the hole against the inner layer of the core plate member to form a blind via hole The thermal stress generated by the difference in thermal expansion coefficients of the layers reduces the cracking caused in the plating layer on the inner wall of the crucible. As described above, the conventional technique aims to reduce the difference between the thermal expansion coefficient of the plating layer and the thermal expansion coefficient of the insulating layer by making the film thickness of the insulating layer smaller than the blind via hole formed by drilling the insulating layer toward the core plate member. The resulting thermal stress is caused by cracking in the plating on the inner wall of the blind -4- (2) (2) 1293015 hole. However, there is no capacity for improving the conventional blind via hole processing technique by borrowing a hole and making the end of the hole in the drilling direction abut the pad formed in the top core plate member to form a blind via having a predetermined diameter. Effective Technology In particular, in recent years, high-density wiring has increasingly thinned the signal pattern of printed wiring boards. In order to form a thin signal pattern (wiring pattern), it is expected to reduce the thickness (conductor thickness) of the wiring pattern in terms of pattern formation and productivity. Generally, the pads in the blind via liner are simultaneously formed by the pattern pattern of the same layer by pattern etching or the like. For this reason, the thickness reduction of the wiring pattern may result in a decrease in the conductor thickness of the corresponding via lining pad, assuming that the conductor thickness of the blind via lining pad is reduced to be used in the core plate member and the drilling direction In the case where the end of the hole is abutted against the pad formed in the top core plate member to form a blind via hole processing technique, in this example, the drilling depth control greatly affects the formation of a normal blind via hole, and the productivity is reduced. . More specifically, if the hole formed in the core plate member is shallow, the failure may occur due to the unconnected circuit; on the other hand, if the hole is deep, the failure may occur due to the circuit pattern in the drilling direction. Occurs when the end is connected to another layer. Nowadays, a stacking structure using an insulating layer as a surface layer is generally used, and the accuracy of the dimension in the depth direction of each insulating layer is lower than the accuracy of the size of each core panel, and thus the above problem will be remarkable. As described above, the conventional blind guide is formed according to the hole formed by the hole forming hole--5-(3) (3) 1293015 by the hole formed by the hole and the end of the hole in the drilling direction adjoining the core plate member. Hole treatment technology, drilling depth control will greatly affect the formation of normal blind vias, and has therefore become a problem in the production capacity and facilitation of the treatment of the crucible. SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has an object to provide a multilayer printed wiring board in which a reliable conductive via hole is formed, and a manufacturing method of a multilayer printed wiring board which can easily form a reliable blind guide hole. According to the present invention, there is provided a multilayer printed wiring board in which a blind via hole is formed in a hole in the core plate member by drilling a hole and abutting a tip end of the hole in the drilling direction adjacent to a pad formed in the top core plate member a core board; a wiring pattern formed in the core board; a solder pad for lining a blind via hole formed in the core board to protrude from a surface of the wiring pattern and having a large thickness; and a blind guide The hole is formed in a core plate with a surface opposite to the pad such that an end of the blind via hole in the drilling direction abuts against the liner pad. Further, according to the present invention, there is provided a method of fabricating a printed circuit board comprising: forming a pad of a liner blind via and a wiring pattern in a core plate member; by forming the pad from a relative thereto The surface of a surface of the core plate member is bored to form a hole having a predetermined diameter, an inner wall of the hole formed by the electric ore and a surface adjacent to the pad abutting the hole; and a blind guide hole is formed in the core plate member Throughout an insulating layer, the thickness of the lead -6-(4) (4) 1293015 of the pad of the blind via hole formed in the end of the blind via hole in a drilling direction is made to be thicker than the thickness of the wiring pattern Big. This arrangement makes it easy and high-capacity to realize a multilayer printed wiring board in which a predetermined hole is formed in a core plate member by a drill hole, and the end of the hole in the drilling direction is made to abut against the top. A solder pad formed in the core plate member and a blind via hole are formed in which a reliable blind via hole is formed. Additional objects and advantages of the invention will be set forth in the description in the description. In particular, the objects and advantages of the invention may be realized and attained by the means and combinations disclosed herein. [Embodiment] Embodiments of the present invention will be described with reference to the drawings. In the present invention, when the blind via hole is bored and the end of the hole in the drilling direction abuts the pad formed in the top core plate member, a hole having a predetermined diameter in the core plate member is formed. The pad (blind via liner pad) of the core plate member is formed to have a thickness greater than a thickness of a wiring pattern formed in the core plate member. This arrangement increases the dimensional accuracy required for the holes in the depth direction and ensures a sufficiently large joint area between the blind vias and the liner pads. The present invention can easily form reliable blind vias with high throughput. Fig. 1 shows the structure of a blind via hole in the multilayer printed wiring board 1 A according to the first embodiment of the present invention. The multilayer printed wiring board 1 A comprises a layer which alternately stacks a plurality of insulating layers (resin sheet-7-(5) (5) 1293015 stain) 18 and a plurality of core board members (copper) under a pressure and temperature. The multi-layer printed wiring board 1A having an n-layer structure has a through-hole 13 extending through all the layers, blind via holes 11 each extending only to a predetermined layer, and a wiring pattern 14 . The multilayer printed wiring board 1 A shown in Fig. 1 has pads 1 2 (# 1 ) and 12 ( #2 ) which are respectively lined with blind via holes 1 1 ( #1 ) and 1 1 ( #2 ) In the core plate member 10(2) between the second layer L(2) and the third layer L(3) and in the (n-1)th layer L(nl) and the (η-2) layer L In the core plate member 10 ( η — 2 ) between ( η — 2 ), the blind via holes 1 1 ( # 1 ) and 1 1 ( #2 ) are respectively electrically connected to the first layer L ( 1 ) and the third layer L (3) and the nth layer L(n) and the (n-2)th layer L(n-2). Each of the pads 1 2 (#1) and 1 2 (#2) of the lining blind vias 1 1 (#1) and 1 2 (#2) (hereinafter referred to as "via lining pads") are formed There is a thickness larger than the thickness of the corresponding wiring pattern 14 such as the wiring pattern of the wiring pattern 1 4 ( 3 ) in which Th ( 3 ) is the third layer L ( 3 ), in this example, having the conductor thickness TH (#1) A via liner pad 1 2 (# 1 ) larger than the conductor thickness Th(3) is formed in the core plate member 1 〇(3) of the corresponding layer; similar to the third layer L(3), having a conductor A via liner lining pad 1 2 ( #2 ) having a thickness TH ( #2 ) which is larger than the conductor thickness Th ( η — 2 ) of the corresponding wiring pattern 14 of the same layer is formed in the (η — 2 ) layer L ( η — 1) Corresponding layer. An example of the conductor thickness Th of the wiring pattern 14 is 18 μm (// m ) or 35 μm. Preferably, the conductor thickness of the via liner pad 1 2 is about -8 - (6) (6) 1293015 1.5 to 3.0 times greater than the conductor thickness Th of the wiring pattern 14. If the conductor thickness Th of a wiring pattern 14 is 18 μm, the conductor thickness TH of the corresponding blind via lining pad is preferably 35 μm; on the other hand, if the conductor thickness Th of a wiring pattern 14 is 3 5 microns, the corresponding conductor thickness TH of the blind via liner pad is preferably 70 microns. In this example, the thickness of the corresponding layer L is 1 Å to 200 μm, and the multilayer printed wiring board 1A formed by stacking the 10 layers of L has a thickness of 1.2 mm (mm) to 1.4 mm. Such enthalpy is merely an example, and the invention is not limited thereto. Holes having a predetermined diameter are drilled into the core plate members 1 〇( 2 ) and 10 ( η - 2 ) to a large depth to reach the via lining pads 1 2 (# 1 ) and 1 2 ( # 2) formed with via lining pads 1 2 (#1) and 12 (#2), respectively, passing through the insulating layers 18(1) and 18(n) in the planar direction with respect to the via lining Pads 1 2 ( # 1 ) and 1 2 ( #2 ), the inner walls of the holes are covered with predetermined plating portions 19 (#1) and 19 (#2). With this arrangement, blind via holes 11 (#1) and 1 1 respectively connecting the first layer L (1) and the third layer L (3) and the nth layer L (n) and the (n - 2) layer can be formed. ( #2 ). Fig. 8 depicts an example of a cross section of a drilled wiring board; Fig. 9 depicts a cross-sectional example of a wiring board that receives a plating step after drilling. As described above, the conductor thicknesses # (#1) and ΤΗ(#2) of the via pads 1 2 (#) and 1 2 (#2) are made larger than the wiring patterns 14 (3) of the corresponding layers. And 导体4(η-2) conductor thicknesses Th(3) and Th(n-2), [Th(3) <TH(#1), Th(n-2)<TH(#2)]. With this arrangement, it is possible to increase the dimensional accuracy in the depth direction required for drilling, and it is possible to manufacture multilayer printed wiring boards with reliable conductive holes at a constant capacity. As described above, the conductor thickness TH of each of the via liner pads 1 2 is made larger than the conductor thickness Th of the wiring pattern 14 of the corresponding layer (Th < TH ). This increases the junction area of the via liner pad 1 2 in the blind via 1 and forms a blind via which has low resistance and is stable. At the same time, the conductor thickness Th of each of the wiring patterns 14 can be lowered without any consideration of the conductor thickness TH of the corresponding via liner pad 12, which causes a decrease in the thickness of the multilayer printed wiring board 1 A. In the blind via structure according to this embodiment, each blind via is formed in a hole formed in the core plate member 10, for which reason 'may not be formed prior to the plating on the inner wall of the blind via hole A reliable blind via that ruptures the plated portion of the thermal stress caused by the difference between the thermal expansion coefficient of the portion 19 and the thermal expansion coefficient of the insulating layer 18. Figs. 3 to 7 show an example of a process of forming a via liner pad 1 2 having a conductor thickness TH greater than the conductor thickness Th of the wiring pattern 14. The steps shown in Figs. 3 to 7 depict an example in which a via-hole lining pad having a thickness as described above is formed on both sides of the copper clad laminate 30 which functions as the core plate member 10. In the step of processing the via liner lining pad, as shown in FIG. 3, the copper foil 31 of each surface on both surfaces of the copper clad laminate 30 is etched; as shown in FIG. 4, the wiring pattern 3 i a}, 3 ! — 2, 3 1 — 3, and 3 1 - 4 and pads 3 2 - 1 and 3 2 - 2 acting as a base of the via liner pad as described above are simultaneously formed on each surface As shown in FIG. 5, a foot station 40 prints a conductive paste 4 1 -1 on the pad 3 2 - 1; as shown in Fig. 6, the -10 (8) (8) 1293015 foot table 40 The conductive paste 41-2 is printed on the pad 32-2; as shown in Fig. 7, the printed conductive pastes 4 1 - 1 and 4 1 - 2 are hardened. Through the series of steps, only the conductor thickness of each of the via-hole pads 1 2 of the corresponding blind vias 1 1 of the lining can be increased. Fig. 2 shows the structure of a blind via hole in the multilayer printed wiring board 1 B according to the second embodiment of the present invention. Unlike the first embodiment, the multilayer printed wiring board 1 B has a core layer member 20 of a surface layer and includes an n layer which is alternately stacked with an insulating layer (prepreg) 28 and a core plate member 2 The multilayer printed wiring board having the n-layer structure is formed with through holes 23 extending through all the layers, and formed in the blind via holes 21 (#1) and 21 (#2) in the core plate member 20 functioning as the surface layer. ), and wiring patterns 24 ( 1 ) to 24 ( η). Multilayer printed wiring board shown in Figure 2! β has pads 2 2 (# 1 ) and 22 ( #2 ), which respectively line the blind via holes 21 ( #1 ) and 21 ( #2 ) in a first layer L(l) which acts as a surface layer and a core layer member 20(1) between the second layer L(2) and an nth layer L(n) and a (n-1) layer L (η-1) arranged to function as a surface layer In the core plate member 20 (η-1), the blind via holes 21 (#1) and 21 (#2) are respectively electrically connected to the first layer L(1) and the second layer L(2) and the nth layer L (η) and the η - 1 layer L (n-1). Similarly, in the second embodiment, similar to the first embodiment, the pads 22 (#1) and 22 (#2) of the lining blind vias 21 (#1) and 21 (#2) are formed. It is thicker than the thickness of the corresponding inner wall wiring pattern 24 of the same layer'. This can increase the formation of the blind via holes 2 1 ( # 1 ) and -11 - (9) (9) 1293015 in the 2 1 ( #2 ) Tolerance of dimensional accuracy required, multilayer printed wiring boards with reliable blind vias can be fabricated. Since the conductor thickness of each of the via liner pads 22 is made larger than the conductor thickness of the corresponding wiring pattern 24, the junction area of the via liner pads 22 in the blind vias 21 can be increased, and the formation can be low. A resistor and a stable blind via circuit. At the same time, the conductor thickness of each of the wiring patterns 24 can be lowered without any consideration of the conductor thickness of the corresponding via liner lining pad 22, which causes a decrease in the thickness of the multilayer printed wiring board 1B. In the blind via structure according to this embodiment, each of the blind vias 21 is formed in a hole formed in the core plate member 20, and for this reason, it may not be formed as in the prior art due to the inner wall of the blind via hole. A reliable blind via hole in which the plated portion of the thermal stress caused by the difference between the thermal expansion coefficient of the plating portion 19 and the thermal expansion coefficient of the insulating layer is broken. Additional advantages and modifications will occur immediately from those skilled in the art, and thus the invention in its broad aspects is not limited to the specific details and representative embodiments shown and described herein. . Accordingly, various modifications may be made without departing from the spirit and scope of all inventions as defined by the appended claims and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be described in conjunction with the preferred embodiments of the invention 1 is a cross-sectional view showing an example of arrangement of a multilayer printed wiring board according to a first embodiment of the present invention; -12 - (10) (10) 1293015 Fig. 2 is a cross-sectional view showing multilayer printing according to a second embodiment of the present invention Example of the arrangement of the wiring board; FIG. 3 is a diagram for explaining the concept of an etching step in forming a via liner-lined pad according to an embodiment of the present invention; FIG. 4 is a diagram for explaining the implementation according to the present invention Example of forming a pad formation step in a via liner lining pad; FIG. 5 is a diagram for explaining the concept of a conductive paste printing step in forming a via lining pad according to an embodiment of the present invention; Figure for illustrating the concept of a conductive paste printing step in forming a via liner lining in accordance with an embodiment of the present invention; Figure 7 is a diagram for illustrating the formation of a guide in accordance with an embodiment of the present invention The concept of the conductive paste hardening step in the hole-lined pad; FIG. 8 is a cross-sectional view showing an example in which the via-hole lining pad according to the embodiment of the present invention is formed by a drill hole; and FIG. 9 is a cross-sectional view For example, an example in which one of the drilled via lining pads according to the embodiment of the present invention is subjected to electroplating is shown. [Symbol description of main components] TH ( #1 ) , TH ( #2 ) , TH : Conductor thickness 14 (3) , 1 4, 3 1 — 1 to 3 1 — 4, 2 4 : Wiring pattern
Th ( 3 ) ，Th :導體厚度 12 ( #1 ) ，12(#2) ，12，32-1，32-2，22(#1) ，22 ( #2):導孔襯裡焊墊 10 ^ 10(2) ，2 0 :核心板構件 -13- (11) 1293015 L ( 3 ):第三層 18(1) ，1 8 :絕緣層 L ( 1 ):第一層 11 ( # 1 ) ，11(#2) ，11，21(#1) ，21(#2):盲Th ( 3 ) , Th : conductor thickness 12 ( #1 ) , 12 ( # 2 ) , 12 , 32-1 , 32-2 , 22 ( # 1 ) , 22 ( #2 ) : via lining pad 10 ^ 10(2) , 2 0 : core plate member-13- (11) 1293015 L (3): third layer 18(1), 18: insulating layer L (1): first layer 11 (#1), 11(#2), 11, 21(#1), 21(#2): blind
導孑L 1 9 ( # 1 ) ，1 9 ( # 2 ) ，1 9 :電鍍部分 L ( 2 ):第二層Guide L 1 9 ( # 1 ) , 1 9 ( # 2 ) , 1 9 : plating part L ( 2 ): second layer
40 :平台 41— 1，42—2:導電糊 3 0 :銅包覆疊層 2 3，1 3 :貫穿孔 3 1 :銅箔40: platform 41—1, 42—2: conductive paste 3 0 : copper clad laminate 2 3,1 3 : through hole 3 1 : copper foil
-14--14-