TWI284971B - Multichip stack structure - Google Patents
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- TWI284971B TWI284971B TW095103006A TW95103006A TWI284971B TW I284971 B TWI284971 B TW I284971B TW 095103006 A TW095103006 A TW 095103006A TW 95103006 A TW95103006 A TW 95103006A TW I284971 B TWI284971 B TW I284971B
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
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- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Description
1284971 九、發明說明: 【發明所屬之技術領域】 種關於 、—本發明係有關於-種多晶騎疊結構,尤指 稷數具皁邊銲墊之晶片的堆疊結構。 【先前技術】 力產品之微小化以及高運作速度需求的择 二車一半導體封裝結構之性能 子產品小型化之需求,半導體封裳件 才口電 (Muhichip paekage)乃成^θ 于裝 之半導體晶片相入乂„0 男悍错此將兩個或兩個以上 日日片、、且δ在早一封裝結構中,以 積,並提昇電性功能。亦即,多晶片封 == 個或兩個以上之晶片組合在 筹Τ糟由將兩 作速度之限制最小化。此外曰::二二來使系統運 間連,線路之長度而降低訊號延遲以及存取時間。 ^ ^ 1Μ t ί I " 2r " # ^ ^ # ^ (side-by'side) 於一共同基^之主要^ =個以上之晶片彼此並排地安裝 造之缺點為封裝二:二因:=式多晶片封裝構 片數目的增加而加大。H同基板之面積會隨著晶 所辦f解決上述習知問題,近年來常使用堆疊方法來安裝 rl:的晶片,其堆疊的方式按照其晶片之設計及打線製 旦沾ϋ不同。如5己^、卡結構即為—種整合複數晶片之高容 1的快閃記憶體電路模組,其内之快閃記憶體晶片(fiash memory chlp)係將其表面之鲜塾設計成集中於一邊,因 5 19267 1284971. T ’於晶片堆疊時係採用階梯狀方式進行堆疊,藉以使該 ^堆疊之晶片得以外露出設於其—邊之銲塾,以便於 進行打線作業。 、 —π麥閱第1圖’係為美國專利第6,则,528號所揭示 -種多晶片堆疊結構,其係在晶片承載件10上堆疊了複 ^曰片’以將第一晶片U安裝於晶片承載件10上,第二 曰曰片12以一偏移之距離而不妨礙第一晶片η銲墊11〇之 > 作業為原則下堆疊於該第-晶片u上,第三晶片13 為原距離而不妨礙第二晶片12銲墊12G之打線作業 最:厂堆登於該第二晶片12上,以形成階梯狀之晶片堆 構;接著再進行打線作業,以利用複數銲線14而使該 1_弟二及第三晶片n,12,13電性連接至該晶片承載件。 則述梯狀之晶片堆疊結構雖較並排晶片方式節省 ^壯且可先行堆疊晶#後,再—次進行打線作業,並透 勝“=壓製程以形成用以包覆該堆疊晶片及銲線之封裝 ^产對製程作業;其中為減少於料模壓製程之 該封心ϊ Γ擊造成線弧傾倒(sweep)或斷裂(br°ken), 才攻杈壓製程之注模口 (moldgate) :方:r’而其可能之實施態樣即如第…上 吏/、鋅線端遠離注模口 G(如第2A圖所示 線^朝向注模口 G(如第2B圖所示)。 次使J干 於封=二第Γ圖所示’當鲜線端遠離注模口0,而 覆該階梯二自該注模口 〇注入封農樹脂以形成包 梯狀曰曰片堆豐結構之封裝膠體時,因封襄樹脂模流 19267 6 1284971 會直接衝擊該階梯狀晶片堆疊結構中上層晶片之懸空部 分,如此,將容易造成上層晶片發生制離問題(如虛線所 示)。 相對地,如第2B圖所示,當銲線端朝向注模口 G, 而於封裝模壓製程中,自該注模口 〇注入封㈣脂以形成 包覆㈣梯狀晶片堆疊結構之封農膠體時,因受模流回流 衫響,即容易在該階梯狀晶片堆疊結構之懸空部分形成氣 洞v,甚而導致於後續熱處理 ^ 賴度測试產生爆米花 (popcorn)效應,造成封裝產品不良問題的產生。 安再者’請參閱第3圖’係為美國專利第M40,622 f卢 案所揭示之半導體梦罟伞而-立 儿 •等電子產。圖’為提升如前述記憶卡 .1 Γ 電性功能’勢必於«結射增設如電容元 % -般係散佈於=之:邊動了 35 ’惟該些被動元件 面尺寸之增加。之兩邊’如此將造成封裝結構平 ^制甚如何提供一種可避免多晶片堆疊結構於封事桓 :,同時可有效提供被動元件接著區 成之目標。 λ馬目刖亟待達 【發明内容】 鑑於以上習知缺點,本發明 晶片堆疊結構, 、係‘供一種多 μ %以避免於封裝模壓製程中堆晶 ▲衝擊造成剝離之問題。 定之日日片受模 本發明之再—日M ^ 、系提供-種多晶片堆疊結構,以避 19267 7 1284971 免於封裝模壓製程中產生氣洞問題。 分提ίίS的係提供―種多晶片堆疊結構’可充 刀棱供被動7G件之接著區域。 傅J兄 為達上揭及其他目的,本 構,其係包含:-晶…:揭路一種多晶片堆疊結 梯狀方六曰7?载件,稷數半導體晶片,係以階 罘狀方式依序堆豐於該晶片 件,係接詈料曰h f戰件上,以及至少-被動元 继曰片中上對應於該階梯狀堆昼之半導 == 卜懸出半導趙晶片之下方。該些半導懸晶 有早邊鋅墊且呈階梯狀 方晶片不致擋到下方晶片件上’使得上 線製程,以供該此半導體曰片域’而不妨礙打 .晶片承載件。 日片、“複數條銲線電性連接至 :發明之多晶片堆疊結構主要係在階梯狀晶片堆疊 i被動=晶片承载件上對應於外懸出晶片之—側預先設 晶=俾在封裝製程中,對應該階梯狀晶片堆 ·=:鲜線端係平行朝向注模口時,即可利_^ 乍為、=件以避免氣洞之產生;相對地,當料端是對 J仃通離於注模口時,即可利用該被動元件作為阻播件 以避免模流直接衝擊晶片’而造成晶片剝離問題;同時由 於《亥被動元件係接置於該晶片承載件上對應於堆疊晶片外 up刀之下方,藉以充分提供被動元件接著區域,避免習 =被動元件散佈設於晶片兩側所造成使用面積之增加,而 得縮減封裝結構之平面尺寸。 【實施方式】 19267 8 1284971 乂下係藉由特疋的具體實施例並配合圖式說明本發 明之實施方式,熟習此技藝之人士可由本說明書所揭示之 内容輕易地瞭解本發明之其他優點與功效。 請參閱第4A及4B圖,係為本發明之多晶片堆疊結構 之剖面及平面示意圖。如圖所示,該多晶片堆疊結構係包 ^ · 一晶片承載件40 ;複數半導體晶片41,係以階梯狀方 式依序堆疊於該晶片承載件4〇上;以及至少一被動元件 曾係接置於5亥晶片承載件4〇上對應於該階梯狀堆疊之半 ’導體晶片中外懸出半導體晶片之下方。 該晶片承載件4 〇係例如為一基板結構。該進行堆属 半導體晶片41係例如為快閃記憶體晶片,其平面且尺 寸、.、勺略相同,且於單邊設有複數鮮塾41〇, 導體晶片41以其具銲墊41〇之_ 、層之丰 片Μ 一預先設定之距離,並使Jim下^之半導體晶 致擔到下層之半導體曰月^于 導體晶片41不 “…田 之銲墊410直向上區域,而依 丨序進仃堆豐各該半導體晶片41,萨以 一 之階梯狀晶片堆疊結構,且外;^/成-早故晶片外懸 塾41〇,進而供該些半導體晶二^ 片4 1件以猎由複數條错綠4 4 而電性連接至該晶片承載件4 〇。 *數仏鋅線4 4 於本實施例中,該銲線4 多晶片堆疊結構時所注人封與供封裝該 態,且該銲線端係對庫設於 曰/拉口0呈平行狀
該階梯狀堆疊晶片之;主模口 G之-㈣ 之-側。 卜心日日片部分係對應朝向該注模口 G 19267 9 1284971 等,以動二45係如電容元件、電阻元件或電感元件 ^ ^ ^ 4Τ φ ; ^7?^# 4 0 ^ ^ ^ ^ ^ ^ ^ + V體日日片41中外懸出晶片之下方。 如此士,不僅可藉由該被動元件45提升整體結構電性 功此,同蚪亦可利用該被動元件45作為阻擋件,以 裝樹脂模流直接衝擊該階梯狀之晶片堆疊 剝離問題。 再^珉日日片 •閱ί 51,係為本發明之多晶片堆叠結構第二 二=1。本實施例之多晶片堆疊結構係與前述 Λ施例大致相同,主要差里力於 要差異在於该銲線端係對應設於朝向 扭之—側,亦即該階梯狀堆疊晶片之外懸晶片部 分係對應遠離該注模口 G之一側,a + _ 恭技Mu 側,如此,該接置於晶片承 載件40上,且對應於該階梯狀堆疊之半導體晶片中外 晶片下方之被動元件45,係可作用為填充件, _ 模壓製程中氣洞的產生。 ι兄封衣 '•晶二:ί過本發!之多晶片堆疊結構主要係在階梯狀 曰且、、^構,係在晶片承載件上對應於外懸出晶片之— 側預先設置至少-被動元件,俾在封裝模壓製程中,對應 該階梯狀晶片堆疊結構之銲線端係平行朝向注模口時,: 可利用該被動元件作為填充件以避免氣洞之產生;相對 地,當銲線端是對應平行遠離於注模口時,即可利用該 動元件作為阻播件以避免模流直接衝擊晶片,而造成^ 剝離問題;同時由於該被動元件係接置於該晶片承裁件上 對應於堆疊晶片外懸部分之下方,藉以充分提供被動元件 19267 10 1284971 接著區域’避免習知被動元件散佈設於晶片兩侧所造成使 用面積之增加,而得縮減封裝結構之平面尺寸。 惟以上所述之具體實施例,僅係用以例釋本發明之特 點及功效,而非用以限定本發明之可實施範疇,在未脫離 本發明上揭之精神與技術範疇下,任何運用本發明所揭示 内容而完成之等效改變及修飾,均仍應為下述之申請專利 範圍所涵蓋。 【圖式簡單說明】 田第1圖係為美國專利第6,9⑼,528號所揭示之多晶片 堆豐結構之剖面示意圖; 第2 A圖係為習知多晶片堆疊結構於封裝模壓製程時 ^生上層晶片剝離問題之剖面示意圖; 第2B圖係為習知多晶片堆疊結構於封裝模壓製程時 兔生氣洞問題之剖面示意圖; _ =圖^美國專利第6,_,622號所揭示之半導體 衣置平面示意圖; 第4A及4B圖係為本發明 之剖面及平面示意圖;以及 第5圖係為本發明之多晶 示意圖; 之多晶片堆疊結構第一實施 片堆疊結構第二實施之剖面 【主要元件符號說明】 晶片承載件 繁一曰 Η 牙7 曰曰乃 望一曰fci 外一日日乃 19267 11 10 1284971 13 弟二晶片 110,120 銲墊 14 銲線 31 半導體晶片 35 被動元件 40 晶片承載件 41 半導體晶片 410 銲墊 # 44 鲜線 45 被動元件
Claims (1)
1284971 ι· # 3· 4· 5. 、申請專利範圍: 一種多晶片堆疊結構,其係包含: 一晶片承載件; 複數半導體晶片,係以階 片承载件上;以及 _狀方式依序堆疊於該晶 該二二:!動:件’係接置於該晶片承載件上對應於 方梯狀堆登之半導體晶片中外懸出半導體晶片之下 如申請專利範圍第1項之容曰 晶片承#株成^ 、之夕日日片堆豐結構,其中,該 曰曰月承载件為一基板結構。 範圍第1項之多晶片堆疊結構,其中,該 + V肢晶片為快閃記憶體晶片。 如申請專利範圍第i項之多曰ΰ协田 半導體”置、夕曰曰片堆豐結構,其中,該 片:邊t有複數銲塾,且在依序堆疊該半導 二ΓΓ传出各該半導體晶片之銲墊,藉以 4#早心4外懸之階梯狀 如申請專利範圍第4項之多晶片堆二:構: 半導I#曰片夕祕田从 隹®、、、口構’其中,該牛V體曰曰片之堆璧結射,上、下 墊係位於同一側,且卜层主 、日日片之如 體晶片預定之距離,以僻If ^ 墊直向上區域,以㈣層半導體晶片之薛 電性連接至該晶#承载件。 错料線而 :"倉專利範圍第i項之多晶片堆叠結構,” +導體晶片係藉由複數條銲線而電性連接至該晶片承〆 19267 13 1284971 載件。 .7.如申請專利範圍第6項之多晶片堆疊結構,盆中,节 銲線之佈設方向係與供封裝該多晶片堆疊結構時岐 入封裝樹脂之注模σ呈平㈣g。 ^主 8· t申料利範圍第7項之多晶片堆疊結構,其中,該 在干線鳊係對應設於遠離該注模口之一側 9. ?請專利範圍第7項之多晶片堆疊結構,其中,該 =梯=堆豐晶片之外懸晶片部分係對應朝向 擊之一側。 10. 如申請專利範圍第7項之多晶片堆疊結構,其中,該 崔干線端係對應設於朝向該注模口之一侧。α χ u.如申請專利範圍第7項之多晶片堆最社構, 階梯狀堆疊晶片之外科曰片邻—構”中,该 之一側。 夕卜懸曰曰U分係對應遠離該注模口 19267 14
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TW095103006A TWI284971B (en) | 2006-01-26 | 2006-01-26 | Multichip stack structure |
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KR100764682B1 (ko) * | 2006-02-14 | 2007-10-08 | 인티그런트 테크놀로지즈(주) | 집적회로 칩 및 패키지. |
US8723332B2 (en) * | 2007-06-11 | 2014-05-13 | Invensas Corporation | Electrically interconnected stacked die assemblies |
TW200917391A (en) * | 2007-06-20 | 2009-04-16 | Vertical Circuits Inc | Three-dimensional circuitry formed on integrated circuit device using two-dimensional fabrication |
US8704379B2 (en) | 2007-09-10 | 2014-04-22 | Invensas Corporation | Semiconductor die mount by conformal die coating |
WO2009114670A2 (en) | 2008-03-12 | 2009-09-17 | Vertical Circuits, Inc. | Support mounted electrically interconnected die assembly |
US7863159B2 (en) | 2008-06-19 | 2011-01-04 | Vertical Circuits, Inc. | Semiconductor die separation method |
US9153517B2 (en) | 2008-05-20 | 2015-10-06 | Invensas Corporation | Electrical connector between die pad and z-interconnect for stacked die assemblies |
US8552566B1 (en) | 2008-05-30 | 2013-10-08 | Maxim Integrated Products, Inc. | Integrated circuit package having surface-mount blocking elements |
TWI570879B (zh) | 2009-06-26 | 2017-02-11 | 英維瑟斯公司 | 半導體總成及晶粒堆疊總成 |
US8476749B2 (en) * | 2009-07-22 | 2013-07-02 | Oracle America, Inc. | High-bandwidth ramp-stack chip package |
US8552546B2 (en) | 2009-10-06 | 2013-10-08 | Samsung Electronics Co., Ltd. | Semiconductor package, semiconductor package structure including the semiconductor package, and mobile phone including the semiconductor package structure |
US9147583B2 (en) | 2009-10-27 | 2015-09-29 | Invensas Corporation | Selective die electrical insulation by additive process |
TWI544604B (zh) | 2009-11-04 | 2016-08-01 | 英維瑟斯公司 | 具有降低應力電互連的堆疊晶粒總成 |
US9082632B2 (en) | 2012-05-10 | 2015-07-14 | Oracle International Corporation | Ramp-stack chip package with variable chip spacing |
CN103928416B (zh) * | 2014-03-24 | 2016-09-07 | 三星半导体(中国)研究开发有限公司 | 具有无源器件的半导体封装件及其堆叠方法 |
US9871019B2 (en) | 2015-07-17 | 2018-01-16 | Invensas Corporation | Flipped die stack assemblies with leadframe interconnects |
US9825002B2 (en) | 2015-07-17 | 2017-11-21 | Invensas Corporation | Flipped die stack |
US9490195B1 (en) | 2015-07-17 | 2016-11-08 | Invensas Corporation | Wafer-level flipped die stacks with leadframes or metal foil interconnects |
US9508691B1 (en) | 2015-12-16 | 2016-11-29 | Invensas Corporation | Flipped die stacks with multiple rows of leadframe interconnects |
US10566310B2 (en) | 2016-04-11 | 2020-02-18 | Invensas Corporation | Microelectronic packages having stacked die and wire bond interconnects |
US9595511B1 (en) | 2016-05-12 | 2017-03-14 | Invensas Corporation | Microelectronic packages and assemblies with improved flyby signaling operation |
US9728524B1 (en) | 2016-06-30 | 2017-08-08 | Invensas Corporation | Enhanced density assembly having microelectronic packages mounted at substantial angle to board |
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US20060267173A1 (en) * | 2005-05-26 | 2006-11-30 | Sandisk Corporation | Integrated circuit package having stacked integrated circuits and method therefor |
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