TWI274372B - Improved process for resurf diffusion for high voltage MOSFET - Google Patents

Improved process for resurf diffusion for high voltage MOSFET Download PDF

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TWI274372B
TWI274372B TW094120444A TW94120444A TWI274372B TW I274372 B TWI274372 B TW I274372B TW 094120444 A TW094120444 A TW 094120444A TW 94120444 A TW94120444 A TW 94120444A TW I274372 B TWI274372 B TW I274372B
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implant
layer
diffusion
arsenic
depth
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TW200603249A (en
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Thomas Herman
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Int Rectifier Corp
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  • Engineering & Computer Science (AREA)
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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)

Description

1274372* 九、發明說明 【發明所屬技術領域】 ，本發明係有關於一種半導體裝置處理，更特別係有關於一種新製程 於製造石夕晶圓結構，而使用於半導體裝置之製造中。 【先前技術】 半導體裝置之製造中，通常在石夕晶圓之頂部形成蠢晶沉積石夕接 層:此蟲晶層具有低的N或P摻雜濃度，而此基板是較厚且較大濃度居。 然後在蠢晶層巾形成任何所想要型式之接合圖案以形成已知裝置 MOSFET、IGBT、二極體、積體電路等。 · 、高壓半導體裝置通常使削賴表面場(resurf)區域，其為高電位差 ^間之低濃度區。當電壓差增加時，此縮減表面場區域變得空: e=te)，以及在施加最大電塵差之前完全空乏。在雙縮減表 (=^esu⑴技射，财_減紐之卿心。#所施加電壓 ，增加^此兩健域均空乏。此觀置與制雙敗㈣技術之優 在吴國專利案號USP4, 866, 495中說明。 ^i=Lrerf技術之高壓裝置中，藉由將適當雜質植人於相反極 23，-生單一極性之reSUrf區。此由擴散職rf =緊之庇曰曰£作為弟一 resurf區。當將在頂部(擴散）⑽社
1X 1〇12cm2'^T^(^^^) resurf 制在15x H) on a夺，則可以達成崩潰電壓。此種結構之一 I 政測rf層之深度稍微改變時，在此所壓緊epi輯中之電又二 ，於失去對崩潰電壓之控制。此效應必_ ;二 消。此較縣晶層具魏項缺點.· 層而抵 L須要較狀_舰，簡在麵· 隔離，在溫度1靴或以上須要較 二 2 I9nn°r^p； 玄杈長之擴政蚪間，導致較低之產量。 .產^ 非吊長之擴散時間造成更多缺陷，而導致較低 3_在溫度纖或以上長之擴散時間，由於較大之橫向擴散，導致較 5 1274372 寬之隔離擴散，因此降低在晶片上可使用面積之數量。 此在1999年1们9日所公告之NimjRanjan之美國專利案號_ 5, 861，657，並移轉於本申請案之受讓人，其對於上述方式建^一種 改良，因此將磊晶層之厚度大幅降低，且修正電荷分佈。因此，其 〇揭=此底部resurf電荷（所壓緊之epi區域)之大部份（大於大約g j較佳大於80% )，是包含於epi底部1至4微米、或epi底部之大 ，25%中、或較佳epi底部之2〇%中。此邙丨之頂部部份是更較輕 祕#雜’以及包含非常小部份底部resurf電荷。
此在下部蠢晶區中所增加電荷藉由以下兩種方式之一 製造過程開始導入： U 1·在磊晶成長輕微掺雜區之前，藉由將適當掺雜物植入於基板晶 中，接著進行擴散。 Μ 2·藉由蠢晶成長過程，其中魏成長薄的重掺雜蠢晶，接著成 厚之輕掺雜epi。 在所產生之結構中，此頂部（經擴散）縮減表面場區之深度變 、匕，對於位於其下之壓緊區域巾所包含電荷具有小許多之效應。此 ^成對於缝電壓較佳控制，其具有麟給定崩潰電壓更薄^晶 =此較薄之蟲晶層，再度減少用於形成隔離擴散所須之擴散處理 守間’以及此隔離擴散具有較小之橫向範圍，且佔用較少之晶片面 積。 【發明内容】 之砷ΐίίϊ明’在成長傳統N縣分艘晶接面接收層之前，將非常淺 他緩慢擴散掺雜_如小於G. 3微米深紐人於p型魏板中。 隨後之1 ’除了在隨魏長I晶層巾於形成峨賴散巾所使用之 曰ict，並未使闕意之擴散步驟。然後，在此紐人之頂上蟲 日日成長N層，其且有业剖q $ f；外水4, 一區_；^ 級厚度° _ ’將大約1微米厚之 f形成接關案後，此最初所擴散之骑深人至例如大約3微米之深 又。反之，習知技術（5, 861，657號）建議將鱗或坤植入，且在p基 散至1至2微米之深度。在以傳統擴散步驟形成崎置後，此最ς之植二 '1274372. 會深^至超過3微米，用於相同之隨後熱處理。 由使用在p基板巾超紐人㈣衝區，可以發現在蠢晶層中整個n 載子濃度較佳分佈與控制，此導致例如更較佳之經控制且更可預測之 resurf 二極體。 ，外，以本發明之新製程，此接面接收層中電荷之大約4〇%是在層 之底部，此與在美國專利案usp 5,861，657中所揭示之7〇%不同。曰 来此重要的是，此植入層保持僅可能的窄。因此，須要較緩慢之砷而非 麟之植入。在較佳實施例巾，在未分段N型蠢晶成長前 初坤植入深度僅大約〇·丨微米。 a在植入立即之後，並不刻意地執行熱擴散而特意將砷擴散於基板中。 當然由於製造此裝置賴之其他齡驟，補伽帶之擴散會驅動坤。 本發明之優點為其對於此在蠢晶層中整個型淨掺雜，提供更大之控 制與準確度，其對關如跡阻則⑽至丨腑之咖耐裝置為重要。 【實施方式】 (a)習知拮術 首先凊參考第1圖，其顯示習知技術之水平導電二極體，其接面是 形成於單晶矽之N—磊晶層之N—井1〇中，而沉積於p型基板丨丨之頂上。 一 N+擴散提供低電阻接觸至：具有端子“κ”之陰極電極12。此 13是裝置陽極“A”。 磊晶層10(有時稱為“epi”）藉由一或多個p型隔離擴散例如擴散 23，分割成多個隔離井2〇、21以及22，此擴散之形狀可以為環形，但 亦可以為任何其他所想要之形狀。陽極接觸13是沉積於p+區域23之頂 上。此擴散23必須足夠深，以截斷區域1〇與Η間之p/N邊界，以便隔 離區域或井20、2卜以及22。井21與22可吨含任何所想要之接面^ 案，以形成二極體、在任何所想要離散或積體電路結構中之士 置及/或雙載子裝置。 衣 當此第1圖之裝置是高電壓裝置例如用於6〇〇伏特以上時，可以設 置環形resurfp-區30，其具有大約ΐχΐ〇12原子/平方公分之總電荷，= 當在二極體之電極12與13間施加最大逆向電壓時，此R^Hp—區3〇 ' 1274372 會完全空乏。為了防止在逆向偏壓下穿透式崩潰，此習知技術將用於高 壓應用例如600V或更高之磊晶層1〇製成大約2〇至25微米厚，且具二 在其表面所測量之均勻K電阻為大約3歐姆/公分。 八 因為比較厚之蠢晶層10，此P型隔離擴散23由於橫向擴散亦變得 比較寬。此造成擴散23佔據此總晶片面積相對大之部份，而減少各種包 含接面井之可使用面積。此外，此較厚之i晶層1Q增加此形成個別晶^ 之晶圓之成本，增加處理時間，以及由於須要較長高溫處理時間而= 額外損壞。
區域30典型地是大約5微米深。當由於製程改變而此深度改， 此區域30下之epi壓縮對於在下面之電荷具有主要影響，除非藉由使用 在區域30下之大epi容積而降低電荷濃度。 第2圖顯示美國專利案號USP 5,861，657中之結構，豆中 中相同之數字代表相同元件。在第2圖中使用與第丨圖層财相θ ，子總濃度’但藉由將其總濃度之較大百分比置於在^層1()底部小厚 度:Γ40中。，其濃度重新分佈。例如，區域40之厚度為層10之總厚度 i ，且具有層10濃度之2至4倍。然而，區域40厚 度應¥致在此區域中之總電荷為丨.2至丨.5xi()1W2。_ 是2 時)J具社約7xlQlw3之掺雜濃度。此辦植1層中電 何為在值入層與epi層中總電荷之大約4〇%。 κί由將在丄區域10中之總電荷重新分佈，此蠢晶層或區域1〇之厚产 大巾田減^ ’例如對600V之崩潰電壓從2〇微米減少至1〇 缺: 幅減少用於隔離擴散23所須深度，以及因此 面積= 留晶片上更多_於_路或元件 、=積口^匕= 所須時間，例如，從用於2〇料芈戶^ ^貝貝上減少驅動擴政23 eP1之6小時。 私削之24小時減少至綱◦微米厚 區域中之電荷具有較^影響°。_喊中之變化，對於賴緊epi 此基何i專統P型基板，且可具有5至25毫米之厚度。 土 & X月月’貝电屬之須求而選擇。例如，對於600V崩潰電屬 、1274372· 基板11之電阻為大約60歐姆/公分，以及對於12〇〇v崩潰電壓基板n 之電阻為大約150歐姆/公分。 土 首先成長在習知技術第2圖中用於600V裝置之epi層部份4〇，而 具有相當低之電阻例如〇· 5至1歐姆/公分與1至4微米之厚度。選擇用 於區域24〇2之厚度與電阻之組合，以致於此層之總電荷為1.2至 1.5χ1012αιΓ2，導致磊晶片電阻3000至4〇〇〇歐姆/平方單位。 此比較重掺雜區40(相較於區域1〇)是藉由以下方式產生·將磷或砷 離子直接植入於Γ型基板Η中，接著藉由擴散(在沉積邙丨層⑺之前) _ 祕質驅動至1至2微米深。選擇此植人缝與驅人擴散條件以達成 • 3000至4000歐姆/平方單位之薄片電阻。然後在擴散40上成長epil〇。 取決於Fresurf區30之深度與在重掺雜區40中雜質種類，以選擇 頂部epi層（區域1〇)之厚度。例如，如果p resurf區3〇'是大約5微米 深且在區域40中使用砷雜質，則對區域1〇選擇大約8微米之厚度〕可 以藉由減少Presurf區30之厚度，而進一步減少頂部邙丨（區域7〇)之 厚度。 取決於積體電路其他部份所施加之須求，此在習知技術第2圖中區 域10之電阻可以為2至4歐姆/公分。此區域10之電組愈低，則俞難控 制P resurf區30中之電荷。選擇此(在p resurf區3〇)下底部ei^所壓 • % _電荷之厚度與電阻為L 5至2. _12〇ϋ2，或在所有處理步驟結束 # 之壓緊ePi薄片電阻為2800至3500歐姆/平方單位。 此所揭示區域1〇與其子區域4〇為掺雜磷或砷。其揭示為當相要較 ，區域時’，較佳(但在植人後擴散），因騎具有較磷為低之&散係 數，且因此具有較少之從重掺雜區40至輕掺雜區1〇之自動掺雜。 (b)本發明 根 =本發明，第2圖之區域40是藉由將珅或類似緩慢擴散麵材料 非Q)植入P基板11巾大約微米深度而形成。在形成區域ι〇之 1此植人後沒有擴散步驟。此對植人所施加之擴健在隨後實施，以 在蟲晶成長區域10中形成接面圖案。在典型過程中，此種擴散步驟合 增加石中植人區4G之最後深度大約3微米。反之，f知技術之第2圖之^ 1274372, =驅動植人40⑽麵），其在沉積層1Q之前擴散至丨至2微米，而在 隨後在蠢晶區域1〇中產生接面圖案期間，被驅動至3微 或6微米。 ^此植入形成區域4〇為一未遮蔽之“地毯式，，植入。如果想要的話， 此選擇式遮蔽植入碎層只可以在稍娜成之高電壓裝置下之區域中形 成。 以下說明使用本發明用於6 〇 〇 v產品之典型製造過程。 。此開始P晶® 11可以具有電阻7〇至1〇〇(較佳9〇)歐姆/公分。此晶 | ®以傳統方式清理且備製用於植入，且在180Kv以L 1El2±大約2〇%之 φ 劑量值入此坤埋入層40。 然後，將N層1〇蠢晶沉積至大約3_ 5微米之厚度而具有大約L 〇 歐姆/公分之電阻。 然後，貝加傳統處理步驟以形成接面圖案。因此，可以使用傳統微 影術遮罩方法在180keV以4· 7E12值入_子、而可形成·rf區洲， 然後在I、j0(rc實施擴散驅動5小日夺。由於此驗驅動與其他，此最初植 入40會深入，但其較習知技術丨-2微米之最初擴散小許多。 第3圖顯不當此橫向導電N通道M〇SFET形成於第2圖之井2丨中時， 可以如何使用本發明。與第2圖中相同數字代表相同元件。在第3圖中， • 此接面圖案包括：由環形resurf擴散51所圍繞之中央汲極擴散5〇。將 • 此包含源極環56之環形P型基底55概於區域10之頂部表面中。在多 晶矽閘極環61下形成適當閘極氧化物，且井1〇之整個表面由鈍化氧 化物62覆蓋。源極電極65為環形而連接至源極56與基底55，且汲極 電極66連接至汲極區50。閘極電極57連接至多晶矽閘極61。 在操作中，此第3圖之結構會承受：在源極電極65與汲極電極邸 間之例如_v與以上之高逆向偏壓。為了將此裝置導通，對閘極61施 加電壓’其造成在絲55中通道區之反轉。此電子電流然後可以從源極 電極65、經由此反轉通道、在resurf擴散51下，流至汲極祁。 應注意此在第3圖中所示之接面圖案可以為任何其他所想要盘已知 之接面圖案，以及可以為蜂巢式、交趾式等。 ” 在600V之實施例中，此從閘極環61之外部邊緣至隔離擴散23之 、1274372 緣之橫向距離大約25微米。區域10大約4微米深。閘極環61之寬度大 約10微米。環61之内部邊緣至接面50外部邊緣之橫向距離、對於 裝置大約為70微米、對於1200V裝置大約為14〇微米。p-resurf區51 可以具有大約1微米之深度。清注意在1微米深度中之製程變化，對於 區域51下之“epi壓緊”具有小的效應，因為總電荷之大約6〇%是在壓 緊區中。 热而，基板之電阻 在1200V電壓裝置之情形中可以維持以上尺寸 增加至大約200歐姆/公分。
第4圖顯示具有高電壓PMOS應用之本發明。在第4圖中，盘第2 與3圖相同之元件具#_之辨識號碼。因此，將第2 * 3圖之^ 合，且閘極61覆蓋p+區域1〇〇與中央Γ區域1〇1間之可反轉通道y設有 中央P+接觸區102以接觸没極接觸66。亦設有N+接觸區1〇3，而與^ 100之邊緣接觸。接地接觸13連接至P+區域23。 一 σ° 3 雖然，以上參考特殊實施例說明本發明，然而，對於熟習此技術人 士為明顯，可以對本發明作許多其他變化、修正、以及其他使用。 本發明較佳並不受限於在此所揭示之内容。 ’ 【圖式簡單說明】 第1醜示在傳統習知技術晶圓蟲晶層巾包含在隔料 體之晶片一部份之橫截面圖； ° 第2圖顯示習知技術結構，其將在第！圖中之蠢晶層中之 八 配，而允井使用較薄蠢晶層以及較佳控制崩潰電壓； σ ,刀 第3圖顯示使用本發明用於Ν通道橫向導電M〇SFET， 圖中晶片之另一個N井中；以及 v、為在第2 第4圖顯示可以在高壓p通道M〇SFET中執行本發明之方式。 【主要元件符號說明】 10 ΡΓ井/磊晶層/區域 11 P型基板/晶圓 1274372
12 陰極電極 13 環形電極/接觸 20 隔離井 21 隔離井 22 隔離井 23 擴散/P+區域 30 區域 40 區域/擴散 50 >及極區 51 resurf擴散/區域 55 P型基底 56 源極環 57 閘極電極 60 閘極氧化物 61 閘極 62 鈍化氧化物 65 源極電極 66 沒極電極 100 P+區域 101 F區域 102 P+接觸區 103 N+接觸區 A 裝置陽極 K 端子 SOURCE 源極 DRAIN 汲極 12

Claims (1)

1274372. 十、申請專利範固： 2形朗於容解導體裝置之晶騎狀製程，_程包括以下 將緩k擴放JV型植人材料植人 小於大約U «之深度：錢在%^^面、巾，該植入具有
層；以及然後執行第-擴散步驟，“接面接收 間對該植人實施。 、在-錄面接收層切成接面期 2·如申請專利範圍第1項之製程，其中 該緩慢擴散植入材料為砷。 3·如申請專利範圍第1項之製程，其中 積上具有恆定之 =入為地毯式植人’而在該表面之實質上整個面 4·如申請專利範圍第2項之製程，其中 參 為地毯式植入，而在該表面之實質上整個面積上具有恆定之 5·如申請專利範圍第1項之製程，其中 該植入具有大約〇· 1微米之深度。 6·如申請專利範圍第4項之製程，其中 該植入具有大約〇· 1微米之深度。 7·如申請專利範圍第2項之製程，其中 此石申植入所具有劑量為5E11至3E12原子/平方公分。 8·如申請專利範圍第7項之製程，其中 13 1274372* 此砷植入所具有劑量為1· 3E12原子/平方公分。 9·如申請專利範圍第5項之製程，其中 此砷植入所具有劑量為1· 3E12原子/平方公分。 10·如申請專利範圍第1項之製程，其中 该磊晶層所具有厚度小於大約5微米且為N式濃度。 11. 如申請專利範圍第2項之製程，其中 除该蠢晶層所具有厚度小於大約5微米且為n式濃度。 12. 如申請專利範圍第n項之製程，其中 2植入為地毯式植人，且在該表面之實肚整個面積上具有值定濃 13_如申請專利範圍第12項之製程，其中 該植入具有大約〇· 1微米之深度。 14·如申請專利範圍第13項之製程，其中 > 此砷植入所具有劑量為1. 3E12原子/平方公分 15. -種起始晶圓，其所包含半導體接面具有超過6〇〇v之額定電 晶圓包括： P型基板； 砷植入，其深度小於0.3微米，跨該基板頂表面而均勻地形成於1 中； /、 N型接面接收磊晶層，其沉積在植入於該基板表面之該砷之上；該砷 植入僅由於隨後之擴散而擴散，此擴散在該磊晶層中形成接面，以 及作為對來自該P型基板該磊晶層掺雜之緩衝層。 14
1274372. 16.如申請專利範圍第15項之起始晶圓，其中 该坤植入藉由隨後至該磊晶層中之擴散，其厚度增加至小於大約5 微米。 17·如申請專利範圍第π項之起始晶圓，其中 。亥P基板以硼掺雜且具有電阻值歐姆/公分，且該砷植入具有由 植入劑置大約1· 3Ε12原子/平方公分所界定之電阻。 18·如申請專利範圍第Μ項之起始晶圓，其中 該Ρ基板以刪参雜且具有電阻值7〇歐姆/公分，且該坤植入具 植入劑ϊ大約1. 3Ε12原子/平方公分所界定之電阻。 19·如申請專利範圍第π項之起始晶圓，其中 該„掺雜，且具有小於大約5微米厚 公分之電阻值。 20.如申清專利範圍第18項之起始晶圓，其中 該蟲晶層為_雜，且具有小於大約5微 公分之電阻值。 子厌，、穴、、0 21·如申請專利範圍第15項之起始晶圓 该石申植入具有較該蟲晶層中為少之電 總電荷之大約40%。 22·如申請專利範圍第15項之起始晶圓，其中 在該蟲晶層中總電荷與該石申植入中電荷之比為60對40 1. 0歐姆/
’其中 荷，且包含此植入與磊晶層中 15
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