TW201029182A - Charged balanced devices with shielded gate trench - Google Patents

Abstract

This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as the drain region whereby a super-junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches. Each of the trench MOSFET cells further includes a trench gate and a gate-shielding dopant region disposed below and substantially aligned with each of the trench gates for each of the trench MOSFET cells for shielding the trench gate during a voltage breakdown.

Description

201029182 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a vertical semiconductor power device, and more particularly to a single-thin epitaxial layer, which is realized by advanced manufacturing and can be used for preparing various sizes (four) having super The junction structure (4) covers the vertical power device of the channel's electrical balance, and the different breakdown voltages are made by simple and flexible fabrication. ek uses [prior art] The manufacturing technology and device structure of the system, although In the reduction of (four) electricity, at the same time, can further increase the breakdown of money, but still face many technical bribes 0

question. Due to the structure and point of the traditional high-power device, it usually takes a long time, complicated and expensive production process. Therefore, the high-dust semi-conducting power will be used in the application of time and the real miscellaneous is the high-power device. The production process is very complicated, and the production: and the income are very low. In addition, semiconductor power racing is usually not made with the original semiconductor wafer, but is made with an acoustic wafer. This undoubtedly increases the cost of semi-conductivity and miscellaneous ‘production. Moreover, its functional and performance characteristics also depend on the process Q parameters used in the epitaxial layer. Thus, the use of such pre-processed wafers for power devices that rely on the original pre-processed wafers further limits the manufacturability and flexibility of production of these power devices. Compared with the conventional process, the super junction technology has the advantages of obtaining a higher breakdown voltage while increasing the drain-source resistance Rdson. For a standard power transistor unit, the breakdown voltage is highly dependent on the low-doped drift > Therefore, the thicker the drift layer, the higher the rated voltage that can withstand 099101558, but the leakage of the form number Α0101 source resistance Rdson has increased significantly. In the conventional power device, the drain-source resistance Rdson and the breakdown voltage BV are approximately combined with the following functional relationship:

Rdson 〇ζΒΥ 2. 5 In contrast, the charge balance is achieved in the drift zone of the device with a super junction structure. The drain-source resistance Rdson is combined with the breakdown voltage BV to be a more convenient functional relationship, namely:

, Rdson 〇cBV Therefore, in high-voltage device applications, it is necessary to design and produce a semiconductor power device with a super ® junction structure in order to reduce the drain-source resistance Rdson while achieving high breakdown voltage and improving device performance. The area near the channel in the drift zone has the opposite conductivity type. Only the region near the channel is doped with the opposite conductivity type, and the relative doping concentration of the drift region is higher. In the off state, the charges in these two regions cancel each other out, and the drift region is depleted and can withstand high voltages. This is called the super junction effect. In the on state, the doping concentration of 'i in the drift zone is higher, so its drain-source resistance pair ^ ^ ", : . ^operry ϋ However, in the manufacture of power devices, the race/junction technology still encounters many technical problems. The problems and limitations. More precisely, some conventional structures require multiple epitaxial layers and/or buried layers. According to previous manufacturing processes, many device structures require multiple back etching and chemical mechanical polishing ( CMP) processes. In addition, these processes for fabricating process devices sometimes do not conform to standard casting processes. For example, some standard high-volume semiconductor foundries have oxide chemical mechanical polishing (CMP)' but some super-junction technologies The chemical mechanical polishing (CMP) that is used in the process is not. Therefore, the structural characteristics and manufacturing process of these devices are 099101558. Form No. A0101 Page 5 / Total 59 Page 0993094181-0 201029182 Defined 'They are not applicable to Low-voltage to high-voltage device applications. In other words, 'some of the cost of the art is too high' and / or the art is too long and complicated, not suitable for high rated voltage _ set The following will continue to discuss 'these traditional devices made with various structural features' through various kinds of artisans' have difficulties and limitations that hinder the practical application of these devices in the market demand. Because the standard VDM0S does not have a charge-balance function. Features, therefore suitable for high-voltage semiconductor power devices, including devices with standard structures as shown in the diagram. According to the Ι-ν (current_voltage) 15 φ test, and the simulation analysis of this type of device further Confirmation: It is precisely because of this, the power, the right, the right, the f factor, that is, Jensen's extreme release. In order to meet the requirements of high voltage, the device with this structure is usually mixed with the drain drift zone. The hetero-concentration, lower, 'cause its on-resistance is relatively high. In order to reduce the on-resistance, the wafer size of such a device is usually large. The disadvantages described above are: the cost of the wafer is too high (per The number of wafers on a wafer is too small): It is not suitable for larger wafers in the standard package, so although the rice ginger is simple to process, it is produced. This is not high, but they are not satisfactory for high current and low impedance applications in the middle. The second type of semiconductor power device is a structure with two-dimensional charge balance, which can be used for a given impedance. Obtaining a breakdown voltage above the Jensen limit' or for a given breakdown voltage, a resistivity lower than the Jensen limit (on-resistance Rdsonx device area) can be obtained. This type of device structure is commonly referred to as super junction technology. In the superjunction structure, based on the PN junction and electrostatic field electrification plate technology in the oxide bypass device, in the drift drain region of a vertical device, parallel to the current direction 099101558 Form No. A0101 No. 6 Page / Total 59 Pages 0993094181-0 201029182

The charge balance allows the device to achieve a higher breakdown voltage. Figure 1 is a cross-sectional view with a superjunction device. By increasing the drain doping concentration in the drift region, the breakdown voltage is maintained. In the case of a change, the resistivity of the device is lowered (Rsp == impedance χ active region). By forming a Ρ-type (for the η-channel device) vertical column in the drain, the drain is completely depleted in the horizontal direction under the pressure, and the trench is pinched off and covered at the Ν + substrate from the drain high voltage. Road, thus achieving charge balance. This technique is already mentioned in the European Patent No. 0, 053, 854 (1982) and U.S. Patent No. 4, 754, the entire disclosure of which is incorporated herein by reference. In the foregoing publications, the vertical superjunctions are vertical-columns β as the bismuth and antimony dopants in the vertical training (10) device, as shown in the drawing, by doping a crucible with inverted walls, One of the doped columns is formed to obtain a vertical charge balance. It is also proposed to use doped floating islands to increase the breakdown voltage or to reduce the resistance, as disclosed in U.S. Patent No. 4,134,123 and U.S. Patent No. 6,037,632. The structure of this super-junction is still affected by the depletion of P-噚, the mask. However, due to the charge storage and conversion, etc., the 3⁄4 iteration is still limited by many technical problems. For the above-mentioned super-junction device, due to the complicated manufacturing process, slow progress of some processes and low yield, it is necessary to prepare Such devices are often quite complex, cumbersome, and require long processing times. It is true that these processes include multiple epitaxial layers and buried layers. Part of the structure = to the required depth of the channel to pass through the entire drift zone, and most of the process requires back etching or chemical mechanical polishing. In short, this traditional makeup and manufacturing method is slow and costly, and is not economical. ° Not suitable for a wide range of applications. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; Super junction device for charge balance epitaxy column. A channel metal etched semiconductor field effect transistor (MGSFET) is formed in the deep epitaxial layer and the top epitaxial layer over the area around the ice channel. However, the electric field of the channel gate of such a device is high and is easily damaged by voltage breakdown. Therefore, in addition to improving the structure and fabrication process of such a superjunction device, it is also necessary to mask the sensitive gate of the active cell during breakdown. Figures w - i to 1 c ~ ~ 3 show U.S. Patent No. 6,635,9,6, in most layers of the epitaxial layer, with P-floating device β, but these floating islands cannot Aligned to the gate or channel, and at the time of 'voltage breakdown, does not effectively protect the sensitive channel gate. Takay'a et al., "The Floating Island and Thick Bottom Oxide Channel Gate Metal Oxide Semiconductor Field Effect Transistor (FITM0S)", presented at the 17th Power Semiconductor Device &amp; In this paper, a structure is proposed, as shown in Fig. 1D, which shows that the floating P-emitter is implanted in order to make the drain and the surface of the gate; The gate can be separated from the P-region. However, since these are located in the 'sea channel; the P-implant region below the gate is in contact with the gate channel with the thick bottom oxide, the amount of current passing through the open circuit may be reduced. Therefore, in order to solve the above difficulties and limitations in power semiconductor device design and manufacturing process, it is necessary to find a new power device structure and manufacturing method. SUMMARY OF THE INVENTION [0003] One aspect of the present invention is to propose a new and improved device structure and method for manufacturing 099101558, forming a form number A0101 in a drifting area by a simple and convenient manufacturing process. Page 8 of 59 pages 0993094181 -0 201029182 Doped column 'to achieve charge balance. There is no need to slap thief chemical mechanical dragging' to streamline the processing steps, only need to form a single thin epitaxial layer, the epitaxial layer grows simultaneously in the deep channel and above the deep channel, and the top surface of the area around the deep channel 'forms a super junction structure . The epitaxial layer β knife in the channel forms an epitaxial column. Above the deep trench and above the surface of the deep trench region, the epitaxial layer of the shape (4), the trench MOSFET is formed in the top epitaxial layer. The two epitaxial layers can be grown simultaneously as a single-epitaxial layer. The channel gate of the 曰β body unit is further masked, and a voltage breakdown occurs. The doped mask region is implanted into the drift region under the gate through the trench gate to form a self-calibrated doping mask. The cover is forced to cover the sensitive gate, which solves the above-mentioned difficulties and limitations. The doped raspberry concealer area reduces the peak electric field at the channel gate; it also slows down the impact ionization speed and increases the breakdown. Voltage. The final structure improves the reliability and sharpness of the electrical parameters. The doped mask region is formed below the accumulation region below the trench gate and does not contact the trench

« ί _ I gate. There is a layer under the gate channel, which has a conductivity type of 7 sa哿m and a conductivity type of the accumulation region; :: &gt; ash is scaled if it can ensure that the mask area of the replacement does not touch the gate trench 4 The current that passes through the device is increased. Another aspect of the present invention is that the super junction structure and shape of the present invention can be used to flexibly adjust the range of breakdown voltages required. It is easy to manufacture and can be easily prepared by standard procedures using standard processing modules and equipment. Since the transistor portion of this structure, such as the channel gate double-diffused metal oxide semiconductor (DMOS), is self-aligned, the fabrication process can be further simplified. The above technical problems and limitations will be solved. 099101558 Form No. 1010101 Page 9/59 Page 0993094181 201029182 Green cuts, one aspect of the present invention is to propose a new and improved device structure and fabrication method for forming an epitaxial layer in a deep channel and In addition, the extended layer has a thin top epitaxial layer partially covering the top surface of the device. In addition, the portion of the extension layer is also formed as a metal oxide semiconductor field effect transistor (P-type in the case of an n-channel metal oxide semiconductor field effect transistor) in the bulk epitaxial layer. The metal halide semiconductor field effect transistor unit is a channel metal oxide semiconductor field effect transistor. The trench gate passes through the (4) trench sidewalls and the trench bottom doped implant region - except for the depth of the trench gate and the thin epitaxial layer opening to de-channel performance. The polydip structure layer is filled into the drift region of the gate trench through the gate trench before the gate impurity concentration is affected. The conductive type 4 of the body region of the doped mask region of the doped mask region is the same as the metal telluride semiconducting ^ ^ I and the doped mask region also bears the thumb mask The miscellaneous area is 5' self-aligned with the gate channel. The doped mask area may be a floating island: or an epitaxial layer in which the *#, ^ singer is connected (to the ''set') to the deep trench, and thus the body region is connected. In particular, the situation of floating islands is not ideal, because, * i 牟 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获 捕获The performance of the transistor unit can be controlled and adjusted by a simple and convenient manufacturing process. The super-junction structure of the present invention can be further improved and applied to a wider field. Another aspect of the present invention is to propose a new improved device structure and manufacturing method for a thin dip. A transistor unit is formed on the phased item layer, wherein the thin top layer covers the top surface of the deep trench and the top surface of the deep trench and the deep trench as an epitaxial layer. Office 099101558 Form Number_第_共"Ion through the deep channel sidewalls 0993094181-0 〇◎ 201029182 / Master (using and filling the deep channel epitaxial layer can adjust the opposite ions of the drift zone around the deep channel) Charge balance, Leakage-source resistance Rds〇n and performance parameters of the hitting and controlling device. Therefore, the method of ion implantation and "4" electric dust can be step-by-step, charge control and semiconductor power for different purposes. The performance of _ is $. The other aspect of the present invention is to construct and fabricate a new improved device. The upper portion is formed on the top surface of the upper surface of the vertical channel, covering: above the epitaxial layer. The bottom of the Tongqing Road is doped with the side material = vertical channel to flexibly adjust the channel secret It can be connected to the bottom of the implant to compensate for the P_ epitaxy, and with the channel and the gully, and to protect the proper accumulation to fill the gate channel through the 2 crystal spar. Perform ion implantation. Use vertical master Shield-sensitive trench gate. Another aspect of the invention resides in a new and improved device structure and method of fabrication to form a power cell with a deep trench gate in a thin 7-layer towel. Zhao unit, wherein the thin top layer is used as an epitaxial layer, and the area around the top surface above the epitaxial column is over the epitaxial column. The channel gate passes through the top thin epitaxial layer and extends to the bottom region, so that it is no longer needed. The bottom of the channel connected to the accumulation region is doped. The gate mask passing through the gate of the gate is shaped to form a calibrated impurity region, and the material channel is reduced for shielding during voltage breakdown. The cover sensitive (four) channel gate 1 channel doping injection is still 099101558 09930941; Form No. A0101 Page 11 / Total 59 pages 201029182 099101558 This is to ensure that her mask is touching the gate channel. The embodiment briefly describes a semiconductor power extension layer having a plurality of deep trench semiconductor substrates. The outer layer (four) further includes a simultaneously grown top portion overlying the deep trench top surface and the semiconductor. Area above the substrate The conductivity type of the epitaxial layer is opposite to that of the semiconductor substrate. In the top epitaxial layer, the top epitaxial layer of the 'shaped channel metal oxide semiconductor field effect transistor cell' serves as the local region, and the semiconductor substrate serves as the drain region. The charge balance between the epitaxial layer of the deep trench towel and the semi-conductive undercut (four) domain has a super junction effect. Each channel metal oxide semi-conducting FET unit also includes a drain gate layer and A gate mask is doped with _' and each gully gate. Self-proclaimed, and each/planning metal inspection semi-conducting (four) (four), U will mask the channel gate during electrical breakdown. In a typical implementation, each channel gate of a channel metal oxide semi-conducting field effect transistor is passed through a top epitaxial layer and filled with a gate dielectric material. In another exemplary embodiment, each trench of the oxide semiconductor field effect transistor cell has a top epitaxial layer that enters the top of the semiconductor substrate and is in the semiconductor substrate. There is a gate trench whose depth is greater than or equal to the thickness of the top epitaxial layer and is filled with a peach dielectric material and a gate conductive material. In another exemplary embodiment, the trench gate further includes a thumb-side doped region around the sidewall of the trench gate, and a gate-bottom doped region under the gate trench, wherein the gate sidewall is doped The conductivity type of the impurity region and the gate-bottom doping region is identical to the conductivity type in the semiconductor substrate. In another exemplary embodiment, the semiconducting germanium substrate further includes a region of the deep trench perimeter, and the doping threshold is 表单0101, page 12/59, 0993094181-0, 201029182, distributed from The doping concentration gradually decreases in the surrounding area, and the concentration decreases rapidly near the side wall of the deep channel. In another typical implementation: two MOSFETs, eight*'s on the sidewall of the channel's e-pole and the gate-bottom __ under the trench gate, with The gate sidewall doped region 'where the conductivity types of the gate sidewall doped region and the gate-bottom doped region are both opposite to the conductivity type in the semiconductor substrate. In another exemplary embodiment, the deep trench is in the semiconductor Near the second side of the substrate, a drain contact doped region surrounds the bottom of the deep trench for connecting the drain electrode. In another exemplary embodiment, the semiconductor power device further includes a bottom metal that forms a drain electrode that contacts the drain junction swap region. In another exemplary embodiment, the channel gate and the deep trench of the trench metal oxide field effect transistor cell are filled with an epitaxial layer.

And further stepping the epitaxial layer into a stripe with a gate mask doped region, as a floating doped region is disposed under the strip of the trench gate. In another exemplary embodiment, the trench gate of the trench metal oxide field effect transistor cell is also processed into a deep trench filled with a |4 κ κ 甩 甩 epitaxial layer with misalignment _, alternating to The gate is over to electrically connect the gate mask doping region to the body region of the transistor unit below the extended trench gate by the epitaxial layer in the via. The present invention also provides a method of fabricating a semiconductor power device on a semiconductor substrate. The method comprises the steps of: a) preparing a semiconductor substrate; b) opening a plurality of turns on the semiconductor substrate, and growing an epitaxial layer to fill the deep trench, and covering the top surface of the semiconductor with a top epitaxial layer, wherein The epitaxial layer portion and the top epitaxial layer in the epitaxial deep trench are a single growth at the same time, wherein the conductivity type of the epitaxial layer is the same as that of the semiconducting_bottom; C) forming a plurality of channel metal oxides in the top epitaxial layer Half 099101558 Form suffix A0101 Page 13 / Total 59 Page 0993094181 201029182 Conductor % effect tube list; t 'opening a plurality of trench gates, implanting a plurality of gate mask doping regions under the trench tearing, so that the channel of the transistor cell is extinguished when the voltage breakdowns the semiconductor power device, the top epitaxial layer The role of the region 'semiconductor's bottom is the role of the drain region, and the superjunction effect is obtained by the charge balance between the epitaxial layer portion in the deep, the semiconductor substrate, and the deep-channel P-knife of the semiconductor substrate. In a typical example, the method further includes implanting an ice channel sidewall with a first conductivity type dopant, forming a level concentration gradient in the semiconductor substrate region between the deep trenches, and passing Adjusting the deep trench sidewall implant to change the performance of the semiconductor power device H typical implementation, the method ❿ also includes implanting a dopant of a conductive type and a semiconductor substrate into the sidewall of the gate trench And the bottom. In another silver exemplary embodiment, the process of fabricating a semiconductor substrate includes preparing a single-layer semi-capture substrate, wherein the step of opening a plurality of deep trenches includes opening a plurality of deep trenches in the single-layer semi-conductive germanium substrate. In another exemplary embodiment, the process of preparing a semiconductor substrate includes preparing a bottom substrate, and growing a top underlayer at the chamber, the top substrate layer having a conductivity type that is the same as that of the portion. In another exemplary embodiment, the method further includes heavily doping at the bottom of the deep trench to form a drain contact region prior to growing the epitaxial layer; polishing the back of the substrate to expose the drain contact region. In another exemplary embodiment, the method further includes partially chemically polishing the top surface of the epitaxial layer to smooth it prior to forming the plurality of channel metal oxide semiconductor field effect transistor cells. [Embodiment] [0004] 099101558 Referring to the cross-sectional view of the metal oxide semiconductor field effect transistor device 1A shown in Fig. 2, a new '^99309418Η» form number of the present invention in terms of structure and manufacturing is proposed. Α0101 Page 14 of 59 Road 201029182 Road. A detailed description of the metal oxide semiconductor field effect transistor device will be described in Figure 3 below. The metal oxide semiconductor field effect transistor device is just located on the substrate 105, and the substrate 1〇5 has a function of draining the county with the doped bottom region 120', and the deep trench 130 filled with the epitaxial layer (such as 3 is shown as 'back grinding' doping. The substrate 1G5 further includes a top portion 125' deep trench m formed in the top portion 125. For example, for an n-channel MOSFET, the substrate 105 is n-type, and the epitaxial layer in the deep trench is? _type. The metal oxide semiconductor field effect transistor transistor unit is located on a single thin epitaxial layer, fills the epitaxial pillar channel 130' and covers the top surface around the ρ_ epitaxial pillar, and fills the Ρ-epitaxial filler into the pillar channel. The thin tantalum-epitaxial layer portion above the top surface also serves as the original region, and the surface is wound around the trench gate 145 filled with the _ pole polysilicon. The body drawer 15 is also surrounded by the trench gate 145. The surrounding source area 155. The trench gate 145 is padded with a gate oxide layer 140, filled with a polysilicon, and covered by an insulating layer 160 with a contact opening so as to pass through the source trench gate ". Region. #栅—Mask doped region 144 is masked, and a gate-mask is implanted through the thumb-polar channel when filling the channel with a gate polycrystal dream. Therefore, the gate is mask-doped. The miscellaneous region 144 and the trench gate 145 are self-aligned. The conductivity type of the gate-mask region 144 is the same as the conductivity type of the epitaxial layer filled in the epitaxial pillar channel 130. The device shown in Figure 2 has a single a thin epitaxial layer to form a trench gate, wherein the channel of the trench gate is filled with a gate polysilicon and an opening is formed therethrough. This new structure achieves performance requirements of the super junction, such as no more than "Jensen" Limit", the breakdown voltage does not vary with the thickness of the epitaxial layer grown on the starting substrate 099101558 Form s ar A0101 苐 15 pages / 59 pages 0993094181-0 201029182. Absolute breakdown voltage factor 疋 'ditch The depth of the track in the semiconductor substrate, and between the substrate regions The charge balance in the channel of the epitaxial column. The thickness of the epitaxial germanium growth is only a function of the deep channel width etched in the stone substrate. The conventional device must grow the epitaxial layer into a drift region, the thickness of the drift region and the required The breakdown voltage is proportional' so the conventional device does not have the above flexibility. The structure shown in the figure is flexible and can be produced by a simple manufacturing method. For example, to make a Jensen limit A device with a low resistivity and a wide range of breakdown voltages (eg, 200V to 900V) can be grown by a single epitaxial layer of a few micrometers with a single channel etch that is proportional to the desired breakdown voltage. (>2〇〇v is about 10-15 microns, &gt;600V is about 40-50 cm, &gt;900V is about 7〇~90 microns). In addition, the structure of the device is located on the top of the epitaxial layer. According to the channel gate double-diffused metal oxide semiconductor device, the device structure is self-calibrated, and the fabrication method is convenient and simple. The sensitive channel gate V45 of the device is partially g-channel 13 The seam above is farther, which also improves the reliability of the device, and saves unnecessary chemical mechanical polishing process. See Figure 3, cross-sectional view of the MOSFET device 1〇〇 According to the idea of the novel design and the basic structure shown in Fig. 2, the process is performed according to the processes described in Fig. 13A to Fig. 13N. The metal oxide semiconductor field effect transistor device 100 is located on the N type substrate, including a The N + doped bottom region 120 acts as a drain contact region and is in direct contact with the bottom drain electrode &apos; ο over. The deep trench replacement drain contact region 120 is provided through the epitaxial layer 13 。. A P-epitaxial layer is used. Fill each deep trench and cover the top surface around the trench and above the trench. Metallic germanide semi-conducting 0993094181-0 099101558 Form No. A0101 Page 16 of 59201029182 Body-effect transistor transistor unit is located in a single On the thin P- epitaxial layer, a single thin P- epitaxial layer is filled in the epitaxial pillar channel 130 and covered on the top surface around the P-extension pillar. The thin P-epitaxial layer above the top surface is formed by a P-body region 150 around the trench gate 145, and a trench gate 145 with a gate polysilicon is filled in the trench, and the trench passes through the top epitaxial layer 13 Opening. p — The body region also surrounds the source region 155 around the trench gate 145. The trench gate 45 is filled with a gate oxide layer 160, and the trench gate 145 is covered with an insulating layer 160 having a tab opening such that the source contact metal 17 above the metal barrier layer 165 contacts the trench gate Between 145, a source region, a P-type gate mask doping region 144 further shields the trench gate 145, and before the gate polycrystalline unicorn is filled with the gate trench, The polar channel is implanted into the N-substrate region 125. The gate mask doped region 144 protects the gate 145 that is sensitive to degradation when a voltage breakdown occurs in the metal oxide semiconductor material barrier device. The N substrate region 125 around the P-extension pillar 130 may be implanted through the sidewall of the deep trench 130 with N-dopant to obtain a level doping concentration gradient, and control the n-column electricity: the ijui is filled in the trench Balance in the P-outside level in the track to obtain the super-junction A or the drain current flow in the n-type drift region 丨25 perpendicular to the vertical MOSFET structure to obtain charge balance. When the MOSFET is in the off state, the drain current is depleted. In other words, the amount of charge of the germanium-epitaxial layer filled in the channel is substantially equal to the amount of electricity in the germanium-drift region near the germanium substrate, within the manufacturing tolerances. The control and adjustment of the charge in the helium-drift zone can be by doping the germanium-substrate, or doping the germanium-substrate with any other germanium-doped ions implanted in the sidewalls of the deep trench. For ideal conditions, the target 099101558 is 每 = Ν = 1Ε12 atoms per square centimeter. Form number Α0101 Page 17/59 page through 0993094181-0 201029182 during fabrication The over implant concentration, implant annealing, substrate doping concentration, epitaxial doping concentration, channel depth, width and shape, and other processing The more flexible the parameters of the process, etc., the more flexible the power control is, the more optimized the device structure is, and it is easy to tune to obtain a lower resistivity at a given breakdown voltage. The metal oxide semiconductor field effect transistor transistor unit further includes an N-type doped implant region 135-S along the gate side wall and an n-type doped implant region 135-B under the gate channel bottom. The doped implant regions surrounding the sidewalls and bottom around the gate 145 can be used to eliminate the MOSFET channel channel sensitivity to channel depth and P- epitaxial doping concentration. An embodiment of this novel structure is considered to be based on the formation of a high performance metal oxide semiconductor field effect transistor structure in the p_ epitaxial layer. The epitaxial layer is the same as the smallest or no: the p_ epitaxial layer of the back engraved together grows together. A metal-oxide-semiconductor field effect transistor - to operate, must have the source's conductivity type consistent with the drain, opposite the body, and have an accumulation region that connects the channel to the drain _L. After the channel is inserted into the vertical metal oxide semiconductor field effect transistor structure, the source is also at the top, and the channel is formed along the sidewall of the gate channel in the body 4 below the source. The accumulation zone must be shaped ........ into the body area and the drain. For the novel high voltage device described in the present invention, it is difficult to form a high performance vertical channel gate metal oxide semiconductor field effect transistor when the P- epitaxial growth on the top level surface of the N substrate is thick. If the P- epitaxial layer is thick, the gate trench must be deep in order to pass through the drift drain region. The combination of a deep channel and a thick p-body region will lengthen the channel and increase the channel resistance, ultimately resulting in a decrease in the performance of the vertical double-diffused metal oxide semiconductor structure. Thus, 'in the embodiment of the present invention' In the case of the P-epitaxial layer, additional dopants are implanted in the sidewalls and bottom of the gate trenches to make the thickness of the gate trenches generally 0. 8 to 099101558 Form No. A0101 Page 18 of 59 Page 0993 201029182 Typical gate channel thickness in the 1.5 micron range, thick to 3 microns. The two additional doping implants are used to compensate for the P-epitaxial regions in the accumulation and drain regions near the gate channel in order to obtain a high performance, short channel vertical channel double diffused metal oxide semiconductor. Device. Therefore, prior to processing the MOSFET device, implanting additional tilted and non-tilted implants in the gate trench will result in a high performance trench gate MOSFET device, It is again dependent on the P-epitaxial layer thickness and doping concentration in these regions. N_ ❹ at the bottom of the gate channel

The 099101558 type doping implant 135-B can also be used to protect the gate mask region 144 from contact with the gate channel 145. It should be noted that the embodiment in FIG. 3 represents a wear, over ρ _ epitaxy The gate channel of the layer and the additional Ν-, implant 135-s, 135-Β ~τ are used to optimize the metal emulsion semiconductor field effect, the performance of the tube without the need to fully compensate for Ρ-doping A region, i.e., an epitaxial layer on the sidewall of the gate trench. The implant is preferably a lion and a bell or a record. The energy should be in the range of 5 〇 KeV to 200 KeV. With the bottom implanted ΐ ΐ 霉 倾 倾 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应 应The implant dose should be in the range of 1E11 to 1E13. The frontal body implant can be used to form the body region 150' and maintain the channel region in a direction along the sidewall of the channel gate 145. Figure 4 is a cross-sectional view showing an alternative embodiment of a metal oxide semiconductor field effect transistor device similar to that shown in Figure 3, except that the sidewalls of the N-substrate region 125' are not implanted. The N dopant is introduced to achieve a charge control function through the fabrication process. Since it is assumed that the initial N-base has a sufficiently large dopant concentration to achieve charge balance with the p-type epitaxial layer grown in the deep channel, this embodiment does not require additional N-doping 0993094181-0 Form No. A0101 19th Page / Total 59 pages 201029182 area, introduced into the side wall of the deep channel. When the actual value of the doping concentration can reach the desired charge balance, i.e., the absolute value of the N charge = p charge = 1e12 particles/cm2, the doping concentration of the initial N-substrate is sufficient. When the substrate concentration can achieve charge balance within the required tolerance limits (for example, when the repeatability of the N_substrate with sufficient doping concentration is greater than +/- 10%), it is not necessary to Charge control is achieved by doping the implant. Figure 5 is a cross-sectional view showing an alternative embodiment of a metal oxide semiconductor field effect transistor device similar to that shown in Figure 3, except that the metal oxide semiconducting field effect transistor device is not Contains the sidewalls, as well as the channel shown in Figure 3, at the bottom of which is selected as 'mixed' areas 4_35 — B and 135 — S. When the depth of the trench gate 145 is large, and extends below the epitaxial layer 13 into the bottom region 125, it is no longer necessary to use the * trench to be implanted into the wall and the bottom of the trench. Zone to eliminate the sensitivity of the channel to the depth of the trench gate. 099101558 Section 6 is a cross-sectional view showing an alternative embodiment of a metal oxide semiconductor field similar to that shown in Figure 3, except that the metal oxide semiconducting tube is disposed. The depth of the trench gate is shallow, and the oxide semiconductor field effect device of the doped germanium layer includes a gate trench sidewall and a gate trench bottom doping implant region 135 - S and 135-B, respectively It is used to compensate the p_ epitaxial layer 13〇 and to ensure that the device has appropriate accumulation and channel regions. This embodiment is based on the structure in which the metal oxide semiconductor field effect transistor device has a thick P - epitaxial layer or a shallow gate channel, or both. The gate channel does not reach the N drain region. In order to ensure proper and efficient operation of the transistor, the lower portion of the gate trench must be doped as an N-doped region 135-B to form an active trench in the body region along the sidewall of the gate trench. The channel is connected to the drain of Form No. A0101 Page 20 / Total 59 Page 09qg 201029182. Conventional wafers have heavily doped substrates, as well as lightly doped top layers. However, the device shown in Figures 2 through 6 made of a conventional wafer does not have an epitaxial layer at the beginning. Although this can save a large amount of wafer cost, it has an additional process of bottom doping through deep trench and back grinding of the wafer. In addition, the apparatus shown in FIGS. 7 to 8 uses a conventional wafer with a heavily doped N + underlying substrate 121, and a sub-heavy-doped N-type top liner grown over the N + underlying substrate 121. The bottom layer 126. In a conventional wafer, such an N-type top substrate layer 126 is generally considered to be an epitaxial layer, and in this patent, to avoid confusion, it is referred to as a top substrate layer. Figure 7 is a cross-sectional view showing an alternative embodiment of a MOSFET device similar to that shown in Figure 3, except that the deep trench 130 filled with the epitaxial layer is now located at the top lining The bottom layer 126 extends into the heavily doped underlying substrate region 121. It is no longer necessary to form the individual drain contact regions 120 as shown in FIG. 3 by a separate doping implantation process. In contrast, in this embodiment, a heavily doped N + underlying substrate region 1·21 As a drain contact, a Ν-type top substrate layer 126 is also grown on top of the Ν + bottom substrate region 121. In order to save cost, the thickness of the top substrate region is generally small compared to conventional wafers. This embodiment does not necessarily require back grinding. The metal drain electrode 110 can be formed under the heavily doped underlying substrate region 〇 The drain contact doping implantation process at the bottom of the deep trench can be omitted, thus significantly simplifying the fabrication process. Figure 8 is a cross-sectional view showing an alternative embodiment of the MOSFET device similar to that shown in Figure 7, not 099101558 Form No. 1010101 Page 21 / Total 59 Page 0993094181-0 201029182 In the same place, the thickness of the deep trench 130 filled with the P-epitaxial layer is small MN + the underlying substrate 121. Fig. 9 is a plan view showing the strip structure of the semiconductor power device of the present invention. A strip-shaped structure is formed along with the epitaxial layer 130—the epitaxial deep channel grown together. The outline of the epitaxial deep trench 130 is indicated by a chain line. The channel gate 145 included in the transistor unit also forms a linear strip structure, and the trench gate 145 is filled by the gate oxide layer 14 around the source region 155 and surrounded by the body region 150. A self-calibrated gate mask doped region (not explicitly shown) is also formed as a floating strip under the trench gate 145. Figure 10 shows an alternative embodiment of another different transistor cell structure. The gate mask P-doped region 144 should be extended to the electro-crystal as shown in Fig. 1 by using the trench; 遂杨极丨4 5 as a cross-channel gate; p-column in a part of the dish unit The 130 region is connected to the 卞'-doped epitaxial pillar 130 below the body region 150 instead of processing the gate mask doping region 144 into a floating region below the trench gate 145. Figure u is a similar embodiment in which the extended channel gate 5 strip has taper portions 丨4 5 - τ B to reduce the drain-v source on-resistance Rd^oii to improve the device. Manufacturability (when filling the cross-shaped gate channel, it can be: can be: out: the current hole problem) ^ Figure 12 shows the same structure as the 11th, explaining the gate mask doped area protrusion 144 - how the TB is self-aligned under the gate trench 145, and how to diffusely contact the P-doped pillar 150 ^ under the main gate strip 145 and the gate bump 145 perpendicular to the main gate stripe - Below 1^, an exemplary mask doped region 144 is implanted. By inserting the gate mask doping region protrusions 144 - TB and p - the contact regions between the epitaxial pillars 130, p - the mask doping region 144 is electrically contacted to the p - body 15 region, the misalignment structure is reduced The effect of the channel width. As long as current flows through the channel gate projections 145-TB, another 099101558, Form No. A0101, Page 22 of 59, 0993094181-0 201029182 One side 'misplaced projections can also obtain better distributed current. Referring to a series of side cross-sectional views of Figures 13A through 13N, the fabrication steps of the charge balancing semiconductor power device as illustrated in Figure 3 are used. Fig. 13A shows that the initial dream base includes ~ substrate 205 having an impedance of about 10 ohm/cm. Substrate 205 does not initially have an epitaxial layer. A hard mask oxide layer 212 having a thickness of about 0.1 to 1.5 micrometers is set or thermally grown. Then use a trench mask with a critical dimension in the range of 1 to 5 microns (not shown) to perform an oxide etch, open a plurality of channel engraving windows 'and then remove the photo-anti-moist agent'. For a device with a working voltage of about 650 volts, a deep trench 214 with a depth of about 4 〇 to 50 μm is to be opened. Depending on the type of etcher and the etching reaction, the photoresist mask can also be used. The etching is prohibited and the channel is opened without using the hard mask oxide layer 212 as shown. The channel opening can be in the range of 1 to 5 micrometers, but it is appropriate to use 3 micrometers in most device applications (the channel opening is determined by the previously mentioned channel mask). Then the wafer clear '1 | i ί is washed. In Fig. 13B, the oxide layer on the surface of the bottom portion of the oxide layer 21 of the positive projection is formed by the oxygen enthalpy quenching field heat-length process; ; ' f I 4 is thicker, then the % can be used An anisotropic etch of the etch removes oxide from the bottom surface of the trench. If an optional reactive ion etching process is not employed, the thickness of the oxide layer 215 is between 0.015 and 0.1 micrometers. If an alternative reactive ion etching process is employed, the thickness of the oxide layer 215 is 0.0151. Between 0.4 microns. In order to form the drain contact region 220 directly under the deep trench 214, the drain contact implant is performed, that is, the erbium+ ion is implanted in a direction perpendicular to the tilt angle of the trench sidewall, that is, the vertical implant is performed, and the implant dose is greater than 1Ε15. The drain contact region 220 is implanted with a ruthenium-type ion such as a dish or arsenic. Oxide layer 215 along the sidewall direction 099101558 Form No. Α0101 Page 23 of 59 0993094181-0 201029182 'The protective sidewall is not affected by the high dose of the drain contact implant. In Fig. 13C, ruthenium-type ions such as phosphorus are implanted into the channel sidewalls to set the doping concentration in the ruthenium region. Depending on the depth of the channel, the tilt implant is implanted at a dose of 5Ε11 to 2Ε13 and a tilt angle of 5 to 15 degrees to form a crotch region 225 in the channel. In Fig. 13D, at very low oxygen and/or nitrogen. Under the environment, annealing at a high temperature of 1050 to 1200 °C for 3 〇 to 6 〇 minutes allows the Ν + drain contact region 220 to diffuse 'sidewall implant Ν-region 225 level diffusion. Zone 225 forms a level Ν-type concentration gradient with a concentration near the sidewall of the deep trench. In order to obtain charge balance (super gas junction effect), together with the Ρ-epitaxial layer 230 (to be grown), it is possible to adjust the area of the region beside the deep channel in the substrate 2 〇5 by sidewall implantation; ~: Alternatively, for sidewall implantation, the initial Ν-type concentration is used to form a dance 205 W to obtain a super knot effect. In Figure 13, the eclipse removes oxygen &quot; Huaguang 2 and 215, and grows a Ρ-epitaxial layer 230' where the erbium doping concentration is ^^ to ^" even higher. Ρ-epitaxial layer 23 (| The thickness is sufficient to fill the trench 214 » the channel 214 is about 3 microns wide, and the thickness of the ytbfcluat layer 230 in the Ν-region 22W portion is about 1.5 to 2.0 micrometers + the second cold oxide layer having a degree of about 0.5 to 1.5 micrometers as a hard mask. The film is 2^8 money: set, using a gate channel mask (not shown), etching the hard mask oxide layer 228, and then removing the photo-resistance agent. The width of the gate channel is generally 〇 5微米的范围内。 Through the _ etch method through the P_ epitaxial layer 23 〇, etch the trench gate opening 232 'channel depth is about 1 to 2. 5 microns, may pass through p Epitaxial layer 230, entering the N-doped region 225 between the epitaxial pillars 230 disposed in the channel 212, wafer cleaning, and then circular hole etching to smooth the gate channel structure and then cleaning Next wafer. In Figure 13G, remove the oxidized hard mask 228, then set a thin flash 099101558 Form No. A0101 Page 24 / Total 59 Page 〇 993 20 1029182 幕 Curtain layer 234, covering the sidewalls and bottom surface of the tree-pole channel 232. Deep p_-type implant collar ions (B11) 'energy between 200 and 600 KeV, dose between 1E12 and 1E13, zero tilt angle implant So that under the gate trench 232 in the n-doped pillar 225, a gate mask p-doped region 244 is formed. In Figure 13H, an N-type gate trench sidewall implant can be selected, tilted. The angle (implantation angle) is between +/-5 and 7 degrees to compensate for the p_ epitaxial layer 23〇. If the gate channel 232 is too shallow, the n-type gate channel with zero tilt angle is used. The bottom implants, compensates for the P- epitaxial layer 230, or ensures that the gate mask p_ doped region 244 does not contact the gate trench 232. The implant enters the gate trench sidewall and bottom surface, forming sidewall and bottom surface doping, respectively The regions 235-S and 235-B' eliminate the sensitivity of the channel of the metal oxide semiconducting FET device to the channel gate depth and the doping concentration/thickness of the P- epitaxial layer 230.

In the 13.1.::::, the gate oxide layer 234 is removed, and a gate oxide layer 240 having a thickness between 0.01 and 0.1 micrometers is formed, depending on the rated voltage of the device. A gate polycrystalline layer 245 is disposed in the gate trench 232. The most complicated method of gate polysilicon layer 245; if in-situ doping is not used, the gate polysilicon layer 245 is back etched starting or diffusing the doped top surface. In Fig. 13J, a bulk mask (not shown) can be used, the body is implanted with boron at a dose between 3E12 and 1E14, and then bulk driven at 1 to 1500 degrees Celsius, in the trench gate. In the epitaxial layer 230 around the pole 245, a P-body region 250 is formed. The bulk implant can form good contact with the body region and also ensure that the metal oxide semiconductor field effect transistor channel region is always above the gate sidewall implant 235-S. The 13th [Fig. 099101558 represents the source doping implant. The source implant mask (not shown in the figure, Form No. Α0101, page 25/59 pages 0993094181-0 201029182) can be used to protect this position to form a p_body contact. The source is implanted with a source ion such as a Kun ion at a potential of about 7 〇 KeV, a dose of about 4E15, and a zero tilt angle, and then a source annealing operation is performed at 8 〇〇 to 95 〇 Celsius. Diffusion source region 255. In Fig. 13L, a dielectric layer 260 formed by a low temperature oxide arrangement (LT0) and a bovine acid (BPSG) layer 260 containing boric acid are formed on the top surface, and then a bismuth glass flow operation containing boric acid is performed. Contact openings are etched through a bismuth glass layer 26 containing boric acid using a contact mask (not shown). The P+ body contact implant is optional and then reflows after the body contacts are implanted. In the 13th 蹰, a barrier metal is provided covering the top surface of the barrier metal layer 265, and then provided and thickened. The metal forms the source metal layer 270. Metal mask (not shown in the figure for 凼θ is used to etch the source metal 260 and the gate metal (not shown) and form a pattern. The dielectric layer is provided to passivate the surface of the device. The pattern of the passivation layer is used to form a bond. The opening of the area (not shown in the figure), the whole process is completed, and the end - i . | e becomes the final town. For the sake of simplicity, this: some of the production process is not detailed here. In Fig. 13N, after the back grinding, the low doped portion of the substrate 205 is removed from the bottom surface of the substrate to form a back metal layer 21' to form a contact with the drain region 22 when the doping concentration is high. The back metal layer 210 can be formed by directly providing a TiNiAg layer on the back side of the wafer. The thickness of the back grinding process can be controlled to a few micrometers or even micrometers, enabling reliable back contact to form the drain electrode layer 210 to contact the N+ drain. The polar contact area 220. Although the present invention has been proposed in the prior art, these disclosures should not be limited. Those skilled in the art, after reading the above description, must be able to grasp various other kinds. Variations and corrections. For example, at 099101558, Form No. A0101, page 26/59, 0993094181-0, 201029182. The above embodiment uses an n-channel device body, but the invention can be modified by changing the conductivity of the region. All changes encompassed by the scope of the appended claims::: All fall within the scope of the invention and the true intent. / [0005] Although the content of the present invention has been The present invention has been described in detail, but it should be understood that the above description should be construed as limiting the invention. It will be apparent to those skilled in the <RTIgt; The scope of the present invention should be limited by the scope of the appended claims. [FIG. 1A to 1B] FIG. 1A to FIG. 1B show a cross-sectional view of a conventional vertical power device structure manufactured by a conventional method; 1 to: 1C-3: the figure shows a cross-sectional view of a floating island formed in a bulk epitaxial layer not aligned with the gate and gate channels; The cross-sectional view of the doped region of the doped region below the entanglement trench of the trench is shown in Fig. 1 to Fig. 8 to Fig. 2 to Fig. 8 for the high voltage power with the super junction structure of the present invention. The cross-section of the present invention is shown in Fig. 1. Fig. 9 to Fig. 12 show top views of various layout structures for arranging the channel mask doping regions; Figs. 13A to 13N are diagrams for fabricating a high voltage power device. The cross-sectional view of the process, which is similar to that shown in Figure 3, with a superjunction structure and a self-calibrated trench mask doping region. [0006] [Major component notation] 100: Metal oxide semi-conductive field effect transistor device 099101558 Form No. 1010101 27th/Total 59 Page 0993094181-0 201029182 1 05: Substrate 110: Metal drain electrode 120: N + doped bottom region · 121 : N + bottom Substrate 125: top portion, N substrate region, n-type drift region 126: Ν-type top substrate layer 130: deep trench, epitaxial layer 135-S: Ν-type doped implant region 135-Β: Ν-type doping Miscellaneous implant region 140: gate oxide layer 144: thumb-mask mask change region 145: trench gate ' : :: S' § sti 4:# f)ru:]r ying u 145 —ΤΒ, 144 —ΤΒ : Projection 150 : Body region 15 5 : Source region 160 : Insulation layer 165 : Metal barrier layer 170: source metal 205: substrate 210 · back metal layer, drain electrode layer 212: hard mask oxide layer 214: deep channel 215: oxide layer * 220: drain region, N + drain contact region 225 : N-doped region, N-doped pillar 228: hard mask layer 099101558 Form No. A0101 Page 28 / Total 59 Page 0993094181-0 201029182 : p- Epitaxial layer: Gate channel: Thin screen layer -S: Sidewall_B: bottom doping region: gate oxide layer: P-doped region: gate polysilicon layer: P-body region: source region: dielectric layer, germanium glass layer: source metal layer 099101558 Form No. A0101 29 pages / total 59 pages 0993094181-0

Claims (1)

201029182 VII. Patent application scope: 1 - A semiconductor power device, comprising: a semiconductor substrate containing a plurality of deep trenches; an epitaxial layer filled in the deep trench, the epitaxial layer including a simultaneously a grown top epitaxial layer 'covers a region on the top surface of the deep trench, and the semiconductor substrate, wherein the epitaxial layer has a conductivity type opposite to the semiconductor substrate; a plurality of channel metal germanide semiconductor field effect transistor cells, Provided in the top epitaxial layer, the top epitaxial layer is used as the body region, and the semiconductor substrate is used as the drain region to obtain the super-equivalent balance between the epitaxial layer in the deep trench and the region in the side of the semiconductor substrate. a junction effect; and each of the plurality of channel metal oxide semiconductor field effect transistor cells further includes a trench gate and a trench disposed therewith and associated with each trench metal oxide semiconductor field effect transistor unit The gate gate is substantially calibrated with a gate mask doped region' so that when voltage breakdown occurs, the mask is immersed in the gate, where the gate is covered The semiconductor power device of the first aspect of the invention is characterized in that: f Μ the gate mask doping region is disposed at a distance from the trench gate. The bottom surface of the pole is at a certain distance and does not contact the trench gate. 3. The semiconductor power device according to claim 1, further comprising: said gate disposed under each channel gate and implanted with a dopant of the same conductivity type as the substrate A pole bottom doped region is located above the gate mask doped region. The semiconductor power device according to claim 1, wherein the trench gate is located in the top epitaxial layer and between the deep trenches. 5. The semiconductor power device of claim 1, wherein the trench gates of each of the trench metal oxide semiconductor field effect transistor cells extend into the The top epitaxial layer has a depth of the gate channel that is less than or equal to the thickness of the top epitaxial layer. 6. The semiconductor power device of claim 1, wherein each of the channel gates extends and penetrates the top epitaxial layer into the top of the semiconductor substrate. . 7. The semiconductor power device according to claim 1, wherein the semiconductor power device is characterized in that The trench gate further includes a gate sidewall doped region surrounding the trench gate sidewall, and a doped region at the bottom of the Sttectii Q# pole, wherein the gate sidewall doped region The conductivity type of the singular singer is the same as the conductivity type of the semiconductor substrate. The semiconductor power device of claim 1, wherein the semiconductor substrate further comprises a deep trench surrounding the semiconductor device. The region has a level of doping concentration gradient, and the concentration gradually decreases from the region immediately adjacent to the sidewall of the deep channel. The semiconductor power device according to claim 2, wherein each of said metal oxide semiconductor field effect transistor units further comprises 099101558 0993094181-0, form number A0101, page 31/Bing 59 pages. 201029182 a gate sidewall doped region surrounding the trench gate sidewall, and a gate bottom doped region under the trench gate, wherein the gate sidewall doped region and the gate bottom The conductivity type of the doped region is the same as the conductivity type of the semiconductor substrate. The semiconductor power device of claim 1, further comprising: the semiconductor surrounding the bottom of the deep trench A drain near the bottom surface of the substrate contacts the doped region. 11. The semiconductor power device according to claim 1, wherein the gate mask doping region constitutes an island J.. 12 as described in claim 1 of the patent application. The semi-conducting power is characterized in that '...black; the gate mask doping region is electrically connected to the body region of the metal oxide semiconductor field effect transistor unit. 13. For example, please refer to the semi-conductor: body power splitting described in item 1 of the patent scope, which is characterized by ::::::; channel metal oxide semiconductor 'effect tube unit The trench gate, and the deep trench filled with the epitaxial layer, in the form of stripes, the gate mask doped region is disposed on the trench of the trench gate Below, as a floating doping area. 14. The semiconductor power device according to claim 1, wherein the channel metal pole of the channel metal oxide semi-conducting field effect transistor unit is formed with a protruding portion. The stripe form 'the projections extend toward the deep channel direction filled with the epitaxial layer' so that the convex 099101558 form number A0101 section 32 / code 59 page 0993 201029182 out of the channel grid The gate mask doped germanium under the pole is electrically connected to the body region of the transistor 15 ❹ 16 17 unit by the epitaxial layer filled in the deep trench. The semiconductor power device of claim 1, wherein the trench gate of the channel metal oxide semiconductor field effect cell unit further has a stripe with a misaligned protrusion. In the form of the dislocation protrusions on opposite sides of the trench gate, alternately extending toward the deep trench filled with the epitaxial layer to place the trench under the trench The gate mask doping region of the square is electrically connected to the vessel of the electro-ceramic unit by the epitaxial layer filled in the deep trench: | as claimed in the patent Vail 1 The semi-guided power device of the present invention, wherein the semiconductor substrate further comprises a heavily doped underlying substrate and a substrate grown on the underlying substrate, the deep channel of the towel is formed. In the top substrate. The device of claim 12, wherein the deep channel extends to the bottom portion as described in claim 18, and the semiconductor power device according to the fourth aspect of the patent application is characterized by the deep trench described in 19 099101558. The trace extends into the top of the substrate 'but does not touch the bottom of the sprinkle. 4 The semiconducting (four) rate is 0, which is characterized by 'comprising: one semi-conducting containing deep trenches' Single extension of semiconductor extinction; 33rd buy / total 59莨〇9ί Form No. Α0101 J J993094181-0 201029182 and a plurality of channel metal oxide semiconductor field effect transistors formed in the epitaxial layer above the semiconductor surface a cell in which a portion of the semiconductor substrate beside the deep trench is responsible for the drift layer of the channel metal oxide semiconductor field effect transistor unit, and wherein the channel of the channel gold oxide semiconductor field effect transistor cell a gate formed in the sub-epitaxial layer above the drift region between the deep trenches and passing between the drift region and the portion of the epitaxial layer in the deep trench Balance 'to make the semiconductor power device get super junction effect; and - a gate « doped region, placed under the gate of each channel, and is basically calibrated with each channel gate for oxidation of each channel metal When the voltage breakdown occurs in the semiconductor FET unit, the film is removed. 20. The semiconductor power device according to claim 19, wherein the gate mask doping region is disposed at a bottom surface of the trench gate. At a certain distance, there is no contact with the channel gate. 21 . - Forming a semi-conducting defect on the semiconductor substrate: § method, its characteristic I: .. Preparing a semiconductor substrate; 开 opening a plurality of deep trenches in the semiconductor substrate, growing a top epitaxial layer, filling the deep trenches with the top surface of the semiconductor substrate Wherein a portion of the epitaxial layer in the deep trench and the top epitaxial layer are both grown simultaneously as a single layer, wherein the conductivity type of the epitaxial layer is opposite to that of the semiconductor substrate; and in the top epitaxial layer, a plurality of gate trenches, and implanting a plurality of gate mask doped regions under the gate trenches to form a plurality of trench metal oxide semi-conducting FET units for Semiconductor 0993094181-0 099101558 table grass No. A0101 Page 34 / Total 59 Page 201029182 When the voltage breakdown of the power device occurs, the channel b gate of the transistor unit is covered, and the top epitaxial layer acts as the impurity region. The semiconductor substrate is responsible for the drain region. The effect of achieving a charge balance between a portion of the epitaxial layer in the deep tunnel and a portion of the semiconductor substrate beside the deep trench, obtaining a superjunction 22. ❹ 23 . Effect in the semiconductor lining as described in claim 21 A method of forming a semiconductor power device on a substrate, further comprising: implanting a dopant having a first conductivity type through a sidewall of the deep trench to form the deep channel in the semiconductor substrate A level concentration gradient is formed in the region between the regions, and the immersive property of the semiconductor power device is adjusted by adjusting the deep trench sidewall implant, as described in claim 21, in the semi-conductor lining A method of forming a semiconductor power device on a bottom, wherein: / ❹ 24. said step of implanting a plurality of gate mask doping regions under said thumb-pole channel Included at a distance below the bottom surface of the gate channel, the gate mask doping region implanted in the plurality of gates is not in contact with the The method for forming a power device on the basis of the patent application (4) 21, further comprising: passing through the bottom of the gate channel, implanting a doping region of the same conductivity type as the substrate 099101558 The same foreign matter is implanted into the bottom. The semiconductor 0993094181-0 26 is formed on the sidewalls of the gate trench and the bulk substrate as described in the twenty-first part of the patent application, in the semi-conductive form number A0101, page 35/59. 201029182 The method of power device, further comprising: « said step of preparing a semiconductor substrate comprises preparing a single-layer semiconductor substrate, and wherein said step of opening a plurality of deep trenches comprises comprising a single-layer semiconductor A plurality of deep trenches are opened in the substrate. The method of forming a semiconductor power device on a semiconductor substrate according to claim 21, further comprising: said step of preparing a semiconductor substrate further comprising preparing a heavily doped bottom portion The substrate is grown with a top substrate layer over the bottom substrate, wherein the top substrate layer has the same conductivity type as the bottom substrate. 28. The method of forming a semiconductor power device on a semiconductor substrate of claim 26, further comprising: heavily doping the bottom of the deep trench prior to growing the epitaxial layer Forming a drain contact region; and back grinding the substrate to expose the drain contact region. The method of forming a semiconductor power device on a semiconductor substrate according to claim 21, further comprising: the step of forming said plurality of channel metal oxide semiconductor field effect transistor units Previously, the top surface of the epitaxial layer was partially chemically mechanically polished to smooth the top surface. 0993094181-0 099101558 Form No. A0101 Page 36 of 59