TWI267151B - Processing method during a package process - Google Patents

Processing method during a package process Download PDF

Info

Publication number
TWI267151B
TWI267151B TW093131187A TW93131187A TWI267151B TW I267151 B TWI267151 B TW I267151B TW 093131187 A TW093131187 A TW 093131187A TW 93131187 A TW93131187 A TW 93131187A TW I267151 B TWI267151 B TW I267151B
Authority
TW
Taiwan
Prior art keywords
providing
conductive
packaging process
bumps
processing method
Prior art date
Application number
TW093131187A
Other languages
English (en)
Other versions
TW200612504A (en
Inventor
Chien Liu
Meng-Jen Wang
Sheng-Tai Tsai
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW093131187A priority Critical patent/TWI267151B/zh
Priority to US11/249,485 priority patent/US20060084199A1/en
Publication of TW200612504A publication Critical patent/TW200612504A/zh
Application granted granted Critical
Publication of TWI267151B publication Critical patent/TWI267151B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Description

1267151 七、指定代表圖： (一） 本案指定代表圖為··第（二B)圖。 (二) 本代表圖之元件符號簡單說明： 1 〇晶粒 !2 凸塊 14 引腳 16 導電表面 18 刻槽 示發明特徵的化學式·· 八、本案若有化學式時，請揭示最能顯 九、發明說明： 【發明所屬之技術領域】 的結構，特別是 f發明係有關一種晶粒結合至多層板中製作 提供一種可整合晶粒與多層板的複合式結構。 【先前技術】 覆晶封裝製程技術主要是在晶粒所在金屬塾上長成奶凸塊，而於基 板上生成與晶粒凸塊相對應之接點，接著將翻轉之晶粒對準基板上之 接點’將晶粒與基板所有！/〇點進行接合。由於覆晶封裝製程具有良 好電器特性、高輸出/人接點密度，且能縮小IC尺寸增加每片晶圓產 出，已被看好為未來極具潛力之構裝方式。 1267151 覆晶的標準化製程，包括組裝前置作業的凸塊製作(Bumping)、晶圓切 割(Die Saw)，以及组裝作業的晶粒接合出⑽出叩）、迴銲、清 洗(Clean)、填膠(Underfill)、膠烘烤固化(Cure)等。其中，於組裝作業 時，係將晶粒經銀膠(EP〇xy)與引線架(Lead F麵雜著，然後用金線 (Au Wire)將晶粒上之輸出/入銲點與引線架上之内引腳連接，用樹脂予 以封合保護以避免受外力破壞。 如第-圖所不，為傳統覆晶進行晶粒回銲時的側面示意圖…般而言， 將晶粒11G轉使得具有凸塊m的表面朝下固定至導線細上未示) 之引腳 114 (lead finger)。 導線木乃1C封裝之^承載體，其觀目前被使_有銅合金及鐵_錄 (Alloy-42)合金。然而’由於凸塊112的材料不斷發展以增進其效能， 因此凸塊112與引腳114的介面上亦導致若干問題產生。問題之一， 疋當凸塊112於畴時，部分的凸塊材料可因流動性的增加或其他介 面作用力(interaction)而擴散至引腳114上。上述的情形造成凸塊ιΐ2 接近引腳114之表面的部分會有細化(neddng)的現象產生，如此會造 成整個封裝轉於信賴麟效能上的損壞。 【發明内容】 ;述者’Y、中，有關封裝覆晶晶粒於導線架上時可能衍 生的效能降低’於此提供—於覆晶晶粒㈣中的處理方法， 1267151 於回銲中利用凸塊本身的重力，可避免凸塊於引腳表面上擴散開 來。 再者’爲了避免凸塊產生細化的現象，於此提供一種覆晶與 導線木封裝時的處理方法，當欲⑽凸塊時，將整個封裝結構翻 轉，使得覆晶晶粒之具有凸塊的表面朝上，湘凸塊本身的内聚力 與覆晶晶粒之重力，可減少凸塊細化的發生。 根據上述之目的’本發明之_實施例，提供一種處理方法， 用於進行―回銲步驟時，首先提供-封裝結構，其包含至少 覆曰曰複數個導電凸塊與—導線架彼此固^。其令覆晶以 -銲墊表面與複數個導電凸塊連接，導線架以一導電表面與 後數個導電凸塊連接，此時銲墊表面係為一與重力方向相同 的方向。_封裝結構之後再回銲被翻轉的封裝結構。 【實施方式】 本發月之實關用不意圖詳細描述如下，在料本發明之實施例時， 表不封裝結翻部份纽大齡並制，财齡此作為有限定的贫 知。此外，在實際的封裝結構與方法中，應包含此結構中其他必 部分。 的 其次，當本發明之實施例圖式中的各元件或結構以單一元件或結構 描述說明時，不應以此作為有限定的認知，即如下之說明未特別強調 1267151 數目上的限制時’本發明之精神與應用範圍可推及多數個元件或結構 並存的結構與方法上。 第一A圖所不為本發明之一實施例進行晶粒接合的側面示意圖。參照 第A圖於曰曰粒1〇欲固定於導線架(圖上未示)之引腳μ的步驟中， 係將阳粒1G轉使得具有凸塊12的表_下，然後固定至引腳“之 一導電表面16上。於一實施例中，晶粒10係為-裸晶，可以為任何 需要封裝的晶粒，例如半導體元件、域測元件或光電元件等等。凸 免2則為錫氣凸塊(s〇lder bump)、金凸塊(神^伽幻或無錫錯凸塊等鲁 等。要說明的是，晶粒10與凸塊之間尚形成一導電結構(圖上未 示），例如凸塊下金屬結構。 其-人’引腳14 ’其材料可以為銅合金或鐵鎳合金為主的材料，利用引 腳末端的導電表面16與凸塊12黏接固定。於一實施例中，尚利用點 膠機點膠(dispensing)的方式將一般_著継於引腳14之導電表面16 上與凸塊Π對應的位置上或周圍形成黏著結構藉以作為後續形成角落魯 鍵結(comer bond)，但不限於此。此外，引腳14的幾何形狀，例如具 有刻槽18(notch)，並不限於此。 於此固定步驟(mounting process)中，係將包含引腳14的導線架欲固定 的表面朝上(face-up orientation)，即與重力方向相反的方向。另一方面， 匕έ凸塊12的晶粒10朝下(face-down orientation)，即與重力方白 1267151 相同的方向，兩者黏著固定。於—實施例巾，以麵化(prc_euring)的 方式將兩者黏著固定並形成上述之角落鍵結。 參照第二B _示為本發明之—實施例進行回銲之前_面示意圖。 當欲進行轉時，先行將上額定步驟t的翻結構轉，再進行回 銲的步驟。當整個結構翻轉時，形成晶粒1〇為整個結構的最底部元 件，其具有凸塊12的録墊表® 20朝上，即與重力方向相反的方向。 另一方面，引腳14與凸塊12固定黏著的導電表面16朝下，即與重力 方向相同的方向。當回銲時，溫度升高造成凸塊12的材料之流動性增 加。此時流動性增加的凸塊12因内聚力與重力的作用，會略朝向晶粒 1〇表面集中，由於凸塊下金屬結構的存在與幾何形狀，可以限制流 動性增加的凸塊12不會過度擴散。另一方面，上述情形亦減少凸塊12 擴散於引腳14之導電表面16,進而避免凸塊12於接近介面的部分產 生細化的現象。 根據上述，本發明之一實施例中提供一種封裝製程中之處理方法， 首先提供一晶粒結構及一導線架。晶粒結構具有複數個導電 凸塊，例如锡鉛凸塊或金凸塊，配置於一銲墊表面上，導線 架，例如以鐵/鎳為主材料或以鋼為主，包含複數個導電引腳。 之後，固定，例如以預固化方式，導電凸塊至導電引腳上， 其中銲墊表面20係朝向與重力方向相同的一方向。接著， 轉動被固定的晶粒結構與導線架，使得銲墊表面2〇係朝向 1267151 與重力方向相反的-方向，之後，回銲被轉動的晶粒結構與 導線架。 以上所述之實施例僅係為說明本發明之技術思想及特點，其目的在使 热習此項技藝之人士能夠瞭解本發明之内容並據以實施，當不能以之 限定本發明之專利麵，即大凡依本發明·私精神^之均等變 化或修飾，仍應涵蓋在本發明之專利範圍内。 【圖式簡單說明】 第一圖所示，為傳統覆晶進行晶粒回銲時的側面示专圖。 第二A圖所动本發明之-實施舰行晶轉合賴面示意圖。 第二B騎示為本發明之-實施舰行轉之前_面示意圖。 【主要元件符號說明】 1〇 晶粒 12凸塊 14引腳 16導電表面 18 刻槽 20 銲墊表面 110晶粒 U2凸塊 1267151

Claims (1)

1267151
十、申請專利範圍： 1 · 一種封裝製程中的處理方法，用於進行一回銲步驟時，包含： 提供一封裝結構，其包含至少一覆晶、複數個導電凸塊與一 導線架彼此固定，其中該覆晶以一銲墊表面與該複數個導電凸 塊連接，該導線架以一導電表面與該複數個導電凸塊連接，此 時該導電表面係朝向一與重力方向相反的方向； 翻轉該封裝結構；及 回銲(reflow)該被翻轉的封裝結構。 2·如申請專利範圍第1項所述之封裝製程中的處理方法，其中 該翻轉步驟使得該銲墊表面朝向一與重力相反的方向。 3·如申請專利範圍第1項所述之封裝製程中的處理方法，其中 該提供步驟包含提供複數個錫鉛凸塊作為該複數個導電凸塊。 4·如申請專利範圍第1項所述之封裝製程中的處理方法，其中 該提供步驟包含提供複數個金凸塊作為該複數個導電凸塊。 5·如申請專利範圍第1項所述之封裝製程中的處理方法，其中 該提供步驟包含提供該導線架之複數個鐵/鎳引腳以提供該導 電表面。 12 1267151 6·如申請專利範圍第1項所述之封裝製程中的處理方法，其中 該提供步驟包含提供該導線架之複數個以銅為基本之引腳以提 供該導電表面。 7. 如申請專利範圍第1項所述之封裝製程中的處理方法，其中 該提供步驟包含以點膠方式將複數個黏著結構形成於該導電表 面對應每一該導電凸塊的位置。 8. —種封裝製程中的處理方法，包含： 提供一晶粒結構，該晶粒結構具有複數個導電凸塊配置於一 銲墊表面上； 提供一導線架，該導線架包含複數個導電引腳； 固定該複數個導電凸塊至該複數個導電引腳上，其中該銲墊 表面係朝向與重力方向相同的一方向； 轉動該被固定的晶粒結構與該導線架，使得該銲墊表面係朝 向與重力方向相反的一方向；及 回銲(reflow)該被轉動的晶粒結構與該導線架。 9·如申請專利範圍第8項所述之封裝製程中的處理方法，其中 提供該晶粒結構之步驟包含提供複數個錫鉛凸塊作為該複數個 導電凸塊。 · 13 1267151 10·如申請專利範圍第8項所述之封裝製程中的處理方法，其中 提供該晶粒結構之步驟包含提供複數個金凸塊作為該複數個導 電凸塊。 11·如申請專利範圍第8項所述之封裝製程中的處理方法，其中 提供該導線架之步驟包含提供一鐵/鎳為主材料的該導線架。 12·如申請專利範圍第8項所述之封裝製程中的處理方法，其中 該固定步驟包含以預固化(pre-cure)方式處理該複數個導電凸 塊0 13·如申請專利範圍第8項所述之封裝製程中的處理方法，其中 該固定步驟包含以點膠方式形成複數個黏著結構於每一該導電 引腳上及預固化（pre-cure)方式處理該複數個導電凸塊。 1267151 L...—….a… ....... 112 112 110 Γ 114 114 第一圖
第二A圖 18 18
TW093131187A 2004-10-14 2004-10-14 Processing method during a package process TWI267151B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW093131187A TWI267151B (en) 2004-10-14 2004-10-14 Processing method during a package process
US11/249,485 US20060084199A1 (en) 2004-10-14 2005-10-14 Processing method during a package process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW093131187A TWI267151B (en) 2004-10-14 2004-10-14 Processing method during a package process

Publications (2)

Publication Number Publication Date
TW200612504A TW200612504A (en) 2006-04-16
TWI267151B true TWI267151B (en) 2006-11-21

Family

ID=36181280

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093131187A TWI267151B (en) 2004-10-14 2004-10-14 Processing method during a package process

Country Status (2)

Country Link
US (1) US20060084199A1 (zh)
TW (1) TWI267151B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010520888A (ja) * 2007-03-09 2010-06-17 アメリカ合衆国 神経変性の治療としてのニトロキシドラジカル

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4989069A (en) * 1990-01-29 1991-01-29 Motorola, Inc. Semiconductor package having leads that break-away from supports
US6794202B2 (en) * 2000-03-15 2004-09-21 Tessera, Inc. Assemblies for temporarily connecting microelectronic elements for testing and methods therefor
JP3597754B2 (ja) * 2000-04-24 2004-12-08 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
JP4744689B2 (ja) * 2000-12-11 2011-08-10 パナソニック株式会社 粘性流体転写装置及び電子部品実装装置

Also Published As

Publication number Publication date
US20060084199A1 (en) 2006-04-20
TW200612504A (en) 2006-04-16

Similar Documents

Publication Publication Date Title
TWI220781B (en) Multi-chip package substrate for flip-chip and wire bonding
TW546795B (en) Multichip module and manufacturing method thereof
TWI230104B (en) Electronic device
TW544901B (en) Semiconductor device and manufacture thereof
TWI284973B (en) Flip-chip joint structure, and fabricating process thereof
TWI261330B (en) Contact structure on chip and package thereof
TW201112370A (en) Semiconductor flip chip package
US20090065943A1 (en) Microelectronic Assembly Having Second Level Interconnects Including Solder Joints Reinforced with Crack Arrester Elements and Method of Forming Same
JPWO2006064534A1 (ja) 半導体装置
TWI402951B (zh) 無鉛半導體封裝件
TW200805596A (en) Method of packaging semiconductor die
JP2001110926A (ja) フリップチップパッケージ
TW200924087A (en) Chip structure, substrate structure, chip package structure and process thereof
TW200421587A (en) Multi-chip module
TWI236109B (en) Chip package
US10943795B2 (en) Apparatus and methods for creating a thermal interface bond between a semiconductor die and a passive heat exchanger
TWI267151B (en) Processing method during a package process
JP3670625B2 (ja) 半導体装置およびその製造方法
TWI375307B (en) Flip chip package structure and method for manufacturing the same
TW200419748A (en) Under bump metallurgy and flip chip
JPH11168116A (ja) 半導体チップ用電極バンプ
CN101800181A (zh) 覆晶封装结构的制造方法
TWI234256B (en) Process for fabricating semiconductor package having heat spreader and the same thereof
JP3594442B2 (ja) 半導体装置
JP2004259886A (ja) 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法