TWI234256B - Process for fabricating semiconductor package having heat spreader and the same thereof - Google Patents
Process for fabricating semiconductor package having heat spreader and the same thereof Download PDFInfo
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- TWI234256B TWI234256B TW091132643A TW91132643A TWI234256B TW I234256 B TWI234256 B TW I234256B TW 091132643 A TW091132643 A TW 091132643A TW 91132643 A TW91132643 A TW 91132643A TW I234256 B TWI234256 B TW I234256B
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- heat sink
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
1234256 五、發明說明（1) 尤指 【發明領域】： 本發明係關於一種半導體封裝件製法及其結構’ 一種具有散熱件（Heat Sink)，並以覆晶型態（F1 lp Chip)將晶片接置於銲球（Solder Bal 1)同側之基板底 部覆晶式半導體封裝件製法及其結構。 【發明背景】： 隨著晶片集積度（Integration)不斷提昇，半導體 封裝件對於電性品質及散熱效率的要求亦愈來愈高。為滿 足電子產品高功能性及高處理速度之發展趨勢，業界嘗試 將多片半導體晶片載置於同一封裝結構内，而開發出多晶 片半導體封裝件。 傳統型悲的多晶片半導體封裝件，如第4圖所示，係 先備妥一基板2 1 0，該基板2 1 0具有一上表面2丨〇 a及一相對 之下表面210b，並運用覆晶（Flip chip)或銲線電性連 接（Wire Bonded)等方式將兩片以上晶片211 212安琶於 基板21〇之上表面210a上，該基板21。之下表 汉有多f鈐球2 1 3，以使完成模壓技術（M〇 i d i ng)之封裝 結構能藉由該等銲球2丨3電性連接至外部裝置（如印刷電 路板）上。1234256 V. Description of the invention (1) Especially [invention field]: The present invention relates to a method for manufacturing a semiconductor package and its structure. 'A heat sink is provided, and the chip is in a flip-chip type (F1 lp Chip). Method for manufacturing a flip-chip semiconductor package on the bottom of a substrate connected to the same side of a solder ball (Solder Bal 1) and its structure. [Background of the Invention]: With the increasing integration of wafers, the requirements for electrical quality and heat dissipation efficiency of semiconductor packages have become higher and higher. In order to meet the development trend of high functionality and high processing speed of electronic products, the industry has tried to place multiple semiconductor wafers in the same package structure and developed a polycrystalline semiconductor package. A conventional multi-chip semiconductor package, as shown in FIG. 4, first prepares a substrate 2 10, which has an upper surface 2a and a relatively lower surface 210b, and uses Flip chips or wire bonding are used to place two or more wafers 211 212 on the upper surface 210 a of the substrate 21 and the substrate 21. The following table shows how many balls 2 1 3, so that the packaging structure of the completed molding technology (Mooing) can be electrically connected to external devices (such as printed circuit boards) through the solder balls 2 丨 3. .
然而’此種封裝結構承藝 夕 A宜此主二u , 稱水戟之多數晶片，若分散接置在 同一暴板表面上，往往合佔田、κ丄# L ft «Mt- ^ ^ · .TF, ^ a a佔用過大基板面積而不利於產品 被型化而各晶片若採mi· (』hipHowever, this kind of packaging structure Cheng Yi Xi A should be the main two u, said that most wafers of water halberd, if scattered on the same surface of the storm board, often share Zhantian, κ 丄 # L ft «Mt- ^ ^ · .TF, ^ aa occupies an excessively large substrate area and is not conducive to the product being modeled.
Stacked)封裝，則又合佬得占一 〜 專利第5, 801，0 7 2號案進一步揭# 絲收 疋 ^ 芡揭路一種將至少一第一晶片Stacked) package, then the co-owners have to take up one ~ Patent No. 5, 801, 0 7 2 case further unveiled # 丝 收 疋 ^ 芡 Unveil a kind of at least one first chip
16605.ptd 第7頁 1234256 五、發明說明（2) 及第二晶片分別覆晶銲接於基板之上下表面，以使該第二 晶片在不影響回銲（Re f丨〇w)的情形下，與銲球同側安置 於基板之下表面上。 如第5圖所示，此一半導體封裝結構3係於一基板3 i 〇 之上下表面3 1 0 a，3 1 0 b上，各以覆晶技術（F 1 i p Ch i p Technology)銲接至少一第一晶片31 i及第二晶片312，經 過底部填膠作業（Under f i 1 1)後，再以第一蓋件350 (First Lid)及第二蓋件351 ( Second Lid)取代封膠技 術封閉晶片，復於該基板3 1 0之下表面3 1 Ob上植設多數銲 塊3 1 3，以使該第二蓋件3 5 1之高度明顯低於該等銲塊3 1 3 咼度而不致妨害回銲作業（Reflowing Process)之實 施。 惟上述結構中，該第二晶片係與銲塊同側安置於相同 基板表面，因此，基板表面無法再容散熱結構（如内嵌式 散熱件（Embedded Heat Sink)或外加式散熱件 (External Heat Sink)接置而往往令第二晶片運作產生 的熱量難以逸散，甚至損及產品性能；是故，美國專利第 5, 798, 56 7號案於是另外提出一種藉由導電膠 (Conductive Paste)將第二晶片非作用表面（即未佈設 銲墊之晶片表面）黏接到印刷電路板上之結構。 如第6圖所示，此種型態之半導體封裝件4係利用基板 底部覆晶方式接置晶片4 1 2，使得該晶片4 1 2之非作用表面 4 1 2b係朝向供該半導體封裝件4銲接之印刷電路板43，而 後，以一導電膠42 ( Conduct ive Paste)黏接該晶片41216605.ptd Page 7 1234256 5. Description of the invention (2) and the second wafer are flip-chip soldered to the upper and lower surfaces of the substrate, so that the second wafer does not affect the reflow (Re f 丨 〇w), The same side as the solder ball is disposed on the lower surface of the substrate. As shown in FIG. 5, this semiconductor package structure 3 is mounted on a substrate 3 i 〇 on the upper and lower surfaces 3 1 0 a and 3 1 0 b, each of which is soldered by F 1 ip Ch ip Technology. After the first wafer 31 i and the second wafer 312 are under-filled (Under fi 1 1), the first cover 350 (First Lid) and the second cover 351 (Second Lid) are used to replace the sealing technology. The wafer is placed on the lower surface 3 1 Ob of the substrate 3 1 with a plurality of solder bumps 3 1 3 so that the height of the second cover 3 5 1 is significantly lower than the solder bumps 3 1 3. Does not hinder the implementation of the reflowing process. However, in the above structure, the second chip is disposed on the same substrate surface as the solder bump on the same side. Therefore, the substrate surface can no longer accommodate a heat dissipation structure (such as an embedded heat sink or an external heat sink). Sink) connection often makes it difficult to dissipate the heat generated by the operation of the second chip and even damage the product performance; therefore, US Patent No. 5,798, 56 7 therefore proposes another method of conducting paste (Conductive Paste) The structure in which the non-active surface of the second wafer (that is, the surface of the wafer without a bonding pad) is adhered to the printed circuit board. As shown in FIG. 6, this type of semiconductor package 4 uses a chip-on-chip method The wafer 4 1 2 is connected so that the non-active surface 4 1 2b of the wafer 4 1 2 faces the printed circuit board 43 for soldering the semiconductor package 4, and then the conductive adhesive 42 is used to adhere the Chip 412
16605.ptd 第8頁 1234256 五、發明說明⑶ — ~_ 曰曰 非作用表Φ 412b至印刷電路板43上，俾藉該導電膠 片41 2產生〃的熱能傳遞至印刷電路板43。但由於該導、E 42之熱阻係數較高，無法有效改善晶片熱積存問題 夕 者’此種封裝製法需要事先在印刷電路板43上 42以及助焊劑（Flux)(未圖示），待半導體 ^膠 導電膠42黏接至定位後’復用回銲方式將該半 > 4銲固到印刷電路板43上，而導致製程複雜度增：政件 i本ί:製法亦需要另外增加點膠等製程，亦會提高額外 【發明概述】： ^本發明之主要目的即在提供一種可有效解決與銲球 側安置之半導體晶片之散熱問題，俾使晶片運作產生之 量能以最短路徑傳送至印刷電路板之基板底 ^ 體封裝件製法及其結構。 是阳式+導 〃本發明之另一目的在於提供一種不需增加表面黏接技 術（Surface Mounting Technology， SMT)額外製程，運 用現有製程技術即可提高封裝產品散熱效率之基板 晶式半導體封裝件製法及其結構。 -σ i 為達成上揭及其他目的，本發明之基板底晶 導體封裝件係包含一基板，f亥基板具有至少一上表是：J士 第一晶片及第二晶片，該第一晶片係接置 於暴板之上表面上，並以覆晶或銲線連接（W丨re16605.ptd Page 8 1234256 V. INTRODUCTION OF THE INVENTION (3) — — — — Non-active table Φ 412b to the printed circuit board 43. The thermal energy generated by the conductive film 41 2 is transferred to the printed circuit board 43. However, due to the high thermal resistance coefficient of this guide and E 42, it is not effective to improve the problem of thermal accumulation of the wafer. 'This packaging method requires the 42 and Flux (not shown) on the printed circuit board 43 in advance. The semiconductor glue is bonded to the conductive glue 42 after the positioning. The multiplexing reflow method is used to solder the half > 4 to the printed circuit board 43, which leads to an increase in the complexity of the process. Processes such as dispensing will also increase the extra [Invention Summary]: ^ The main purpose of the present invention is to provide a heat dissipation problem that can effectively solve the problem of semiconductor wafers placed on the solder ball side, so that the amount of wafer operation can be achieved in the shortest path Manufacturing method and structure of substrate base body package transferred to printed circuit board. It is a male type + a conductive type. Another object of the present invention is to provide a substrate crystal semiconductor package that does not require additional surface mounting technology (SMT) additional processes and can improve the heat dissipation efficiency of packaging products by using existing process technologies. Method and structure. -σ i In order to achieve the disclosure and other purposes, the substrate bottom crystal conductor package of the present invention includes a substrate, and the f Hai substrate has at least one of the above tables: J first wafer and second wafer, the first wafer system Connected to the upper surface of the storm board, and connected with flip-chip or welding wire (W 丨 re
Bonded)等方式電性連接至基板，而該第二晶片則安置於 基板之下表面；以藉由覆晶技術提供該第二晶片與基板電Bonded) and other methods to electrically connect to the substrate, and the second chip is placed on the lower surface of the substrate;
16605.ptd 第9頁 1234256 五、發明說明（4) 性連結；一散熱片，其具有一第一表面及一相對之第二表 面，該散熱片係藉一塗佈於該散熱片第一表面上之導熱膠 黏接到該第二晶片之非作用表面上，且散熱片之第二表面 上預佈有一銲錫層；以及多數銲球’係與該第二晶片同側 安置於基板之下表面，俾於銲接時與該散熱片一併回銲至 外部印刷電路板上。 由於該散熱片一表面上預鍍妥一錫層，因此當銲球回 銲到印刷電路板上時，該散熱片可以一併銲接到該印刷電 路板相對應之散熱墊，再透過該散熱墊連接之貫孔將晶片 熱量傳遞至印刷電路板内部的接地層（Ground Layer)。 藉以釋散第二晶片在運作中產生之熱量而克服傳統基板底 部覆晶晶片（即第二晶片）無法充分散熱的問題。 而上述基板底部覆晶式半導體封裝件其製法則包含以 下步驟：首先，預備一基板，該基板具有一上表面及一相 對之下表面，以供至少一晶片覆晶連接於基板下表面上， 而與植接於基板下表面上之多數銲球同側安置；接著，製 妥一散熱片，該散熱片具有一第一表面及一相對之第二表 面，該第二表面上預形成有一銲錫層，俾與一具有至少一 散熱墊及多數銲球墊之印刷電路板銲接；之後，佈覆一導 熱膠至該散熱片第一表面，並將該散熱片黏接至基板底部 覆晶晶片之非作用表面上，以使基板底面與銲球底面之間 的間隔高度大於「晶片-導電膠-散熱片」之厚度總合；然 後，銲連各銲球至該印刷電路板，使各銲球回銲時能一併 透過該銲錫層將散熱片銲固到該印刷電路板上，因此該基16605.ptd Page 9 1234256 V. Description of the invention (4) Sexual connection; a heat sink having a first surface and an opposite second surface, the heat sink is coated on the first surface of the heat sink by one The thermal conductive adhesive is adhered to the non-active surface of the second chip, and a solder layer is pre-arranged on the second surface of the heat sink; and most of the solder balls are disposed on the same side of the second chip on the lower surface of the substrate. , When soldering back to the external printed circuit board together with the heat sink. Because a tin layer is pre-plated on one surface of the heat sink, when the solder ball is re-soldered to the printed circuit board, the heat sink can be soldered to the corresponding heat sink pad of the printed circuit board, and then pass through the heat sink pad. The connecting through hole transfers the heat of the chip to the ground layer inside the printed circuit board. By dissipating the heat generated during the operation of the second wafer, the problem that the chip-on-chip (ie, the second wafer) at the bottom of the conventional substrate cannot sufficiently dissipate heat is overcome. The method for manufacturing the flip-chip semiconductor package at the bottom of the substrate includes the following steps: first, preparing a substrate having an upper surface and a relatively lower surface for at least one wafer flip-chip to be connected to the lower surface of the substrate; It is placed on the same side as most of the solder balls planted on the lower surface of the substrate; then, a heat sink is prepared, the heat sink has a first surface and an opposite second surface, and a solder is pre-formed on the second surface. Layer, and soldered to a printed circuit board having at least one heat sink pad and a plurality of solder ball pads; then, a thermally conductive adhesive was applied to the first surface of the heat sink, and the heat sink was bonded to the chip-on-chip wafer at the bottom of the substrate. On the non-active surface so that the height of the gap between the bottom surface of the substrate and the bottom surface of the solder ball is greater than the thickness of the "wafer-conductive adhesive-radiating fin"; then, soldering each solder ball to the printed circuit board so that each solder ball During reflow, the heat sink can be soldered to the printed circuit board through the solder layer together.
16605.ptd 第10頁 1234256 五 、發明說明 (5) 板 底 部 覆 晶 晶 片 產生 之熱量可透過該導熱膠、散熱片及銲 锡 層 傳 遞 至 印 刷 電路 板内部之接地層（Ground Layer)。 [ 發 明 詳 細 說 明 ]·· 以 下 即 藉 由 第1 A至1 E圖詳細說明本發明半導體封裝件 之 整 體 製 作 流 程 ，並 以第2圖顯示此基板底部覆晶式半導 體 封 裝 件 製 法 應 用在 多晶片模組件（M u 11 i - C h i ρ Μ 〇 d u 1 e， MCM) 之較佳實施例c 如 第 1 A圖 所 示， 先備妥一散熱片1 〇，該散熱片1 0係由 銅 Λ 銅 合 金 及 其 他導 熱性良好之金屬材質製成，其具有一 第 一 表 面 1 0 0及- -相對之第二表面1 0 1，並於該散熱片1 〇之 第 二 表 面 1 0 1上預鍍- -錫層1 0 2或其他如錫船合金等熱熔融 銲 料 Ο 如 第 1B圖 所 示， 另預備一封裝體1 1，該封裝體11係一 基 板 底 部 覆 晶 式 結構 ’其包含有一基板11 0，該基板11 0具 有 一 上 表 面 1 1 L 0 a及一 下表面1 1 0 b以分別電性連接至少一第 一 晶 片 1 ] L 1及第二 二晶片11 2，惟該第一晶片11 i得以銲接連 接 ( Wi Lre Bonded)或覆晶（Flip Chip)技術等方式電性 連 接 至 基 板 1 ] L 0上表面1 1 0 a，而該第二晶片11 2具有一作用 表 面 1 ] L2a ( 即 佈 設有 多數電子電路及電子元件之晶片表 面 ) 及 一 相 對 之 非作 用表面112b，且以其作用表面H2a朝 上 之 方 法 將 該 第 二晶 片1 1 2女置於基板1 1 〇下表面1 1 〇 b上。 而 後 ， 塗 佈 導 熱膠 1 2至該散熱片1 0第一表面1 〇 〇上，用 以 接 合 該 散 熱 片 1 0及 第二晶片1 1 2。並且限定該基板11 〇下 表 面 1 ] LOb與 銲 球 11 3底面間之間隔距離需明顯大於第二晶16605.ptd Page 10 1234256 V. Description of the invention (5) The heat generated by the chip on the bottom of the board can be transferred to the ground layer inside the printed circuit board through the thermal conductive glue, heat sink and solder layer. [Detailed description of the invention] The following is a detailed description of the overall manufacturing process of the semiconductor package of the present invention through the first 1 to 1 E diagrams, and the second figure shows the method of manufacturing the chip-on-chip semiconductor package on the bottom of the substrate applied to multi-chip A preferred embodiment of a mold assembly (M u 11 i-C hi ρ Μ DU 1 e, MCM) c As shown in FIG. 1A, a heat sink 10 is prepared first, and the heat sink 10 is It is made of copper Λ copper alloy and other metal materials with good thermal conductivity. It has a first surface 1 0 0 and a second surface 1 0 1 opposite to the second surface 1 0 1 of the heat sink 1 0. Pre-plating-tin layer 102 or other hot-melt solders such as tin boat alloys, etc. As shown in Fig. 1B, another package body 1 1 is prepared, and the package body 11 is a crystal structure on the bottom of a substrate. It comprises a substrate 110, which has an upper surface 1 1 L 0 a and a lower surface 1 1 0 b to electrically connect at least one first chip 1] L 1 and the second two chips 11 2 respectively, but the First wafer 11 i is soldered (Wi Lre Bonded) or flip chip (Flip Chip) technology and other methods to electrically connect to the substrate 1] L 0 upper surface 1 1 0 a, and the second chip 11 2 has an active surface 1] L2a The surface of the wafer of the electronic circuit and electronic component) and an opposite non-active surface 112b, and the second wafer 1 1 2 is placed on the lower surface 1 1 〇b of the substrate 1 2 with the active surface H2a facing upward. . Then, a thermal conductive adhesive 12 is applied to the first surface 100 of the heat sink 10 to bond the heat sink 10 and the second wafer 112. And the bottom surface of the substrate 11 is limited. The distance between the LOb and the bottom surface of the solder ball 11 3 needs to be significantly larger than that of the second crystal.
16605.ptd 第11頁 1234256 五、發明說明（6) 片1 1 2、導熱膠1 2及散熱片1 0三者高度之總和。由於高溫 回銲（R e f 1 〇 w)作業中，錫船合金材料製成之銲球1 1 3受 熱潰縮（Col lapse)，故可藉由銲球潰縮時產生的高度下 降現象，將該散熱片1 0銲接至印刷電路板（未圖示）上； 若以本實施例視之，該導熱膠1 2、散熱片1 0、預鍍錫層 1 0 2及晶片11 2之厚度總和係佔銲球1 1 3高度的7 〇 %至9 0 %者 為佳（以8 0 %較佳）。 再如第1 C圖所示，另備妥至少一印刷電路板1 3，該印 刷電路板1 3係一多層印刷電路板（M u 11 i - 1 a y e r P r i n t e d Circuit Board)，如以四層板為例，印刷電路板内部一 般設有以銅镇形成之接地層1 3 0 ( G r 〇 u n d L a y e r )，該接 地層1 3 0藉由多數貫孔1 3 1連通到各接地墊（未圖示），此 等倶為習知製程，故不重複贅述。惟該印刷電路板1 3與第 二晶片1 1 2相對之表面上係分別預設有至少一與該散熱片 相對應之散熱墊1 3 2 ( Th e rma 1 Pad)以及複數個與該銲球 1 1 3相對應之銲球墊1 3 3，且該散熱墊i 3 2亦如其他接地墊 (未圖示）係藉由多數貫孔1 3 1連通到該接地層1 3 〇上。待 一助焊劑1 4 ( F 1 u X)塗佈於該散熱墊1 3 2及銲球墊1 3 3後， 即可進行回銲製程（Reflow Process)。 如第1 D圖所示，將上述封裝體丨丨對位接置到該印刷電 路板1 3上’以使該散熱片1 〇及多數銲球n 3各對應於該散 熱整1 3 2及鮮球塾1 3 3，若再以第3圖更進一步顯示回銲作 業前後’基板與鮮球底面間距與「第二晶片—導熱膠_散熱 片」厚度總和之間的變化。如第3圖可知，未實施回銲作16605.ptd Page 11 1234256 V. Description of the invention (6) The sum of the height of the sheet 1 1 2, the thermal conductive adhesive 12 and the heat sink 10. Since the solder ball 1 1 3 made of tin boat alloy material collapses under heat during the high temperature reflow (Ref 1 0w) operation, the height drop phenomenon caused when the solder ball collapses can be used to reduce the height of the solder ball. The heat sink 10 is soldered to a printed circuit board (not shown); if viewed in this embodiment, the total thickness of the thermally conductive adhesive 12, the heat sink 10, the pre-tinned layer 102, and the wafer 11 2 It is preferably 70% to 90% of the height of the solder ball 1 1 3 (preferably 80%). As shown in FIG. 1C, at least one printed circuit board 13 is prepared. The printed circuit board 13 is a multilayer printed circuit board (Mu 11 i-1 ayer Printed Circuit Board). As an example, a printed circuit board is generally provided with a ground layer 1 3 0 (Grundund Layer) formed by a copper town. The ground layer 1 3 0 is connected to each ground pad through a plurality of through holes 1 3 1 (Not shown), since these are known processes, they are not repeated here. However, the printed circuit board 13 and the second chip 1 12 are respectively provided with at least one thermal pad 1 3 2 (Th e rma 1 Pad) corresponding to the heat sink, and a plurality of solder pads corresponding to the solder pad. The solder ball pad 1 3 3 corresponding to the ball 1 1 3, and the heat dissipation pad i 3 2 is also connected to the ground layer 1 3 0 through a plurality of through holes 1 3 1 like other ground pads (not shown). After a flux 1 4 (F 1 u X) is applied to the heat dissipation pad 13 2 and the solder ball pad 13 3, a reflow process can be performed. As shown in FIG. 1D, the above-mentioned package 丨 丨 is placed on the printed circuit board 13 in a position so that the heat sink 10 and the plurality of solder balls n 3 each correspond to the heat sink 1 2 2 and Fresh ball 塾 1 3 3, if you use Figure 3 to further show the change between the substrate and the bottom surface of the fresh ball before and after the change between the thickness of the "second chip-thermal adhesive_ heat sink" thickness change. As can be seen in Figure 3, no reflow operation has been performed.
1234256 五、發明說明（7) 業前，第二晶片1 1 2、導熱膠1 2、散熱片1 0及銲錫層1 〇 2各 元件之整體厚度總和h係小於該銲球1 1 3高度Η—預設距離 (如前所述，此等元件之整體厚度總和佔銲球高度之7 〇 % 至9 0 %)，然而，回銲進行時，該銲球1 1 3受熱潰縮 (Cο 1 1 ap s e)而導致基板1 1 〇與銲球1 1 3底面的間隔距離降 低成H’，且回銲後的銲球1 1 3高度H’乃不大於第二晶片 1 1 2、導熱膠1 2、散熱片1 〇及銲錫層1 0 2之整體厚度h。 再而，該散熱片1 0可與預佈有助焊劑1 4之散熱墊1 3 2 接觸’並藉由該散熱片10第二表面1〇 1上預佈之銲錫1 〇 2將 該散熱片1 0銲固於印刷電路板1 3之散熱墊1 3 2上。因此， 本發明之半導體封裝件無須增加額外步驟，在銲球回鋒過 程中即可一併將該散熱片銲接到印刷電路板上。 如第1 E圖所示，回銲作業完成後，該第二晶片u 2可 透過導熱膠1 2、散熱片1 〇及銲錫層1 〇 2連接至印刷電路板 1 3之散熱墊1 32上，因此，第二晶片i丨2運作時產生的熱能 將能透過該導熱膠1 2、散熱片1 〇、散熱墊1 3 2、貫孔i 3 = 傳導到印刷電路板1 3内部之接地層1 3 〇 (當作散熱層）， 以有效改善基板底部覆晶晶片的熱積存問題。 綜上所述，經由前述製程可製得一基板底部覆晶式半 導體封震件，如第2圖所示，此半導體封裝件1包含有一基 板11 〇，該基板1 1 〇具有一上表面i丨〇a及一相對之下表面土 11 〇b ’至。少一第一晶片111及第二晶片11 2，該第一晶片 π 1係以單一晶片或疊晶等型態接置於基板11 0上表面1 i 上’並以覆晶或金線銲接等方式與該基板π 〇形成電性連·1234256 V. Description of the invention (7) Before the industry, the second wafer 1 1 2, the thermally conductive adhesive 1, 2, the heat sink 10, and the solder layer 1 〇 The total thickness of each component h is less than the height of the solder ball 1 1 3 Η -A preset distance (as mentioned above, the total thickness of these components accounts for 70% to 90% of the height of the solder ball), however, the solder ball 1 1 3 is thermally collapsed during reflow (Cο 1 1 ap se) and the distance between the bottom surface of the substrate 1 1 〇 and the solder ball 1 1 3 is reduced to H ′, and the height H ′ of the solder ball 1 1 3 after reflow is not greater than the second wafer 1 1 2 1 2. The overall thickness h of the heat sink 10 and the solder layer 102. Furthermore, the heat sink 10 may be in contact with the heat sink 1 3 2 pre-mounted with the flux 14 and the heat sink 10 may be pre-arranged by the solder 1 0 2 on the second surface 10 of the heat sink 10. 10 is soldered on the heat sink 1 3 2 of the printed circuit board 13. Therefore, the semiconductor package of the present invention does not need to add extra steps, and the heat sink can be soldered to the printed circuit board during the process of solder ball return. As shown in Figure 1E, after the reflow operation is completed, the second chip u 2 can be connected to the heat dissipation pad 1 32 of the printed circuit board 13 through the thermal conductive adhesive 1 2, the heat sink 1 〇 and the solder layer 1 〇 2. Therefore, the thermal energy generated during the operation of the second chip i 丨 2 will be able to pass through the thermally conductive adhesive 1 2, the heat sink 1 〇, the heat sink 1 3 2, and the through hole i 3 = conductive to the ground layer inside the printed circuit board 1 3 13 (as a heat dissipation layer) to effectively improve the heat accumulation problem of the flip-chip wafer on the bottom of the substrate. In summary, a chip-on-chip semiconductor vibration-isolating member at the bottom of the substrate can be obtained through the foregoing process. As shown in FIG. 2, the semiconductor package 1 includes a substrate 11 〇, which has an upper surface i.丨 〇a and a relatively lower surface soil 110 ′ to. The first wafer 111 and the second wafer 11 2 are less. The first wafer π 1 is connected to the upper surface 1 i of the substrate 11 0 as a single wafer or a stacked wafer, and is bonded by flip chip or gold wire. Form an electrical connection with the substrate π 〇
16605.ptd 第13頁 1234256 五、發明說明（8) 接關係，而該第二晶片1 1 2則以覆晶方法銲接於銲球11 3相 同側，俾使該第二晶片1 1 2之非作用表面1 1 2b朝向提供封 裝件外接之印刷電路板1 3表面；以及一散熱片1 0，其具有 一第一表面1 0 0及一第二表面101，且該散熱片1 3係藉由一 塗佈於該第一表面1 0 0上之導熱膠1 2黏接至該第二晶片1 1 2 之非作用表面1 1 2 b上，該散熱片1 0第二表面1 0 1則預鍍有 一錫層1 0 2，俾於銲球1 1 3回銲時一併將該散熱片1 0銲接至 印刷電路板1 3上。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之實質技術内容範圍，本發明之實質技術内容係 廣義地定義於下述之申請專利範圍中，任何他人所完成之 技術實體或方法，若是與下述之申請專利範圍所定義者係 完全相同，或是同一等效之變更，均將被視為涵蓋於此申 請專利範圍之中。16605.ptd Page 13 1234256 V. Explanation of the invention (8) The second wafer 1 1 2 is soldered to the same side of the solder ball 11 3 by the flip-chip method, so that the second wafer 1 1 2 is not The active surface 1 1 2b faces the surface of the printed circuit board 13 which provides the external connection of the package; and a heat sink 10, which has a first surface 100 and a second surface 101, and the heat sink 13 is formed by A thermally conductive adhesive 1 2 coated on the first surface 100 is adhered to the non-active surface 1 1 2 b of the second wafer 1 1 2, and the heat sink 1 0 and the second surface 1 0 1 are A tin layer 10 2 is plated, the heat sink 10 is soldered to the printed circuit board 13 when the solder ball 1 13 is re-soldered. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the essential technical content of the present invention. The essential technical content of the present invention is broadly defined in the scope of the patent application described below. Any technical entity or method that is completely the same as defined in the patent application scope described below, or the same equivalent change, will be considered to be covered by this patent application scope.
16605.ptd 第14頁 1234256 圖式簡單說明 【圖式簡單說明】： 第1 A至1 E圖係顯示本發明基板底部覆晶式半導體封裝 件製法之整體流程示意圖； 第2圖係顯示本發明之基板底部覆晶式半導體封裝件 之剖面示意圖； 第3圖係顯示本發明半導體封裝件中，該基板底部覆 晶晶片進行運作時其晶片熱量傳遞之路徑示意圖； 第 4圖係顯示 傳 統 多 晶 片 圖， 第 5圖係顯示 美 國 專 利 第 件之剖 面示意圖； 以及 第 6圖係顯示 美 國 專 利 第 件之剖 面不意圖。 【元件 符號說明】 1,3,4 半 導 體 封 10 散 熱 片 100 散 熱 片 第 101 散 熱 片 第 102 銲 錫 層 11 封 裝 體 110, 210, 310 基 板 110a， 210a，31 0a 基 板 上 表 110b， 210b， 310b 基 板 下 表 111,211,311 第 一 晶 片 半導體封裝件之剖面示意 5，8 0 1，0 7 2號案之半導體封裝 5，7 9 8，5 6 7號案之半導體封裝 裝件 一表面 二表面 面 面16605.ptd Page 14 1234256 Brief description of the drawings [Simplified illustration of the drawings]: Figures 1 A to 1 E are schematic diagrams showing the overall flow of the method of manufacturing a flip-chip semiconductor package at the bottom of the substrate of the present invention; Figure 2 shows the present invention A schematic cross-sectional view of a flip-chip semiconductor package at the bottom of a substrate; FIG. 3 is a schematic diagram showing a path of heat transfer of a wafer when the flip-chip wafer at the bottom of the substrate is operating in the semiconductor package of the present invention; FIG. 5 is a schematic cross-sectional view of the first U.S. patent; and FIG. 6 is a schematic view showing the cross-section of the U.S. patent. [Element symbol description] 1, 3, 4 semiconductor package 10 heat sink 100 heat sink 101 heat sink 102 solder layer 11 package 110, 210, 310 substrate 110a, 210a, 31 0a substrate 110b, 210b, 310b substrate The following table shows the cross-section of the first chip semiconductor package 111,211,311 The semiconductor package No. 5,8 0 1,0 7 2 The semiconductor package No. 5,7 9 8,5 6 7 The first surface and the second surface
!6605.ptd 第15頁 1234256! 6605.ptd Page 15 1234256
16605.ptd 圖式簡單說明 112, 212, 312, 412 弟二晶 片 112a 晶片作 用表 面 112b,412b 晶片非 作用 表面 113,213,313 銲球 12 導熱膠 13, 43 印刷電路板 130 接地層 131 貫孔 132 散熱墊 133 鮮球塾 14 助焊劑 350 第一蓋 件 351 第二蓋 件 42 導電膠 第16頁16605.ptd Brief description of the diagram 112, 212, 312, 412 The second wafer 112a Wafer active surface 112b, 412b Wafer non-active surface 113, 213, 313 Solder ball 12 Thermal conductive glue 13, 43 Printed circuit board 130 Ground layer 131 Through hole 132 Thermal pad 133 Fresh ball 塾 14 Flux 350 First cover 351 Second cover 42 Conductive glue Page 16
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW091132643A TWI234256B (en) | 2002-11-06 | 2002-11-06 | Process for fabricating semiconductor package having heat spreader and the same thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW091132643A TWI234256B (en) | 2002-11-06 | 2002-11-06 | Process for fabricating semiconductor package having heat spreader and the same thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200408088A TW200408088A (en) | 2004-05-16 |
| TWI234256B true TWI234256B (en) | 2005-06-11 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW091132643A TWI234256B (en) | 2002-11-06 | 2002-11-06 | Process for fabricating semiconductor package having heat spreader and the same thereof |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI234256B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI406388B (en) * | 2008-12-02 | 2013-08-21 | Innolux Corp | Light source array substrate, backlight module and liquid crystal display |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI596718B (en) * | 2015-02-13 | 2017-08-21 | 台灣東電化股份有限公司 | A circuit module package structure and packaging method thereof |
-
2002
- 2002-11-06 TW TW091132643A patent/TWI234256B/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI406388B (en) * | 2008-12-02 | 2013-08-21 | Innolux Corp | Light source array substrate, backlight module and liquid crystal display |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200408088A (en) | 2004-05-16 |
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| MM4A | Annulment or lapse of patent due to non-payment of fees |