TW200408088A - Process for fabricating semiconductor package having heat spreader and the same thereof - Google Patents
Process for fabricating semiconductor package having heat spreader and the same thereof Download PDFInfo
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- TW200408088A TW200408088A TW091132643A TW91132643A TW200408088A TW 200408088 A TW200408088 A TW 200408088A TW 091132643 A TW091132643 A TW 091132643A TW 91132643 A TW91132643 A TW 91132643A TW 200408088 A TW200408088 A TW 200408088A
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- heat sink
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
200408088 五、發明說明（1) 【發明領域】： 本發明係關於一種半導體封裝件製法及其結構，尤指 一種具有散熱件（Heat Sink)，並以覆晶型態（Fl ip C h i p)將晶片接置於銲球（S〇1 d e r B a 1 1)同側之基板底 部覆晶式半導體封裝件製法及其結構。 【發明背景】： 隨著晶片集積度（Integration)不斷提昇，半導體 封裝件對於電性品質及散熱效率的要求亦愈來愈高。為滿 足電子產品高功能性及高處理速度之發展趨勢，業界嘗試 將多片半導體晶片載置於同一封裝結構内，而開發出多晶 片半導體封裝件。 傳統型態的多晶片半導體封裝件，如第4圖所示，係 先備妥一基板2 1 0，該基板2 1 0具有一上表面210 a及一相對 之下表面210b，並運用覆晶（Flip Chip)或銲線電性連 接（Wire Bonded)等方式將兩片以上晶片211，21 2安置於 基板2 1 0之上表面2 1 0 a上，該基板2 1 0之下表面2 1 0 b上則佈 設有多數銲球2 1 3，以使完成模壓技術（Μ ο 1 d i n g)之封裝 結構能藉由該等銲球2 1 3電性連接至外部裝置（如印刷電 路板）上。 然而，此種封裝結構承載之多數晶片，若分散接置在 同一基板表面上，往往會佔用過大基板面積而不利於產品 微型化發展；而各晶片若採垂直疊晶技術（Ch i p Stacked)封裝，則又會使得成品高度增加。是以，美國 專利第5，8 0 1，0 7 2號案進一步揭露一種將至少一第一晶片200408088 V. Description of the invention (1) [Field of the invention] The present invention relates to a method for manufacturing a semiconductor package and a structure thereof, particularly a heat sink (Heat Sink), and a flip-chip type (Fl ip C hip) Method for manufacturing a chip-on-chip semiconductor package on the bottom of a substrate on the same side of a solder ball (S〇1 der B a 1 1) and its structure. [Background of the Invention]: With the increasing integration of wafers, the requirements for electrical quality and heat dissipation efficiency of semiconductor packages have become higher and higher. In order to meet the development trend of high functionality and high processing speed of electronic products, the industry has tried to place multiple semiconductor wafers in the same package structure and developed a polycrystalline semiconductor package. A conventional multi-chip semiconductor package, as shown in FIG. 4, first prepares a substrate 2 0, which has an upper surface 210a and a relatively lower surface 210b, and uses a flip chip (Flip Chip) or wire bonding (Wire Bonded) and other methods to place two or more wafers 211, 21 2 on the substrate 2 1 0 above the surface 2 1 0 a, the substrate 2 1 0 below the surface 2 1 A plurality of solder balls 2 1 3 are arranged on 0 b, so that the packaging structure of the completed molding technology (Μ ο 1 ding) can be electrically connected to an external device (such as a printed circuit board) through the solder balls 2 1 3 . However, if most of the wafers carried by this packaging structure are placed on the same substrate surface, they will often occupy an excessively large substrate area, which is not conducive to the miniaturization of the product. If each wafer is packaged using the vertical stack technology (Ch ip stacked) , Then it will increase the height of the finished product. Therefore, U.S. Patent No. 5,80,0,72 further discloses a method for incorporating at least one first chip
16605.ptd 第7頁 200408088 ’五、發明說明（2) 及第一 μ片为別覆晶銲接於基板之上下表面，以使該第二 a曰片在不影響回銲（r e f 1 〇 w)的情形下，與銲球同側安置 於基板之下表面上。 如第5圖所示，此一半導體封裝結構3係於一基板3工〇 :之上下表面3 1 0 a，3 1 0 b上，各以覆晶技術（F 1 i p Ch 1 P Technology)銲接至少一第一晶片31工及第二晶片312，經 過底部填膠作業（Underf i 1 1)後，再以第一蓋件350 (First Lid)及第二蓋件351( Second Lid)取代封膠技 術封閉晶片，復於該基板3丨〇之下表面3丨〇 b上植設多數辉 • 3 1 3 ’以使該第二蓋件3 5 1之高度明顯低於該等銲塊3丄3 咼度而不致妨害回銲作業（Refl〇wing pr〇cess)之實 施。 、 惟上述結構中，該第二晶片係與銲塊同側安置於相同 基板表面，因此，基板表面無法再容散熱結構（如内丧式 散熱件（Embedded Heat Sink)或外加式散熱件 (External Heat Sink)接置而往往令第二晶片運作產生 的熱量難以逸散，甚至損及產品性能；是故，美國專利第 5, 798, 56 7號案於是另外提出一種藉由導電膠 (Conductive Paste)將第二晶片非作用表面（即未 ,, x 佈設 之晶片表面）黏接到印刷電路板上之結構。16605.ptd Page 7, 200408088 'Fifth, the description of the invention (2) and the first μ chip are soldered to the upper and lower surfaces of the substrate so that the second a chip does not affect reflow (ref 1 〇w) In the case, the same side as the solder ball is placed on the lower surface of the substrate. As shown in FIG. 5, this semiconductor package structure 3 is formed on a substrate 3. The upper and lower surfaces 3 1 0 a and 3 1 0 b are each soldered by flip-chip technology (F 1 ip Ch 1 P Technology). At least one of the first wafer 31 and the second wafer 312, after the underfill operation (Underf i 1 1), then the first cover 350 (First Lid) and the second cover 351 (Second Lid) replace the sealant. The technology closes the wafer, and a plurality of radiances • 3 1 3 'are planted on the lower surface 3 丨 〇b of the substrate 3 丨 〇 so that the height of the second cover 3 51 is significantly lower than the solder bumps 3 丄 3 The degree is not to hinder the implementation of the reflow operation (ReflOwing prOcess). However, in the above structure, the second chip is placed on the same substrate surface as the solder bumps on the same side, so the substrate surface can no longer accommodate heat dissipation structures (such as Embedded Heat Sink or External Heat Sink). Heat Sink) connection often makes it difficult to dissipate the heat generated by the operation of the second chip and even damage the product performance; therefore, US Patent No. 5,798, 56 7 therefore proposes a new method using conductive paste (Conductive Paste). ) A structure in which the non-active surface of the second wafer (ie, the surface of the wafer laid by x, x) is bonded to the printed circuit board.
如第6圖所示，此種型態之半導體封裝件4係利用货L 板 底部覆晶方式接置晶片4 1 2，使得該晶片4 1 2之非作用夺 _4 1 2 b係朝向供該半導體封裝件4銲接之印刷電路板4 3， 後，以一導電膠42( Conductive Paste)黏接該晶片4As shown in FIG. 6, this type of semiconductor package 4 is connected to the wafer 4 1 2 by flip-chip method on the bottom of the L plate, so that the non-action 4 4 2 2 of the wafer 4 1 2 is oriented toward the supply. The semiconductor package 4 is soldered to a printed circuit board 4 3, and then the chip 4 is bonded with a conductive paste 42 (Conductive Paste).
16605.ptd 第8頁 200408088 五、發明說明（3) 非作用表面4 1 2 b至印刷電路板4 3上，俾藉該導電膠4 2將晶 片4 1 2產生的熱能傳遞至印刷電路板4 3。但由於該導電·膠 4 2之熱阻係數較南^無法有效改善晶片熱積存問題，再 者，此種封裝製法需要事先在印刷電路板4 3上塗佈導電膠 4 2以及助焊劑（F 1 ux)(未圖示），待半導體封裝件4與 導電膠4 2黏接至定位後，復用回銲方式將該半導體封裝件 4銲固到印刷電路板4 3上，而導致製程複雜度增加；況 且，此一製法亦需要另外增加點膠等製程，亦會提高額外 成本支出。 【發明概述】： 本發明之主要目的即在提供一種可有效解決與銲球同 側安置之半導體晶片之散熱問題，俾使晶片運作產生之熱 量能以最短路徑傳送至印刷電路板之基板底部覆晶式半導 體封裝件製法及其結構。 本發明之另一目的在於提供一種不需增加表面黏接技 術（Surface Mounting Technology， SMT)額外製程，運 用現有製程技術即可提高封裝產品散熱效率之基板底部覆 晶式半導體封裝件製法及其結構。 為達成上揭及其他目的，本發明之基板底部覆晶式半 導體封裝件係包含一基板，該基板具有至少一上表面及一 下表面；至少一第一晶片及第二晶片，該第一晶片係接置 於基板之上表面上，並以覆晶或銲線連接（W i r e Bonded)等方式電性連接至基板，而該第二晶片則安置於 基板之下表面；以藉由覆晶技術提供該第二晶片與基板電16605.ptd Page 8 200408088 V. Description of the invention (3) The non-active surface 4 1 2 b is on the printed circuit board 4 3, and the conductive glue 4 2 is used to transfer the heat generated by the wafer 4 1 2 to the printed circuit board 4 3. However, because the thermal resistance coefficient of the conductive and adhesive 42 is lower than that of the semiconductor ^, it cannot effectively improve the heat accumulation of the wafer. Furthermore, this packaging method requires the conductive adhesive 4 2 and the flux (F) to be printed on the printed circuit board 4 3 in advance. 1 ux) (not shown), after the semiconductor package 4 and the conductive adhesive 4 2 are bonded to the positioning, the semiconductor package 4 is soldered to the printed circuit board 43 by multiplexing the reflow soldering method, resulting in a complicated process. Increased degree; Moreover, this method also requires additional processes such as dispensing, which will also increase additional costs. [Summary of the invention]: The main purpose of the present invention is to provide a heat dissipation problem for a semiconductor wafer placed on the same side of the solder ball, so that the heat generated by the operation of the wafer can be transmitted to the bottom of the substrate Manufacturing method and structure of crystalline semiconductor package. Another object of the present invention is to provide a method for manufacturing a flip-chip semiconductor package on the bottom of a substrate and a structure thereof without adding an additional process of Surface Mounting Technology (SMT) and using the existing process technology to improve the heat dissipation efficiency of a package product. . In order to achieve the disclosure and other purposes, the substrate-on-chip semiconductor package of the present invention includes a substrate having at least an upper surface and a lower surface; at least a first wafer and a second wafer, the first wafer system It is placed on the upper surface of the substrate, and is electrically connected to the substrate by means of flip-chip or wire bonding, and the second chip is placed on the lower surface of the substrate; provided by flip-chip technology The second wafer is electrically connected to the substrate
16605.ptd 第9頁 200408088 •五、硌明說明（4) 性‘連結；一散熱片，其具有一第一表面及一相對之第二表 面，該散熱片係藉一塗佈於該散熱片第一表面上之導熱膠 黏接到該第二晶片之非作用表面上，且散熱片之第二表面 上預佈有一銲錫層；以及多數銲球，係與該第二晶片同側 -安置於基板之下表面，俾於銲接時與該散熱片一併回銲至 外部印刷電路板上。 由於該散熱片一表面上預鍍妥一錫層，因此當銲球回 銲到印刷電路板上時，該散熱片可以一併銲接到該印刷電 路板相對應之散熱墊，再透過該散熱墊連接之貫孔將晶片 _量傳遞至印刷電路板内部的接地層（Ground Layer)。 胃以釋散第二晶片在運作中產生之熱量而克服傳統基板底 部覆晶晶片（即第二晶片）無法充分散熱的問題。 而上述基板底部覆晶式半導體封裝件其製法則包含以 下步驟：首先，預備一基板，該基板具有一上表面及一相 對之下表面，以供至少一晶片覆晶連接於基板下表面上， 而與植接於基板下表面上之多數銲球同側安置；接著，製 妥一散熱片，該散熱片具有一第一表面及一相對之第二表 面，該第二表面上預形成有一銲錫層，俾與一具有至少一 散熱墊及多數銲球墊之印刷電路板銲接；之後，佈覆一導 K至該散熱片第一表面，並將該散熱片黏接至基板底部 晶片之非作用表面上，以使基板底面與銲球底面之間 的間隔高度大於「晶片-導電膠-散熱片」之厚度總合；然 後，銲連各銲球至該印刷電路板，使各銲球回銲時能一併 透過該銲錫層將散熱片銲固到該印刷電路板上，因此該基16605.ptd Page 9 200408088 • Fifth, the description of Ming (4) sexual 'connection; a heat sink, which has a first surface and an opposite second surface, the heat sink is coated on the heat sink by a The thermally conductive adhesive on the first surface is adhered to the non-active surface of the second chip, and a solder layer is pre-arranged on the second surface of the heat sink; and most of the solder balls are on the same side as the second chip. The lower surface of the substrate is re-soldered to the external printed circuit board together with the heat sink during soldering. Because a tin layer is pre-plated on one surface of the heat sink, when the solder ball is re-soldered to the printed circuit board, the heat sink can be soldered to the corresponding heat sink pad of the printed circuit board, and then pass through the heat sink pad. The connecting vias pass the wafer volume to the ground layer inside the printed circuit board. The stomach releases the heat generated during the operation of the second chip and overcomes the problem that the conventional chip-on-chip (ie, the second chip) at the bottom of the substrate cannot fully dissipate heat. The method for manufacturing the flip-chip semiconductor package at the bottom of the substrate includes the following steps: first, preparing a substrate having an upper surface and a relatively lower surface for at least one wafer flip-chip to be connected to the lower surface of the substrate; It is placed on the same side as most of the solder balls planted on the lower surface of the substrate; then, a heat sink is prepared, the heat sink has a first surface and an opposite second surface, and a solder is pre-formed on the second surface. Layer, and soldered to a printed circuit board with at least one heat sink pad and a plurality of solder ball pads; after that, a non-interacting layer of K is applied to the first surface of the heat sink, and the heat sink is bonded to the bottom wafer of the substrate. On the surface, the height of the gap between the bottom surface of the substrate and the bottom surface of the solder ball is greater than the thickness of the "wafer-conductive adhesive-radiating fin"; then, solder the solder balls to the printed circuit board, and reflow the solder balls. The heat sink can be fixed to the printed circuit board through the solder layer together, so the base
16605.ptd 第10頁 200408088 五、發明說明（5) 板底部覆晶晶片產生之熱量可透過該導熱膠、散熱片及銲 錫層傳遞至印刷電路板内部之接地層（Ground Layer)·。 【發明詳細說明】： 以下即藉由第1 A至1 E圖詳細說明本發明半導體封裝件 之整體製作流程，並以第2圖顯示此基板底部覆晶式半導 體封裝件製法應用在多晶片模組件（Multi-Chip Module， MCM)之較佳實施例。 如第1 A圖所示，先備妥一散熱片1 0，該散熱片1 0係由 銅、銅合金及其他導熱性良好之金屬材質製成，其具有一 第一表面10 0及一相對之第二表面101，並於該散熱片10之 第二表面1 0 1上預鍍一錫層1 0 2或其他如錫鉛合金等熱熔融 銲料。 如第1 B圖所示，另預備一封裝體1 1，該封裝體1 1係一 基板底部覆晶式結構，其包含有一基板11 0，該基板Π 〇具 有一上表面1 1 0 a及一下表面1 1 0 b以分別電性連接至少一第 一晶片1 1 1及第二晶片1 1 2，惟該第一晶片1 1 1得以銲接連 接（Wire Bonded)或覆晶（FI ip Chip)技術等方式電性 連接至基板1 1 0上表面11 0 a，而該第二晶片1 1 2具有一作用 表面1 1 2 a (即佈設有多數電子電路及電子元件之晶片表 面）及一相對之非作用表面1 1 2 b，且以其作用表面1 1 2 a朝 上之方法將該第二晶片1 1 2安置於基板1 1 0下表面1 1 0 b上。 而後，塗佈一導熱膠1 2至該散熱片1 0第一表面1 0 0上，用 以接合該散熱片1 0及第二晶片1 1 2。並且限定該基板1 1 0下 表面1 1 0 b與銲球11 3底面間之間隔距離需明顯大於第二晶16605.ptd Page 10 200408088 V. Description of the invention (5) The heat generated by the chip-on-chip at the bottom of the board can be transferred to the ground layer inside the printed circuit board through the thermally conductive adhesive, heat sink and solder layer. [Detailed description of the invention]: The following is a detailed description of the overall manufacturing process of the semiconductor package of the present invention by using FIGS. 1A to 1E, and FIG. 2 shows that the method of manufacturing a flip-chip semiconductor package at the bottom of the substrate is applied to a multi-chip mold. A preferred embodiment of a multi-chip module (MCM). As shown in Figure 1A, a heat sink 10 is prepared first. The heat sink 10 is made of copper, copper alloy and other metal materials with good thermal conductivity, and has a first surface 100 and an opposite surface. The second surface 101 is pre-plated on the second surface 101 of the heat sink 10 with a tin layer 102 or other hot-melt solder such as a tin-lead alloy. As shown in FIG. 1B, another package body 1 1 is prepared. The package body 1 1 is a substrate-on-chip structure. The package body 1 1 includes a substrate 110, which has an upper surface 1 1 a and The lower surface 1 1 0 b is electrically connected to at least one first chip 1 1 1 and the second chip 1 1 2 respectively, but the first chip 1 1 1 can be soldered (Wire Bonded) or flip-chip (FI ip Chip). It is electrically connected to the upper surface of the substrate 1 10 by a method such as technology, and the second chip 1 12 has an active surface 1 1 2 a (that is, the surface of the wafer on which most electronic circuits and electronic components are arranged) and an opposite surface. The non-active surface 1 1 2 b, and the second wafer 1 1 2 is placed on the lower surface 1 1 0 b of the substrate 1 10 with the active surface 1 1 a facing upward. Then, a thermally conductive adhesive 12 is coated on the first surface 100 of the heat sink 10 to bond the heat sink 10 and the second wafer 1 12. In addition, the distance between the lower surface of the substrate 1 1 0 b and the bottom surface of the solder ball 11 3 must be significantly larger than that of the second crystal.
16605.ptd 第11頁 200408088 •五、#明說明（6) 片1 1 2、導熱膠1 2及散熱片1 0三者高度之總和。由於高溫 回銲（R e f 1 〇 w)作業中，錫鉛合金材料製成之銲球1 1 3受 熱潰縮（Cο 1 1 apse)，故可藉由銲球潰縮時產生的高度下 降現象，將該散熱片1 0銲接至印刷電路板（未圖示）上； <若以本實施例視之，該導熱膠1 2、散熱片1 0、預鍍錫層 1 0 2及晶片1 1 2之厚度總和係佔銲球1 1 3高度的7 0 %至9 0 %者 為佳（以8 0 %較佳）。 再如第1 C圖所示，另備妥至少一印刷電路板1 3，該印 刷電路板1 3係一多層印刷電路板（M u 11 i - 1 a y e r P r i n t e d rcuit Board)，如以四層板為例，印刷電路板内部一 般設有以銅猪形成之接地層130( Ground Layer)，該接 地層1 3 0藉由多數貫孔1 3 1連通到各接地墊（未圖示），此 等倶為習知製程，故不重複贅述。惟該印刷電路板1 3與第 二晶片1 1 2相對之表面上係分別預設有至少一與該散熱片 相對應之散熱墊1 3 2 ( Th e r m a 1 P ad)以及複數個與該銲球 1 1 3相對應之銲球墊1 3 3，且該散熱墊1 3 2亦如其他接地墊 C未圖示）係藉由多數貫孔1 3 1連通到該接地層1 3 〇上。待 一助焊劑14 ( Flux)塗佈於該散熱墊132及銲球墊133後， 即可進行回銲製程（Reflow Process)。 •如第1D圖所示，將上述封裝體11對位接置到該印刷電 路板1 3上，以使該散熱片1 〇及多數銲球u 3各對應於該散 熱塾1 3 2及銲球墊1 3 3，若再以第3圖更進一步顯示回鋅作 業前後，基板與銲球底面間距與「第二晶片-導熱膠—散熱 片」厚度總和之間的變化。如第3圖可知，未實施回辉作16605.ptd Page 11 200408088 • Five, # 明 说明 (6) The sum of the height of the sheet 1 1 2, the thermal conductive adhesive 12 and the heat sink 10. Since the solder ball 1 1 3 made of tin-lead alloy material is thermally collapsed (Cο 1 1 apse) during high temperature reflow (R ef 1 〇w) operation, it can be caused by the height reduction phenomenon when the solder ball collapses. The heat sink 10 is soldered to a printed circuit board (not shown); < If viewed in this embodiment, the thermally conductive adhesive 1 2, heat sink 10, pre-tinned layer 102, and wafer 1 The total thickness of 1 2 is preferably 70% to 90% of the height of the solder ball 1 1 3 (preferably 80%). As shown in FIG. 1C, at least one printed circuit board 13 is prepared. The printed circuit board 13 is a multilayer printed circuit board (Mu 11 i-1 ayer Printed rcuit Board). As an example, a printed circuit board is generally provided with a ground layer 130 (ground layer) formed of a copper pig. The ground layer 1 3 0 is connected to each ground pad (not shown) through a plurality of through holes 1 3 1. Since these are known processes, they are not repeated here. However, the surfaces of the printed circuit board 13 and the second wafer 1 12 are preset with at least one heat dissipation pad 1 3 2 (Th erma 1 P ad) corresponding to the heat sink and a plurality of solder pads. The ball 1 1 3 corresponds to the solder ball pad 1 3 3, and the heat dissipation pad 1 3 2 (like the other ground pad C) (not shown) is connected to the ground layer 1 3 0 through a plurality of through holes 1 3 1. After a flux 14 (Flux) is applied to the heat dissipation pad 132 and the solder ball pad 133, a reflow process can be performed. • As shown in FIG. 1D, the above-mentioned package body 11 is positioned on the printed circuit board 13 so that the heat sink 10 and the plurality of solder balls u 3 each correspond to the heat sink 1 32 and the solder. The ball pad 1 3 3, if further shown in Figure 3, before and after the zinc return operation, the distance between the substrate and the bottom surface of the solder ball and the "second wafer-thermal conductive adhesive-heat sink" thickness changes. As can be seen in Figure 3, no Huihui works
!6605.ptd 第12頁 200408088 五、發明說明（7) 業前，第二晶片1 1 2、導熱膠1 2、散熱片1 0及銲錫層1 0 2各 元件之整體厚度總和h係小於該銲球1 1 3高度Η—預設距.離 (如前所述，此等元件之整體厚度總和佔銲球高度之7 0 % 至9 0 %)，然而，回銲進行時，該銲球1 1 3受熱潰縮 (Co 1 1 apse)而導致基板1 1 〇與銲球1 1 3底面的間隔距離降 低成Η ’，且回銲後的銲球1 1 3高度Η ’乃不大於第二晶片 1 1 2、導熱膠1 2、散熱片1 0及銲錫層1 0 2之整體厚度h。! 6605.ptd Page 12 200408088 V. Description of the invention (7) Before the industry, the second wafer 1 1 2, the thermally conductive adhesive 1, 2, the heat sink 10, and the solder layer 10, the total thickness h of each component is less than this Solder ball 1 1 3 height Η—preset distance. As described above, the total thickness of these components occupies 70% to 90% of the height of the solder ball. However, when reflow is in progress, the solder ball 1 1 3 heat shrinkage (Co 1 1 apse) caused the substrate 1 1 〇 and the distance between the bottom surface of the solder ball 1 1 3 reduced to Η ', and the height of the solder ball 1 1 3 after reflow 回' is not greater than The two chips 1 1 2, the thermally conductive adhesive 1 2, the overall thickness h of the heat sink 10 and the solder layer 10 2.
再而，該散熱片1 0可與預佈有助焊劑1 4之散熱墊1 3 2 接觸，並藉由該散熱片1 〇第二表面1 〇 1上預佈之銲錫1 〇 2將 該散熱片1 0銲固於印刷電路板1 3之散熱墊1 3 2上。因此， 本發明之半導體封裝件無須增加額外步驟，在銲球回鲜^過 程中即可一併將該散熱片銲接到印刷電路板上。 如第1 E圖所示，回銲作業完成後，該第二晶片i丨2可 透過導熱膠1 2、散熱片1 〇及銲錫層1 〇 2連接至印刷電路 1 3之散熱墊1 3 2上，因此，第二晶片11 2運作時產生的執反^ 將能透過該導熱膠1 2、散熱片1 〇、散熱墊1 3 2、貫i /3、成 傳導到印刷電路板1 3内部之接地層1 3 〇 (當作散熱層）1而 以有效改善基板底部覆晶晶片的熱積存問題。 ’Furthermore, the heat sink 10 can be in contact with a heat sink 1 3 2 which is previously provided with a flux 14, and the heat can be dissipated by the heat sink 10 and a second solder 10 which is provided on the second surface 10. The sheet 10 is soldered on the heat sink 1 3 2 of the printed circuit board 13. Therefore, the semiconductor package of the present invention does not need to add additional steps, and the heat sink can be soldered to the printed circuit board during the solder ball refreshing process. As shown in Figure 1E, after the reflow operation is completed, the second chip i 丨 2 can be connected to the heat sink 1 3 2 of the printed circuit 13 through the thermally conductive adhesive 1 2, the heat sink 1 〇, and the solder layer 1 〇2. Therefore, the reciprocity generated during the operation of the second chip 11 2 will be able to pass through the thermally conductive adhesive 1 2, the heat sink 1 〇, the heat dissipation pad 1 3 2, and i / 3, and be conducted to the inside of the printed circuit board 1 3 The ground layer 1 3 (as a heat dissipation layer) 1 can effectively improve the heat accumulation problem of the chip-on-chip wafer at the bottom of the substrate. ’
綜上所述，經由前述製程可製得一基板底部覆晶 導體封裝件，如第2圖所示，此半導體封裝件1包含有二半 板110，该基板11〇具有一上表面3及一相對之下表基In summary, a chip-on-chip conductor package on the bottom of the substrate can be obtained through the foregoing process. As shown in FIG. 2, the semiconductor package 1 includes two half-boards 110, and the substrate 11 has an upper surface 3 and a Relative table base
1 1 0 b ;至少一第一晶片1 11及第二晶片1 1 2，該第一晶$ 1 1 1係以單一晶片或疊晶等型態接置於基板n 〇上表面 上，並以覆晶或金線銲接等方式與該基板π 〇形成電性〇a 200408088 '吞、發明說明（8) 接關係，而該第二晶片1 1 2則以覆晶方法銲接於銲球1 1 3相 同側，俾使該第二晶片1 1 2之非作用表面1 1 2b朝向提供封 裝件外接之印刷電路板1 3表面；以及一散熱片1 0，其具有 一第一表面1 0 0及一第二表面1 0 1，且該散熱片1 3係藉由一 塗佈於該第一表面1 0 0上之導熱膠1 2黏接至該第二晶片1 1 2 之非作用表面1 1 2 b上，該散熱片1 0第二表面1 0 1則預鍍有 一錫層1 0 2，俾於銲球1 1 3回銲時一併將該散熱片1 0銲接至 印刷電路板1 3上。 以上所述僅為本發明之較佳實施例而已，並非用以限 β本發明之實質技術内容範圍，本發明之實質技術内容係 廣義地定義於下述之申請專利範圍中，任何他人所完成之 技術實體或方法，若是與下述之申請專利範圍所定義者係 完全相同，或是同一等效之變更，均將被視為涵蓋於此申 請專利範圍之中。1 1 0 b; at least one first wafer 11 and second wafer 1 12, the first crystal $ 1 1 1 is connected to the upper surface of the substrate n 0 in a single wafer or a stacked crystal, and the The flip chip or gold wire bonding and other methods form electrical contact with the substrate π 〇a 200408088 'swallowing, description of the invention (8), and the second wafer 1 1 2 is soldered to the solder ball 1 1 3 by flip chip method On the same side, the non-active surface 1 1 2b of the second wafer 1 12 is oriented toward the surface of the printed circuit board 13 that provides external packaging of the package; and a heat sink 10 having a first surface 100 and a The second surface 1 0 1 and the heat sink 1 3 are adhered to the non-active surface 1 1 2 of the second wafer 1 1 2 by a thermally conductive adhesive 1 2 coated on the first surface 1 0 0. On b, the heat sink 10 and the second surface 1 0 1 are pre-plated with a tin layer 102, and the solder ball 1 1 3 is re-soldered and the heat sink 10 is soldered to the printed circuit board 13 . The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the essential technical content of the present invention. The essential technical content of the present invention is broadly defined in the scope of patent applications described below, and is completed by anyone else. If the technical entity or method is exactly the same as defined in the patent application scope described below, or the same equivalent change, it will be considered to be covered by this patent application scope.
16605.ptd 第14頁 200408088 圖式簡單說明 【圖式簡單說明】： 第1 A至1 E圖係顯示本發明基板底部覆晶式半導體封裝 件製法之整體流程示意圖； 第2圖係顯示本發明之基板底部覆晶式半導體封裝件 之剖面示意圖； 第3圖係顯示本發明半導體封裝件中，該基板底部覆 晶晶片進行運作時其晶片熱量傳遞之路徑示意圖； 第4圖係顯示傳統多晶片 圖； 第5圖係顯示美國專利第 件之剖面示意圖；以及 第6圖係顯示美國專利第 件之剖面示意圖。 【元件符號說明】： 1,3,4 半導體封 10 散熱片 100 散熱片第 101 散熱片第 102 銲錫層 11 封裝體 110, 210, 310 基板 110a， 210a， 310a 基板上表 110b， 210b， 310b 基板下表 111， 211， 311 第一晶片 半導體封裝件之剖面示意 5，8 0 1，0 7 2號案之半導體封裝 5，7 9 8，5 6 7號案之半導體封裝 裝件 一表面 二表面 面 面16605.ptd Page 14 20040088 Brief description of the drawings [Simplified illustration of the drawings]: Figures 1 A to 1 E are schematic diagrams showing the overall flow of the method of manufacturing a flip-chip semiconductor package at the bottom of the substrate of the present invention; Figure 2 shows the present invention A schematic cross-sectional view of a flip-chip semiconductor package at the bottom of a substrate; FIG. 3 is a schematic diagram showing a path of heat transfer of a wafer when the flip-chip wafer at the bottom of the substrate is operating in the semiconductor package of the present invention; FIG. 5 is a schematic cross-sectional view of the first U.S. patent; and FIG. 6 is a schematic cross-sectional view of the first U.S. patent. [Description of component symbols]: 1, 3, 4 semiconductor package 10 heat sink 100 heat sink 101 heat sink 102 th solder layer 11 package 110, 210, 310 substrate 110a, 210a, 310a substrate 110b, 210b, 310b substrate The following table shows the cross section of the first chip semiconductor package 111, 211, 311. The semiconductor package No. 5, 8 0 1, 0 7 2 has the semiconductor package No. 5, 7 9 8, 5 6 7 on one surface and two surfaces. Face
16605.ptd 第15頁 20040808816605.ptd Page 15 200408088
16605.ptd 第16頁16605.ptd Page 16
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| Application Number | Priority Date | Filing Date | Title |
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| TW091132643A TWI234256B (en) | 2002-11-06 | 2002-11-06 | Process for fabricating semiconductor package having heat spreader and the same thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| TW091132643A TWI234256B (en) | 2002-11-06 | 2002-11-06 | Process for fabricating semiconductor package having heat spreader and the same thereof |
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| TW200408088A true TW200408088A (en) | 2004-05-16 |
| TWI234256B TWI234256B (en) | 2005-06-11 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI596718B (en) * | 2015-02-13 | 2017-08-21 | 台灣東電化股份有限公司 | A circuit module package structure and packaging method thereof |
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| TWI406388B (en) * | 2008-12-02 | 2013-08-21 | Innolux Corp | Light source array substrate, backlight module and liquid crystal display |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI596718B (en) * | 2015-02-13 | 2017-08-21 | 台灣東電化股份有限公司 | A circuit module package structure and packaging method thereof |
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