TWI265577B - Interconnect structures incorporating low-k dielectric barrier films - Google Patents
Interconnect structures incorporating low-k dielectric barrier films Download PDFInfo
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- TWI265577B TWI265577B TW93100682A TW93100682A TWI265577B TW I265577 B TWI265577 B TW I265577B TW 93100682 A TW93100682 A TW 93100682A TW 93100682 A TW93100682 A TW 93100682A TW I265577 B TWI265577 B TW I265577B
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- diffusion barrier
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02219—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
- H01L21/02222—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen the compound being a silazane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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Description
1265577 五、發明說明(1) 一、 【發明所屬之技術領域】 本發明關係到具有低i電常數(3 . 3 )及對金屬擴 散具有阻障性質之介電層的利用。更特別關係到的是,在 積體電路及微電子元件的一部分之金屬内連線結構中,介 電阻障層的使用。本發明主要的好處在於提供如銅線等之 導電金屬特徵t間電容的降低,.這將使整個晶片的效能提 昇。 二、 【先前技術】 本發明主張之申請專利範圍係受益於在2 0 0 3年1月2 9 曰申請之美國暫時專利申請案6 0/443, 504,在此提供其所 有内容及揭露以作為參考。 具有對金屬擴散阻障之功能的材料,可作為積體電路 某一部份之金屬内連線結構。為產生可靠之元件,對金屬 擴散之阻障乃典型地需要,因為低k内層介電質是典型地 不會防止金屬擴散。在内連線結構中,金屬擴散阻障材料 的配置可不相同,而且通常是決定在金屬擴散阻障的性質 及他們所應用之裝置。含有金屬及介電質的阻障層是共同 地被使用在内連線結構中。 擴散阻障層所含之金屬包含但不僅限於鈕、鎢、釕、 氮化鈕、氮化鈦、T i S i N等。擴散阻障層通常供作内襯 (1 iners),藉此與金屬導電結構形成一共形的介面。通常
4IBM03158TW.ptd 第7頁 1265577 五、發明說明(2) 沉積此材料係藉由化學蒸氣沉積(CVD)、電漿加強式化學 蒸氣沉積(P E C V D )、原子層沉積(A L D)、丨賤鑛、熱蒸發、及 其他有關之方式。用這些材料作為阻障層,金屬阻障層必 需與導電金屬線共形,而且不可以被作為會被當做導電途 徑之覆蓋層。 這有很多方式可以來達成。對這些阻障層有一限制準 則就是,他們對導電金屬線之阻抗的貢獻必不能過高;否 則,金屬導電結構整體阻抗的增加將導致效能的下降。 在微電子元件中擴散阻障層所含之介電質包含,但不 僅限於:氮化矽類化物、碳化矽類化物、氮化矽碳類化 物。一般沉積這些材料通常藉由化學蒸氣沉積(CVD)及電 漿加強化學蒸氣沉積(ΡΈ C V D )之方式,而且可以連續式薄 膜來沉積。不像含有金屬之擴散阻障層,介電層可以被沉 積為覆蓋薄膜,且可以放置在導電金屬線之間。在這種作 法下,這些介電層會提供金屬線之間的電容。這些系統被 局限於他們相當高之介電常數(k = 4. 5到 7. 0 ),造成金屬 線之間有效的介電常數實質增加而導致元件效能的下降。 雖然減少這些阻障層的薄膜厚度也可以導致有效介電常 數n k"的降低,然而不足的厚度層可能失去信賴度,而且 無論如何對介電常數還是有一相當程度之負貢獻。這些系 統的另一個缺點是成本及與牽涉到他們的沉積之工具及製 程相關的複雜度。
4IBM03158TW.ptd 第8頁 1265577 五、發明說明(3) 具有一適當銅鍵結部分體以防止銅擴散之阻障層有被 提出過,係藉由旋轉塗佈介電質或其他溶劑型(s〇lvent based)方式來產生。這些系統基本上將銅鍵結部分體作為 二添加劑來加入,而且具有許多潛在的缺點。因為部份體 對"電基體(dielectric matrix)缺乏共價鍵結,部份體 會經由擴散過程、溶劑萃取、及熱解而被驅除,造成銅阻 障性質的消失。
三、【發明内容】 ^發明關係到具有一低介電常數(即3 · 3 )之陶瓷擴 ,阻障層=内連線結構,該陶瓷擴散阻障層作為對金屬擴 散之一阻障’而且以一溶劑型之方式如旋轉塗佈來施加。 本發明可以在任何使用金屬内連線結構之微電子元件中實 施,此微電子元件包含但不僅限於··高速微處理器、專用 型積體電路(Application Specific lntegrated
Circuits,ASICs)、及記憶儲存器。旋轉塗佈低k陶瓷擴 散層的利用與先前技藝比較是更好的,因為它可允許一擴 散阻障層以一成本有效的方式輕易的產生,而且可以透過
在V電金屬線之間電容的下降形成微電子元件效能的增 加0 此内連線結構可包含形成在基板上之至少一導電金屬 4寸欲,此基板進一步包含至少_絕緣層係環繞該導電金屬
1265577 五、發明說明(4) 特徵。絕緣層可環繞至少一導電金屬特徵的底部,頂端及 週圍表面。此結構可進一步包含至少一導電阻障層係形成 在絕緣層及導電金屬特徵之間。導電金屬特徵及絕緣層的 組合可以重覆以形成一多層内連線堆疊。 内連線結構可以是一個矽晶圓,此矽晶圓可含有微電 子元件、一陶瓷晶片載具、一有機晶片載具、一玻璃基 板、一砷化鎵晶片、碳化矽晶圓、一鎵晶圓、或其他半導 體晶圓。 在本發明之第一實施例中描述一具有陶瓷擴散阻障之 内連線結構。廣義來說内連線結構包含: 形成於一基板頂端之至少一導電金屬特徵; 環繞該至少一金屬特徵之至少一内層介電層;及 形成在至少一内層介電層及至少一導電金屬特徵之間的一 陶瓷擴散阻障,此陶瓷擴散阻障有一 Si vNwCxOyH A組成,其 中 0· IS 0· 9,OS 0· 5,0· 01$ xS 0· 9,OS 0.7, 0.01S 0.8 且 v+w+x+y+z=lo 在第一實施例之一第一實例,以一溶劑型方式來施加 一預陶瓷化高分子前驅物以產生陶瓷擴散阻障,也可做為 一覆蓋阻障層薄膜。其餘之内連線結構可含有一導孔層介 電質、一導線介電質、硬罩層、及埋入式蝕刻中止層。
4IBM03158TW.ptd 第10頁 1265577 五、發明說明(5) 在第一實施例之一第二實例,用與上述相同方法施加 一預陶瓷化高分子前驅物來產生一覆蓋阻障層薄膜,且同 時被使用作一低k覆蓋阻障層及一導孔層介電質。這種方 法產生具有一混合内層介電之一内連線結構,其中該導線 層介電層可以是由任何介電質及導孔層介電質及陶瓷擴散 阻障層所結合的一層。 在第一實施例之一第三實例'用與上述相同方法施加 一預陶瓷化高分子前驅物來產生一陶瓷擴散阻障,且同時 被使用作一低k陶瓷擴散阻障層、一導孔層内層介電質、 及一導線内層介電質。這種方法產生具有一内層介電之一 内連線結構,其中導孔及導線介電層與陶瓷擴散阻障層相 互結合以形成一連續的内層介電層。 在第一實施例之一第四實例,用與上述相同方法施加 一預陶莞化高分子前驅物,在具有一内層介電質之一内連 線結構上產生一陶瓷擴散阻障,此内層介電質包含至少兩 個介電質,其中位於金屬底下之介電質與在其他區域之介 電質是化性相異的。 陶瓷擴散阻障有一低於約3. 3之低介電常數,較佳係 低於約2. 8,更佳係約2. 6。陶瓷擴散阻障層也防止金屬擴 散(較佳是對銅),而且在溫度約3 0 0°C時是熱穩定的。陶 瓷擴散阻障層也可含有孔洞以進一步降低介電常數 k到低
4IBM03158TW.ptd 第11頁 1265577 五、發明說明(6) 於約2. 6,更佳約1. 6。孔洞可藉由移除可能是高分子的犧 牲部分體來產生。孔洞的產生可能牽涉到一高沸點溶劑的 排除製程。孔洞可有一尺寸大小約0 . 5 n m到約2 0 n m,且可 具有一封閉式空間形態。: 在本發明之一第二實施例中描述產生陶瓷擴散阻障的 一種方法。廣義來說此創新的方法包含步驟為: 施加一高分子預陶瓷化前驅物在具有至少一金屬區及至少 一絕緣區的一基板上,該高分子預陶瓷化前驅物有一 S i VN WC x0 yH 各組成,其中 Ο · 1S vS Ο · 8, 0$ Ο · 8, Ο · Ο 5 $ 0.8, OS yS 0·3, 0·05$ 0·8 且 v+w+x+y+z=l; 及 轉化此高分子預陶瓷化前驅物成為一陶瓷擴散阻障,其中 此陶瓷擴散阻障防止金屬的擴散。 被用在第二實施例之高分子預陶瓷化前驅物可有一 S i VN WC x0 yH A 組成,其中 0 · 1 < v< 0 . 8, 0< w< 0 · 8, 0 · 0 5 < x< 0.8,0< y< 3,0.05< z< 0. 8 且 v + w + x + y + z = l。 更詳細來說,先將一高分子預陶瓷化前驅物溶解在一 合適溶劑中,然後將它旋轉塗佈在一内連線結構上以形成 一陶瓷擴散阻障層,此内連線結構之最高表面上有露出金 屬及介電材料。此陶瓷擴散阻障可在一較高之溫度下回 火,例如從約2 0 0°C到約4 0 0°C,以排除殘留之溶劑及使材
4IBM03158TW.ptd 第12頁 1265577 五、發明說明(7) 料產生交聯。傳統的製程可接續形成陶瓷擴散阻障,以產 生具有一低k阻障層薄膜的内連線結構,並且將金屬線與 内層介電層分開。
在塗佈過程中’透過使用一個或組合任何合適製程, 包括但不僅限於:熱硬化、電子幅射、離子幅射、以紫外 光及/或可見光幅射等,將高分子預陶瓷化前驅物薄膜轉 化成一陶瓷擴散阻障層。在製程過程中,高分子預陶瓷化 前驅物可以交聯成一剛性、不溶之基體以形成陶瓷擴散阻 障層,此所形成之陶瓷擴散阻障層可有一介電常數低於約 3. 3、是熱穩定的、有一高崩潰電場值、及防止金屬(較佳 是銅)擴散。對於從含有高分子預陶瓷化前驅物之矽所產 生之系統,此陶瓷擴散阻障層可有一 S i VN WC x0 yH z之組成, 其中 0· IS vS 0. 9, OS wS 0· 5, 0· 01S xS 0· 9, 0$ yS 0.7, 0 . 0 1S zS 0 · 8且¥ + ¥ +又+ 7 + 2 = 1。此陶曼擴散阻障也 可有一 S i VN WC xO ΥΗ 式組成,其中 0 · 1 < v< 0 · 8, 0< w< 0 · 8,0 · 0 5 < x< 0·8, 0< y< 3, 0.05< z< 0·8 且 v+w+x+y+z=l° 本發明之一第三實施例係描述用來產生一陶瓷擴散阻 障層的組成。此高分子預陶瓷化前驅物是一種分子,該分 子係用來形成具有一低介電常數(kS 3. 3 )、防止金屬擴 散、及對溫度在約3 0 0°C是熱穩定之一陶擴散阻障層。此 高分子預陶瓷化前驅物可有任何鏈狀結構(包含線性、網
4IBM03158TW.ptd 第13頁 1265577
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〇< w< 0. 5, O.Ol 且 v+w+x+y+z=1o 的矽也會形成一陶瓷擴散阻障係具 S 1 VN WC x0 yH 之組成,其中 〇 · 1<c v< 〇 < x< 〇· 9,〇< y< 〇· 7,〇· 〇1< z ’ 四、【實施方式】 關係到本發明 組成,在參考所附 的是,在所附圖式 考編號。 之創新的陶瓷擴散層 之圖式之下將有更詳 中,相似及對應之元 之結構、方法、及 細之討論。要注意 件係參照相同之參 本發明提供一種含有金屬及介 構,其中供作對金屬擴散的一阻障之^份之内連線結 含有具低介電常數(k< 3 3)之一介電Z免擴散阻障層乃 二 究化前驅物所產生,將此高分子預 種溶劑型製程’包含但不僅限於:旋轉 塗佈、知描塗佈 '噴塗、含浸塗佈、使用一佈粉刮刀 ^octor blade)等,沉積在預先設想的内連線結構上。此 薄膜可有一厚度自約5nm到約l〇〇〇nm。合適的溶劑包含一 般使用在塗佈上的’包含但不僅限於··丙二醇曱醚醋酸酯 (PGMEA)、丙二醇甲醚(pgmE)、甲苯、二甲苯、i,3,5-甲苯(mesitylene)、丁内酯(bytyrolactone)、酮類 (ketones)、環己 _ (cyclohexanone)、已酮 (hexanones)、庚酮(haptanones)乳酸乙酯(ethyl lactate)0
4IBM03158TW.ptd 第15頁 1265577
此内連線結構可佑带π , 、π W m φ ^ , 而要地,利用習知中對沉積高7刀子 顶陶是化前驅物之任何入沾制 ^ < 丨v 牵涉到曝露在•、驗:;=程來加以清潔。此”:: 可牵涉到習知技術中之的-濕式清潔。此清“ 丁心任何乾式蝕刻製程。 接著,透過使用一個 僅限於:熱硬化、電子^組合任何合適製程’包括但不 可見光幅射,⑯高分子二::離:幅射、以紫外光及/或 擴散阻障層。在溫产和 *瓷化前驅物薄膜轉化成一陶瓷 且可以在一純性22 = 400°c時可以施加熱回火,而 瓷化前驅物可以交聯成二知。在製程過程中,高分子預陶 障層薄膜,此覆蓋阻障^,性、不溶之材質以形成覆蓋阻 3 · 3。除此以外,此陶q厚膜可有—介電常數低於约 有低漏電電流、高崩、、主义散阻障層為典型地熱穩定,具 散。 …電場值、及防止金屬透過此薄旗擴 參考圖1,在第一 多層1 0 0 0,其中每一層例中/ 一内連線結構4 0係包含 所組成,如圖所示。内由‘孔層1 1 0 0及~導線層1 2 0 0 屬特徵33,且可具有介面線結,包=橫跨此結構之導電金 屬特徵3 3及含阻障内舜 系έ阻P早内襯金屬3 4。導電金 mo中之介電質包:=屬34被介電質所圍繞。導線層 硬罩介電質41。在導孔展層介電枭31及一依需要來決定之 孔層介電質32及導線層介電質31之間
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1265577 五、發明說明(12) 塊狀共聚合物、尖頭式、高分子混成等)。高分子預陶兗 化前驅物也可有一分子量在約5 0 0及約1 0 0 0 0 0 〇之間。 高分子預陶瓷化前驅物可以選自以石夕為骨架結構之一 部分的系統’包含:聚石夕氮烧類化物(ρ 〇 1 y s i 1 a z a n e s )、 聚碳矽烷類化物(polycarbosilanes)、聚矽烷矽氮烷類化 物(polysilasilazanes)、聚矽烷類化物(p〇iysilanes)、 聚石夕烧碳石夕烧類化物(ρ ο 1 y s i 1 a c a r b 〇 s i 1 a n e s )、聚石夕氧氮 類化物(polysi loxazanes)、 聚碳矽氮烷類化物 (polycabosi lazanes)、 聚甲矽烷碳二醯亞胺類化物 (polysi lycarbodi imides)、或聚矽烷碳矽氮烷類化物 (ρ ο 1 y s i 1 a c a r b 〇 s i 1 a z a n e s )。高分子預陶竟化前驅物結構 中也可以有聚矽氧烷類化物或聚倍半氧石夕烷 polysi lsesquioxane的某些成份。高分子預陶莞化前驅 物可為聚尿素甲基乙烯基;ε夕氮烷類化物 (polyureamethylvinylsilazane)或聚尿素甲基乙稀基 石夕氮烧類化物(K i ON )。此高分子預陶瓷化前驅物可有鍵^ 到鏈狀骨架之懸垂官能基包含氫基、乙烯基、丙烯基 氧基、矽烷基及炫基。高分子預陶瓷化前驅物亦可由一系 統所組成,此系統具有一碳骨架及由至少$丨及N,也可有、 C、0及蹄組成之懸垂官能基。像這一種材料的實例為聚 甲矽烷碳二醯亞胺類化物。 ’來 而分子預陶瓷化前驅物亦可有與主鏈骨架鍵結之官能
1265577 五、發明說明(13)
基,此主鏈骨架可有一對金屬鍵結之傾向,包括:胺類 (amines)、醯胺類(amides)、亞胺類(imides)、硫酯類 (thioesters)、硫醚類(thioethers)、尿素(ureas)、胺 酯類(urethanes)、【月青】類(nitriles)、異氰酸酯類 (isocyanates)、硫醇類(thiols)、【石風】類 (sulfones)、膦類(phosphines)、氧化膦類(phosphine oxides)、膦亞胺類(phosphonimides)、苯并三嗤 (benzotriazoles)、【口比】σ定類(pyridines)、咪唑類 (imidazoles)、亞胺類(imides)、【口号】唑類 (oxazoles)、苯并【口 等】唾類(benzoxazoles)、【口 塞】嗤類(thiazoles)、【口比】峻類pyrazoles)、三吐 類(tri azoles)、【口塞】吩類(thiophenes)、【口咢】 二峻類(oxadiazoles)、【口塞】【口井】類 (t h i a z i n e s )、【口塞】唑類(t h i a ζ ο 1 e s )、【口奎】唑 【口林】類(quionoxal ines) '苯并咪峻類 (b e n z i m i d a ζ ο 1 e s )、氧【口引】【口朵】類 (oxindoles)、及【口引】【口朵】【口林】類 (i n d ο 1 i n e s )。一般而言,這些含高分子預陶瓷化前驅物 的矽可有一 Si vNwCxOyH妁組成,其中〇. 1$ 0· 8,OS wS 0· 8,0· 05$ xS 0· 8,0$ 0· 3,0··05$ 0· 8 且 v + w + x + y + ζ = 1。含高分子預陶瓷化前驅物的矽亦可有一組 成,其中 0· 1< v< 0· 8, 0< w< 0· 8, 0· 05< x< 0· 8, 0 < y< 3, 0·05< z< 0.8,且 v+w+x+y+z=lo
4IBM03158TW.ptd 第19頁 1265577 五、發明說明(14) 對於自含高分子預陶瓷化前驅物的矽所產生的系統, 陶瓷擴散阻障層可有一 S i VN WC x0 yH妁組成,其中0 · 1$
0.9,〇$ wS 0.5,0·01$ 〇_9,0$ yS 0·7,0.01S zS 〇. 8且 v + w + x + y + zH。陶瓷擴散阻障層亦可有一 Si vNwCxOyH 的組成,其中 〇· 1< v< 0· 9, 0< w< 0· 5, 0· 01< x< 0· 9, 〇< y< 0.7,0·01< z< 0.8,且 v + w + x + y + z = l。陶瓷擴散層 之一較佳組成的一個實例為S i。」6Ν。1 7C 0. 1 7〇 0. 1 7H。. 5。 導線層介電質及導孔層介電質係為具有低介電常數 (k< 3 )之介電材料,而且在溫度大於約3 〇 0°C時是熱穩定 的。對於導線層介電質3 2及導孔層介電質3 1較佳之材料 為:聚矽氧烧、聚倍半氧矽烷、聚芳烯、聚芳烴醚(p〇 1 y (arylene ethers))、及藉由化學蒸氣沉積法產生的介電 質’此介電質具有Si vNwCxOyH钓組成,其中0· · 05$ v‘ 0· 8, OS wS 0. 9,0· 05$ xg 〇· 8,# 〇· 8,〇· 〇5$ S 0· 8 且v + w + x + y + z = l。依需要地,介電質可為空氣或一鈍氣。 此低介電常數材料亦可為多孔的。在一實施例中導線層介 電層有一第一組成,且導孔層介電質有一第二組成,其中 第一組成與第二組成不同。 一硬罩介電質4 1可依需要地被使用。此硬罩介電質具 可有一厚度範圍從約5 nm到約1 〇 〇 nm。用作硬罩介電質之較 佳材料為:聚砍氧烧、聚倍半氧矽烷、或具有s i vN / χ〇 yIi妁 組成’其中 〇· 〇5$ 〇· 8, 〇. 9, 〇· 〇5$ 〇· 8, 0
4IBM03158TW.ptd 第20頁 1265577 五、發明說明(15) S yS 0· 8,0· 05S 0· 8 且 v + w + x + y + z = l之 CVD沉積的介 電質。此介電質亦可為Si vNwCxOyH/斤組成,其中0. 〇5< v< 0.8, 0< w< 0.9, 0.05< χ< 0.8, 0< y< 0.8, 0.05< z< 0.8,且 v+w+x+y+z=l° 在導孔層介電質3 2及導線層介電質3 1之間可依需要地 放置一介電質蝕刻中止層37。介電質蝕刻中止層可有一厚 度範圍圍從約5nm到約l〇〇nm。用作介電質中止層之較佳材 料為:聚矽氧烷、聚倍半氧矽烷、或具有S i vN wC x〇 yII妁組 成’其中 0 · 0 5‘ vS 0 · 8, 0$ 0. 9, 0 . 05S 0. 8, 0 S 0 · 8,0 · 0 5S 〇 · 8 且 v + w +x +y + z = 1之任何 C VD沉積 的介電質。S i VN WC xO yH必可為閘極介電質及導線層介電質的 組成,其中 0· 05< v< 〇. 8, 0< w< 0. 9, 0. 05< χ< 0. 8, 〇 < y< 0· 8,0· 05< z< 〇 · 8且 v + w + x + y + z=l。 作為導電金屬特徵較佳之材料為鋼、金、銀、銘及上 述之合金。在‘笔金屬層特徵的頂端表面可有用來降低電 性遷移的層’包括始、鶴、及填之材料。導電金屬特徵的 頂端表面可有一部分體用來降低金屬氧化的傾向,包括笨 并三嗤(benzotriazoles)、胺類(amines)v 醯胺類 (amides)、亞 5*類(imides)、硫醋類(thioesters)、硫 _ 類(thioethers)、尿素(ureas)、胺 g旨類(urethanes)、 【月青】類(nitriles)、異氰酸酉旨類(iS0CyanateS)、硫 醇類(thiols)、【石風】類(suifones)、膦類
4IBM03158TW.ptd 第21頁 1265577 五、發明說明(16) (phosphines)、氧化膦類(phosphine oxides)、膦亞胺類 (phosphonimides)、【口 比】唆類(pyridines)、咪嗤類 (imidazoles)、亞胺類(imides)、【口咢】唑類 (oxazoles)、苯并【口 等】唑類(benzoxazoles)、【口 塞】唾類(thiazoles)、【口比】峻類pyrazoles)、三口坐 類(triazoles)、【口塞】吩類(thiophenes)、【口号】 二唾類(oxadiazoles)、【口塞】【口井】類 (thiazines)、【口塞】嗤類(thiazoles)、【口奎】嗤 【口林】類(quionoxalines)、苯并咪唾類 (benzimidazoles)、氧【口引】【口朵】類 (oxindoles)、及【口引】【口朵】【口林】類 (indol ines)。作為含阻障内襯金屬之較佳材料為鈕、氮 化钽、鎢、鈦、氮化鈦、釕、T i S i N、及上述之組合。 參考圖2,在第一實施例中由多層丨000組成之一個内 連線結構40的另一實例,其中每一層可由一導孔層u 〇〇及 一導線層1 2 〇 0所組成,如圖所示。内連線結構包含橫跨此 結構之導電金屬特徵3 3,且可具有一含阻障内襯金屬3 4之 介面。導電金屬特徵3 3及含阻障内襯金屬3 4被介電質所圍 繞。導線層1 200中之介電質包含導線層介電質43及一依需 要來決定之硬罩介電質❹導孔層11 〇 〇中之介電質包含出現 在導電金屬線下的導孔層介電質3 2、出現在導孔層上方沒 有金屬線的區域之導線層介電質4 3、及陶瓷擴散阻障層 36。在導孔層介電質42及導線層介電質43之間可依需^地
4IBM03158TW.ptd 第 22 頁 1265577 五、發明說明(17) 放置一介電钱刻中止層3 7。 參考圖3,生產陶瓷擴散阻障層之一般製程流程如圖 所示。在步驟1,使用任何溶劑來配製一種含有高分子預 陶瓷化前驅物,此溶劑為用於塗佈之一般溶劑包含但不僅 限於:丙二醇、丙二醇甲醚醋酸酯 (PGMEA)、丙二醇曱 醚 (PGME)、甲苯、二甲苯、茴香醚、1,3,5-甲苯 (mesitylene)' 丁内酯、環己_、已酮、乳酸乙酯、庚 嗣〇 一種抗條痕劑(a n t i s t r i a t i ο n a g e n t )可以共同溶解 在含有高分子預陶瓷化前驅物之溶液中,以產生高度均勻 性的薄膜。抗條痕劑的量可少於此含有高分子預陶瓷化前 驅物之溶液之約1 %。 一種黏著促進劑可以共同溶解在含有高分子預陶瓷化 前驅物之溶液中,且在應用此高分子預陶瓷化前驅物過程 中可隔離薄膜介面。黏著促進劑的量可少於此含有高分子 預陶瓷化前驅物之溶液之約2 %。 在沉積高分子預陶瓷化前驅物之前,可在依需要來選 擇清潔内連線結構之步驟2。此清潔可以牽涉到曝露在 酸、驗及有機溶劑的一濕式清潔。此清潔也可牽涉到習知 技術中之任何乾式蝕刻製程。依需要來選擇之步驟3係為
4IBM03158TW.ptd 第23頁 1265577 五、發明說明(18) 可在基板表面上施加黏著促進劑(例如,内連線結構)。較 佳之黏著劑有S i xL yR疼組成,其中L係選自羥基、甲氧基、 乙氧基、乙醯氧基、烷氧基、羰基、胺類、或鹵素類所組 成之群組,而R係選自氫基、甲基、乙基、乙烯基、及苯 基(任合烷基或芳基)所組成之群組。此黏著促進劑亦可是 六甲基二石夕氮烧(hexamethyldisilazane,HMDS)、乙烯基 二酷酸基石夕烧(vinyltriacetoxysilane)、胺丙基三甲氧 基石夕烧(aminopropyltrimethoxysilane),乙稀基三甲氧 基石夕烧(vinyl trimethoxy silane)或以上之組合。
+、接著在步驟4,藉一溶劑型製程,包含旋轉塗佈、掃 =k佈喷塗、含浸塗佈、使用一佈粉刮刀或上述之組 合,將高分子預陶瓷化前驅物塗佈在預設之基板上。高分 t ^曼化前驅物可有一約5nm到約1 0 0 0_厚度。視需 ^ k擇=步驟5中’黏著促進劑可以施加在含有高分子 =t 2二驅物之薄膜的頂端表面。較佳的黏著促進劑包 s以上所述。
障層係透過使m任何化成陶❹ 化、電子幅射、離子之組合包含:熱硬 幅射等。以熱回火為例,可卜^離子幅射、以可見 及在鈍化氣體下執行,純化,過約4〇货之溫度7 (f—g㈣)、及氬氣成形氣體 ,、 在此I私過程中,高分子預障
1265577 五、發明說明(19) 竟化刖驅物即可交聯成 選擇性之共同溶解黏著 可隔離成薄膜介面。在 進劑可以施加在陶瓷擴 促進劑包含以上所述。
—剛性、不溶材質。如果有使用此 促進劑’在轉化過程中,此黏著劑 f需要來選擇的步驟7中,黏著促 政阻卩早層的頂端表面。較佳的黏著 含有局分子預 特性之部分體,包 的溶劑犧牲性高分 化成陶瓷擴散阻障 性高分子材料可選 酯、聚丙烯酸酯、 較佳陶瓷擴散 穩定的、有低漏電 散穿透薄膜。參考 前驅物所產生的薄 特性,如在場低於 (a))’及在室溫下 7amps/cm 2° =化前驅物的溶液亦可含有產生孔洞 子二解成低分子量副產物及/或高沸點 爲料,在將高分子預陶瓷化前驅物轉 二^秩中會被排除到薄膜外。這些犧牲 取:(笨乙烯)、聚酯、聚甲基丙烯酸 聚二醇、聚醯胺、及聚冰片烯。 層具有一介電常數低於3.3、是熱 私流、有局崩潰電場值、及防止金屬擴 圖4 (a )到4 ( b)係由一聚矽氮烷預陶瓷化 膜所展現的合適之崩潰特性及漏電電流 7MV/cm係顯現低比例的崩潰(如圖4 及1 5 0 C下,漏電電流係低於1 〇 - 以清:我巧”述-些實施例時,可 4- * ^ ^ ^ 上述内谷疋很谷易藉由熟悉此項技藝人 二改變。所以,我們並不希望被已圖式或已描述
4IBM03158TW.ptd 第25頁
1265577
4IBM03158TW.ptd 第26頁 1265577 圖式簡單說明 五、【圖式簡單說明】 圖1為本發明一半導體元件之一剖面圖。 圖2為本發明另一半導體元件之一剖面圖。 圖3為本發明用來產生陶瓷擴散阻障層的一般製程流程。 圖4 (a )及圖4 (b)為本發明之一陶瓷擴散阻障層的電性特性 的實例。 圖式元件符號說明 1000 多 層 1100 導 孔 層 1200 導 線 層 31 導 線 層 介 電 層 32 導 孔 層 介 電 層 33 導 電 金 屬 特 徵 34 含 阻 障 内 襯 金 屬 36 陶 瓷 擴 散 阻 障 37 介 電 質 雀虫 刻 中 止層 40 内 連 線 結 構 41 硬 罩 介 電 層 42 導 孔 層 介 電 層 43 導 線 層 介 電 層
4IBM03158TW.ptd 第27頁
Claims (1)
1265577 六、申請專利範圍 1. 一種内連線結構,包含: 至少一導電金屬特徵,係形成在一基板上; 至少一内層介電層,係環繞該至少一金屬特徵;及 一陶兗擴散阻障(ceramic diffusion barrier),介於 該至少一内層介電層及該至少一導體金屬特徵之間,具有 一 S i VN WC x0 yH 矣組成,其中 0 · IS 0 · 9, 0$ 0 . 5, 0 . 0 1 S xS 0.9, 0$ yS 0·7, 0.01S zS 0.8,且 v+w+x+y+z=l。 2 .如申請專利範圍第1項之内連線結構,其中該陶瓷擴散 阻障有一介電常數低於約3. 3。 進 障 3阻 第 圍 範 利 專 請 申 如 導 一 含 包 步 構η 結11 /tv 線 連層 内電 之介 項層 1線 其中該陶瓷擴散 level 4.如申請專利範爵第1項之内連線結構,其中該陶瓷擴散 阻障進一步包含一導線層介電層及一導孔層介電層 (via level dielectric layer)。 5 .如申請專利範圍第1項之内連線結構,其中該至少一内 層介電層進一步包含具有一第一組成之一導線層介電層、 及具有一第二組成之一導孔層介電層,其中該第一組成與 該第二組成不相同。
4IBM03158TW.ptd 第28頁 1265577 六、申請專利範圍 6 ·如申請專利範圍第1項之結構,其中該至少一内層介電 層具有一組成係包含空氣 (air)或鈍氣 (inert gas)。 7 ·如申請專利範圍第1項之内連線結構,其申該至少一内 層介電層具有一組成係包含Si vNwCxOyHz,其中0. 05$ 0·8,OS 0·9, 0·05$ 0.8,0$ 0·8,0·05$ 〇·8 且 v+w+x+y+z=lo 8 ·如申請專利範圍第1項之内連線結構,進一步包含一含 阻 P平内襯金屬(liningmetal containing barrier), 其中該含阻障内襯金屬在該至少一導電金屬特徵及該至少 一内層介電層之間形成一介面,該含阻障内襯金屬包含 组、氮化鈕、鎢、鈦、氮化鈦、釕、T i S i N、或上述之組 合。 9 ·如申印專利範圍第$項之内連線結構,其中該至少一介 電層進一步包含一介電蝕刻中止層,係位於該導線層介電 層及該導孔層介電層之間。 1 〇 ·如申請專利範圍第1項之内連線結構,其中該陶瓷擴 散阻障有一 SiU6NG.17CG.17HQ•良組成。 1/ · 一種^ k成一陶瓷擴散阻障層的方法,包含: 施加面刀子預陶兗化前驅物(polymeric preceramic
第29頁 1265577 六、申請專利範圍 precursor)之一塗料在一半導體基板上,其中該高分子預 陶究化前驅物具有一 S i VN WC x0 yH之組成,其中 0· 1$ 0· 8,OS wS 0· 8,0· 05g 〇· 8,0$ 〇· 3, 0.05S 0·8 且 v+w+x+y+z=l;及 轉化該高分子預陶瓷化前驅物成為一陶瓷擴散阻障層,其 中該陶瓷擴散阻障防止金屬擴散。 1 2 ·如申請專利範圍第1 1項所述之方法,其中該高分子預 陶兗化前驅物包含聚石夕氮烧類化物(ρ ο 1 y s i 1 a z a n e s )、聚 碳石夕烧類化物(p ο 1 y c a r b o s i 1 a n e s )、聚石夕烧石夕氮烧類化物 (polysilasilazanes)、聚石夕院類化物(polysilanes)、聚 石夕烧碳石夕烧類化物(ρ ο 1 y s i 1 a c a r b 〇 s i 1 a n e s )、聚石夕氧氮類 化物(ρ ο 1 y s i 1 o x a z a n e s )、聚破^夕氮烧類化物 (p ο 1 y c a b o s i 1 a z a n e s )、 聚曱石夕炫礙二醯亞胺類化物 (ρ ο 1 y s i 1 y c a r b 〇 d i i m i d e s )、或聚石夕统碳石夕氮烧類化物 (polysilacarbosilazanes)。 1 3 .如申請專利範圍第1 1項所述之方法,其中該施加一高 分子預陶瓷化前驅物之一塗料係包含製備一該高分子預陶 瓷化前驅物與一溶劑之溶液;及接著藉一溶劑型製程 (solvent based process)來施加該溶液。 1 4.如申請專利範圍第1 3項所述之方法,其中該溶劑型製 程包含旋轉塗佈、喷塗、掃描塗佈(s c a n c 〇 a t i n g )、含浸
4IBM03158TW.ptd 第30頁 1265577 六、申請專利範圍 塗佈、或上述之組合。 1 5 .如申請專利範圍第1 3項所述之方法,其中諄溶液進一 步包含一黏著促進劑係共同溶解在含有該高分子預陶瓷化 前驅物之該溶劑中,該黏著促進劑有一 S i XL yR z,其中L係選 自羥基、曱氧基、乙氧基、乙醯氧基、烷氧基、羰基、胺 類、或iS素類所組成之群組,而R係選自氳基(hydrido)、 甲基、乙基、乙烯基、及苯基所組成之群組。 1 6 ·如申請專利範圍第1 3項所述之方法,其中該溶劑包含 丙二醇、丙二醇甲醚醋酸酯 (PGMEA)、丙二醇甲醚 (PGME)、甲苯、二甲苯、®香醚、1,3, 5-甲苯 (mesitylene)' 丁内酯、環己_、已酮、乳酸乙醋、庚 酮、或上述之組合。 1 7 .如申請專利範圍第1 3項所述之方法,其中將該高分子 預陶磁化前驅體轉化成該陶磁阻障層係包含熱硬化、電子 幅射、離子幅射、以紫外光離子幅射、以可見光幅射、或 上述之組合。 1 8.如申請專利範圍第1 3項所述之方法,其中產生孔洞之 一犧牲部分體係共同溶解在含有高分子預陶瓷化前驅物的 該溶液中,其中該犧牲高分子係選自聚(苯乙烯)、聚 (酯)、聚(甲基丙烯酸酯)、聚(丙烯酸酯)、聚(二
4IBM03158TW.ptd 第31頁 1265577 六、申請專利範圍 醇)、聚(醯胺)、及聚(降冰片烯)。 1 9 .如申請專利範圍第1 3項所述之方法,其中將一抗條痕 劑 (antistriation agent)共同溶入含有該高分子預陶 曼化前驅物之該溶液中。 · 2 0 .如申請專利範圍第1 1項所述之方法,其中該半導體基 板包含至少一金屬區及至少一介電區,其中該陶瓷擴散阻 障係位於該至少一金屬區及該至少一介電區之間。
1 III f
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US7445814B2 (en) * | 2003-10-22 | 2008-11-04 | Hewlett-Packard Development Company, L.P. | Methods of making porous cermet and ceramic films |
US8354751B2 (en) * | 2008-06-16 | 2013-01-15 | International Business Machines Corporation | Interconnect structure for electromigration enhancement |
JP2010021401A (ja) * | 2008-07-11 | 2010-01-28 | Fujitsu Microelectronics Ltd | 半導体装置及びその製造方法 |
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WO2004068550A3 (en) | 2005-10-27 |
WO2004068550A2 (en) | 2004-08-12 |
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US20050087876A1 (en) | 2005-04-28 |
TW200503121A (en) | 2005-01-16 |
US20050206004A1 (en) | 2005-09-22 |
EP1595275A2 (en) | 2005-11-16 |
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