TWI259850B - Dual frequency plasma enhanced chemical vapor deposition of silicon carbide layers - Google Patents

Dual frequency plasma enhanced chemical vapor deposition of silicon carbide layers Download PDF

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Publication number
TWI259850B
TWI259850B TW090119426A TW90119426A TWI259850B TW I259850 B TWI259850 B TW I259850B TW 090119426 A TW090119426 A TW 090119426A TW 90119426 A TW90119426 A TW 90119426A TW I259850 B TWI259850 B TW I259850B
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Taiwan
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layer
page
substrate
silicon carbide
california
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TW090119426A
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English (en)
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Srinivas Nemani
Li-Qun Xia
Ellie Yieh
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Applied Materials Inc
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/32—Carbides
    • C23C16/325—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/505—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
    • H—ELECTRICITY
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    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
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    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02131—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
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    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
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    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
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    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
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    • H01L21/0276—Photolithographic processes using an anti-reflective coating

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Formation Of Insulating Films (AREA)
  • Chemical Vapour Deposition (AREA)

Description

A7
1259850 五、發明說明（） 發明領媸： 本發明係有關於碳化矽層，特別县古 竹⑺疋有關於一種形成碳 化碎層之方法。 發明背景： 積體電路已發展成為複雜的裝置，單一晶片上可容納 數百萬個7L件（例如電晶體、電容器及電阻器等）。晶片設 計的發展持續要求更快的電路系統及更高的電路密度。更 高電路密度的要求使得縮小積體電路元件的尺寸成為必 要。 當積體電路元件的尺寸縮小之後（例如次微米的尺 度），用於製造此等元件的材料對於此等元件的電子特性 有所貢獻。例如，低電阻的金屬内連線（例如鋁及銅）可在 積體電路上的元件之間提供導電路徑。 在典型情況下’金屬内連線係藉由絕緣材料而彼此電 性絕緣。當鄰近的金屬内連線及/或體絕緣材料的厚度位於 次微米尺度時，此種金屬内連線之間將有可能產生電容搞 合。金屬内連線鄰近之間的電容镇合可能會造成線路干擾 及/或阻容（RC)延遲，因而會降低積體電路的整體性能。為 了避免金屬内連線鄰近之間的電容耦合，必須使用低介電 常數（k)的絕緣材料（例如介電常數低於約5 .〇)。 此外，低介電常數阻障層經常用於將金屬内連線與體 絕緣材料分開。阻障層可減少金屬擴散至體絕緣材料。五 人不希望金屬擴散至體絕緣材料，因為此種擴散將會影響 第4頁 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂-ί------線< 經濟部智慧財產局員工消費合作社印製 1259850
五、發明說明（） 積電路的電子特性，或使其無法運作。 對積體電路更高密度的要求同時會引發對於積體電 路製造之處理程序的要求。例如，在使用傳統微影技術的 處理程序當中，能量敏感性抗蝕層形成於基材上的一疊材 料層上方。許多位於下方的材料層會反射紫外光。此種反 射現象可能會使例如線路及介層孔（via)等形成於能量敏 感性抗餘材料中的特徵結構之尺寸產生扭曲。 一種提議用來減少下層材料之反射的技術是利用抗 反射塗層（anti-refiective coating，ARC)。ARC 係在圖案化 抗餘層之前先形成於反射材料層之上。arc能夠在抗蝕層 造影當中，抑制下方材料層的反射現象，以便在能量敏感 性抗姓層中提供精確的複製圖案。 奴化碎（S i C)已被提議用來做為積體電路上的阻障層. 及/或ARC ’因為碳化矽層可具有低介電常數（介電常數小 於約5 · 〇) ’且具有良好的擴散阻障特性，以及良好的光吸 收特性。 然而’碳化矽阻障層通常係利用化學氣相沉積（CVD) 技術而形成。利用CVD所形成的Sic層傾向具有高氧氣 含里（例如’氧氣含量高於約4%)。吾人不希望得到高氧氣 含量’因為如此將會促使諸如銅等金屬從金屬内連線通過 SiC層而擴散到絕緣材料内。 因此’在此技術領域需要一種形成應用於積體電路製 程之可靠的碳化矽擴散阻障層之方法。特別是，此種碳化 碎擴政阻障層亦可做為抗反射塗層（ARC)。 第5頁 本紙張尺度顧中ϋ國家標準（CNS)A4規格（210 X 297公髮 ___________i (請先閱讀背面之注意事項再填寫本頁) 訂--------線赢 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 1259850
碳化矽層的折射率（n)及吸收係數（^)可加以調整，因為在 碳化矽的形成過程中，折射率及吸收係數可為氣體混合物 組成的函數而隨著所想要的範圍改變。當碳化矽層形成於 基材上之後，能量敏感性抗蚀材料層將形成於其上方。在 波長小於約250nm的情況下，一圖案被界定於能量敏感性 抗蚀層。接著，界定於能量敏感性抗钱層的圖案會被轉換 至碳化石夕層。當碳化矽層經過圖案化之後，此圖案可選擇 第6頁 本紙張關家標f(cns)A4祕㈣x 297公4)
1259850 A7 五、發明說明（ 性地被轉換至基材 圖式簡單說明： 本發明之教示可藉由參照以下詳細說明及所附圖式 而容易理解，其中： 第1圖描繪可用於實施在此描述之設備的概要圖； 第2a-2e圖描繪基材結構在積體電路製造之不同階段的截 面圖，其中該結構係以碳化梦做為硬罩幕； 第3a-3d圖描繪雙重鑲嵌結構在杳 傅在％體電路製造之不同階段 的截面圖，其中該結構# 再係以奴化矽做為硬罩幕；及 第4a-4e圖描緣基材結構在積， 償隨電路製造之不同階段的截 面圖，其中該結構係以 以奴化矽做為抗反射塗層 (ARC)。 經濟部智慧財產局員工消費合作社印製 圖號對照說明： 10 晶圓處理系統 102 真空幫浦 110 控制單元 114 支援電路系統 118 訊號匯流排 120 噴頭 150 基座 172 溫度感應器 200 基材 1〇〇 1〇6 112 116 Π9 13〇 17〇 19〇 202 第7頁 處理室 電源供應器 中央處理單元 控制軟體 射頻電源 氣體板 加熱單元 晶圓 材料層 ------------------訂·-------線%· (請先閱讀背面之注意事項再填寫本頁)
1259850 五、發明說明（） 204 碳化矽層 206 中介層 208 能量敏感性光阻材料 210 罩幕 300 基材 302 第一介電層 304 碳化矽層 306 接觸孔/介層孔 308 弟—介電層 310 内連線 314 導電材料 316 阻障層 400 基材 402 碳化矽層 404 能量敏感性光阻材料 406 罩幕 450 基材結構 發明詳細說明： (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 第1圖係晶圓處理系統1 ο之概要圖，晶圓處理系統 1 0可用於根據在此描述之實施例來沉積碳化矽層。在典型 情況下’系統1 0包含處理室1 〇 〇、氣體板1 3 〇、控制單元 1 1 0 ’以及其它硬體裝置’例如電源供應器1 1 9、1 〇 6及真 S幫浦1 〇 2。晶圓處理系統1 〇的範例包括電漿激發化學氣 相沉積（PECVD)處理室’例如DXZ™處理室，其可從位於 美國加州聖克拉拉市的應用材料公司（Applied Materials Inc.)購得。 晶圓處理系統1 0的細節已描述於與本案具共同受讓 之美國專利申請案第09/21 1，998號，該美國專利申請案之 發明名稱為「高溫化學氣相沉積處理室」（"High Temperature Chemical Vapor Deposition Chamber") » 該專 利申請案於1998年12月14日提出申請，在此併入此相 第8頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1259850 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（） 關木做為參考。系統丨〇的顯著特徵將簡要描述如下。 處理$ 100概括覆蓋支撐基座150,該支撐基座係用 於支撐如半導體晶圓190之類的基材。基座15〇通常可在 處理至100内部利用位移機制（未圖示）而沿著垂直方向移 動。 晶圓190可纟沉積碳化碎之前行被加熱至所想要 的=度，並取決於特定製程而定。例如，晶圓支撐基座15〇 Y藉由嵌入式加熱單元17〇進行加熱。基座15〇可藉由將 人泥電源供應器1 06所提供的電流通往加熱單元i 7〇，而 以電阻方式進行加熱，然後再由基座15〇 I加鼽晶圓 190 〇 、溫度感應H 172，例如熱電偶，亦内嵌於晶圓支撐基 座15 〇，藉以如同傳統方式來監測基座i 5 〇的溫度。測量 到的溫度係用於反饋迴路，藉以控制供應到加熱單元170 勺％源，以使晶圓的溫度能夠維持或控制在所想要且適於 特定製程應用的溫度。此外，亦可選用輻射熱能(未圖示） 來加熱基座。 真2幫浦1 0 2係用於抽取處理室丨〇 〇當中的氣體，以 維持處理室100内部的適當氣體流量及壓力。喷頭12〇係 位於晶圓支撐基座150的上方，製程氣體可透過噴頭而被 導入處理罜。噴頭1 20係連接於氣體板丨3 〇，其可控制及 供應各種用於不同製程階段的氣體。 賣頭120及晶圓支撐基座i 5〇亦構成一對隔開的電 極。當電場在此等電極之間產生時，被導入處理室1〇〇内 第9頁 ---------^ij-------^^^1 (請先閱讀背面之注意事項再填寫本頁) 1259850
、發明說明（ 經濟部智慧財產局員工消費合作社印製 邵的製程氣體將合祜、、蘇益4 + m 曰被激發成電漿。電場係藉由將喷頭1 2 0 連接至w 口射頻電源i i 9而產生。混頻rf電源的細節已 、田ϋ於與本木具共同雙讓之美國專利第6,〇41，川號，該 美國專利之發明名稱為「在處理基材當中利用非對稱波形 制離子森擊 f ” τ τ Q θ r 」（ se 〇f an Asymmetric Waveform to ontrol Ion Bombardment During Substrate Processing") » 該美國專利於2000年3月28日獲准，在此併入此專利做 為參考。 在典型^況下’在控制單元丨丨〇控制下的混頻RF電 源1 19可將南頻電源（例如在約1〇MHz至15MHz範圍内的 RF電源）及低頻電源（例如在約l5〇KHz至45〇KHz範圍内 的RF電源）供應到噴頭12〇。高頻rf電源及低頻電源 兩者係透過匹配網路（未圖示）而與.噴頭12〇耦合。高頻rF 電源及低頻RF電源亦可選擇與晶圓支撐基座丨5〇耦合， 或其中一個與噴頭丨2〇耦合，而另一個與晶圓支撐基座 1 5 0耦合。 電漿激發化學氣相沉積（PECVD)技術係藉由在基材 附近的反應區域施加電場而促使反應氣體的激發及/或裂 解，從而產生反應物種的電漿。電漿物種的反應性可降低 發生化學反應所需的能量，因此，其在功效上可降低此種 PECVD製程所需的溫度。 通過氣體板130的氣體流量係藉由流量控制器 (M F C)(未圖示）及控制單元1 1 〇來進行適當的控制及調 整。喷頭1 2 0可讓來自氣體板1 3 0的製程氣體均勻地導入 第10頁 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公f ) ^ --------訂丨---------線 (請先閱讀背面之注意事項再填寫本頁) 1259850 A7 五、發明說明（） 及散佈於處理室1〇〇。 如第1圖所示’控制單元110包含中央處理單元 (CPU)112'支援電路系統114’以及含有相關控制軟體U6 的記憶體。控制單元11〇係負責晶圓處理所需之各種不同 步驟的自動化控制，彳丨』.曰
如· 0日圓運送、氣流控制、混頻RF 電源控制、溫慶扣告，丨、由 ^ 4 二制處理至抽氧及其它步驟。控制單元 110與晶圓處理孕絲1n +欠絲 里乐、、无10 I各種裝置之間的雙向通訊係透 過許多訊號纜線逸杯田 & f、 订處理’邊♦訊號纜線統稱為訊號匯流 排11 8，其中—些匯流排圖示於第1圖。 w中，處理單元（CPU)112可為任何一種一般用途的電 處理态並可在工業環境中用於控制製程處理室，以及 做為副處理器。雷月溢φ I古 每中了使用任何適當的記憶體，例如隨 機存取記憶體、唯赛分斤减 ,,^ 項记憶m、摩人碟機、硬碟機，或其它任 何位於近端或遠端的勃p蚀六壯艰 ' 的數位儲存裝置。各式支援電路系統可 與CPU耦合，並以值絲士 + ， 卫^傳扁万式支板處理器。處理過程所需的 例行程序可儲存在1 咅蝴 I.,,
在记U m 或由位於遠端的第二個CPU 來執行。 田基材190被放置在晶圓支撐基座150上之後，處理 過程的例行程序即被執行。當執行處理過程的例行程序 時，例行程序會將一般用途電腦轉換成特殊用途電腦，並 且控制處理室的運作，茲y 、 連作精以執伃沉積製程。在另一種情沉 下，處理室的運作可士丨田乂上 、土 J用位於逆端的硬體加以控制，即如 特殊應用積體電路ίΑςΐΓ、十、甘、1 C)或其它類型的硬體實作，或由軟 體與硬體的結合來控制。 第11頁 ______I I I K L (請先閱讀背面之注意事項再填寫本頁) 訂—--- 線秦 經濟部智慧財產局員工消費合作社印製 A7 1259850 五、發明說明（） 滅化妙層的形成 在-實施例中，碳切層係經由氣體混合物之反應而 形成，此乳體混合物包切源、碳源及惰性氣體。碎源及 碳源可為其一般化學式為Si c Η夕右撼☆ xCyHz <有機矽烷化合物，其 中X的範圍從1至2，y的範圍從丨 剡6而z的範圍則從 6到20。例如，甲基矽烷（SiCH )、一 6) —甲基矽烷（Sic2H8)、 三甲基㈣（SiC3Hl°)、四曱基錢（SiC4Hl2)、二乙基秒燒 (SiC4H12)及*它化合物可做為有機矽烷化合物。在其它選 擇中’㈣（’4)、乙錢（Si2H6)、甲燒（Cl)及其^成物 可做為矽源及碳源。 氦氣、氬氣、氮氣或其合成物及其它氣體可做為惰性 氣體。 概括而言，以下的沉積製程參數可用於形成碳化矽 層。製程參數的範圍如下：曰曰曰圓溫度約200至彻。C，處 理1：的壓力約3 i 15托耳，有機秒燒化合物的流速约功 至200標準立方公分（sccm),惰性氣體的流速約5〇至谷㈧ seem(使得有機矽烷之流速與惰性氣體之流速的比率範團 介於1 ·· 1至1 : 4)，氣體板的間隔約3〇〇至6〇〇密爾（mu， 千分之一英吋），而混頻RF電源具有至少一第一 rf電源， 其頻率範圍介於約13MHz至約27MHz，而功率則介於約 2〇〇至800瓦，混頻RF電源另具有至少一第二RF電源， 其頻率範圍介於約ΙΟΟΚΗζ至约50〇κΗζ，而功率則介於约 1至200瓦。第二rf功率與總混頻功率的比率最好小於 約〇· 6至1 · 〇。當使用購自美國加州聖克拉拉市之應用材 第12頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297 ----------^ --------訂if------ 線, (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印制衣 1259850 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（） 料A司的/儿積處理室時，上述製程參數可在200mm的基 材上提供每分鐘約1 〇 〇 〇 至5 0 〇 〇埃的沉積速率。 其匕〉儿積處理言；fjR it 4- # T在本發明的範圍内，且上述參數可 根據二於形成碳切層的特定沉積處理室而加以調整。舉 例而言’其它沉積處理室的容積以及所需的氣體流速可能 大於或小於在此描述之應用材料公司的沉積處理室，並且 可配置容納300 mm的基材。 儿積過後的石反化矽層的介電常數小於約4 · $，因而適 於做為積體電路中的絕緣材料。碳切層的介電常數可加 以:正，因為此介電常數可為混頻rf電源之比率的函數 現其夂化具而吕’當低頻RF功率與總混頻rf功率 的比率下降時，沉積後之碳切層的介電常數也會降低。 >成膜層的過私中，碳化碎層之介電常數亦可為氣 f混合物之成分的函數而加以調整。當氣體混合物中的碳 展度曰加時’ /儿積後之碳化矽層的碳含量亦同時增加，而 $介電常數則降低。此外，隨著沉積後之碳切層的碳含 量的增加，其疏水特性亦增加，使得此種膜層適於做為積 體電路中的水氣阻障層。 此外，沉積後之碳化碎層的氧氣含量低#工％。吾人 相仏此種氧氣含量可減少金屬擴散，並改善碳化矽膜層 的阻障層特性。例如，沉積後之碳化碎層的電流阻擔能力 約為1MV/Cm(百萬伏特/公分），其小於ΐχΐ〇·9安培/平方公 分，因而其適用於減少積體電路之内連線結構之間的干 擾。 第13頁 --------^ij------- (請先閱讀背面之注意事項再填寫本頁) 1259850 A7 B7 五、發明說明（ 經濟部智慧財產局員工消費合作社印製 在波長約低於250 nm時，碳化矽層的光吸收係數（Λ ) 约介於至0.7之間，使其適於做為DUV波長的抗反射 塗層（ARC)。在形成膜層的過程中，碳化砍層的吸收係數 可為沉積溫度和氣體混合物之碳含量的函數而隨其變 化。具體而言，當沉積溫度增加時，沉積後之碳化矽層的 吸收係數㈣時增加。此外，當沉積後之碳切層的碳含 量增加時’其吸收係數亦同樣會增加。 積體電路的製造過程 A·碳化矽硬罩幕 第2a圖至第2e圖概略繪示基材2〇〇在積體電路製 之不同階段的截面圖中碳化珍係做為硬罩幕。概括 言’基材200可代表任何進行處理的工件，而基材結構2別 則概括代表基材以及形成於基材2〇〇上方的其它材料層 基材則可能對應硬晶圓或其它已經形成於珍晶圓上二 料層’並取決於製程的特定階段而定。例如，第h圖 示基材結構250的截面圖，其上具有以習知方法形成的 料層2〇2。材料層202可能是氧化層（例如二氧切或氟 璃）。概括而t ’基材200可包含珍層 '妙化物層、金 層或其Έ材料層。第2a圖繪示一種實施例，其中基材 矽層，且其上方形成有二氧化矽層。 土 第2b圖繪示形成於第2a圖所示之基材結構25〇上 的碳化碎| 204。碳化參層2〇4係依照上述製程參數而 成於基材結構250之上。此碳化秒層的厚度係隨著特 第14頁 本纸張尺度適用中國國家標準（CNS)A4 ^¥7^10 x 297公f ) 造 而 材 材 玻 屬 為 方 形 定製 --------訂丨^-------^^^^1 (請先閱讀背面之注意事項再填寫本頁) 1259850 A7 B7 五、發明說明（ 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 程階段而改變。在典型情況下，碳化矽層的沉積厚度約5〇 埃至1000埃。 一層能量敏感性光阻材料208形成於碳化矽層204 上。該層能量敏感性光阻材料208可被旋塗於基材上，其 厚度約介於4,000埃至10,000埃。大部分的能量敏感性光 阻材料容易受到波長小於約45〇奈米之紫外輻射的影響； 而深紫外線（DUV)光阻材料則容易受到波長小於約245奈 米之紫外輻射的影響。 中介層206係形成於碳化矽層2〇4的上方，其取決於 製程當中所使用的能量敏感性光阻材料之蝕刻化學成 而足。當能量敏感性光阻材料208及碳化層204可利用 同的化學蝕刻劑進行蝕刻時，中介層2〇6即可當作碳化。 204的罩幕。中介層2〇6係以習知方式形成於碳化層 之上。中介層206可為碳化矽蓋層、氧化物、氮化物、 氧矽化物、非結晶矽或其它合適材料。 將一層能量敏感性光阻材料2 〇 8經由罩幕2 1 〇暴露 紫外輻射，即可將圖案影像引導至該層能量敏感性光阻 料208。如第2c圖所示，被引導至該層能量敏感性光阻 料208的圖案影像在適當的顯影劑當中進行顯影，以界 出其中的圖案。然後，請參照第2 d圖，界定於能量敏 性光阻材料208中的圖案轉移通過碳化矽層2〇4。該圖 係利用能量敏感性光阻材料2〇8當作罩幕而被轉移通過 化矽層204。該圖案係利用適當的化學蝕刻劑而被轉移 通過杈化矽層204。舉例而言，四氟化碳或含有三氟甲 第15頁 本紙張尺度適用中國國家標準（cns)A4規格（2〗〇 X 297公釐） 分 相 層 氮 於 材 材 定 感 案 石炭 至 ^ --------訂-----------線 (請先閱讀背面之注意事項再填寫本頁) 1259850 A7 B7 五、發明說明（) 和氧氣之氣體混合物等可用於化學性蝕刻碳化矽層2〇4。 在另一種情況下，當中介層206存在時，首先利用該 (請先閱讀背面之注意事項再填寫本頁) 能量敏感性光阻材料2〇8做為罩幕，將界定於能量敏感性 光阻材料208中的圖案轉移通過中介層206。然後，利用 中介層206做為罩幕而將圖案轉移通過碳化矽層204。圖 案係利用適當的蚀刻劑而被轉移通過中介層2 〇 6及碳化秒 層 204。 第2e圖繪示製程完成之後的積體電路，此製程係利 用碳化碎層204做為硬罩幕，而將界定於碳化矽層2〇4中 的圖案轉移通過二氧化矽層202。 當二氧化矽層202經過圖案化之後，碳化矽層204可 選擇性地藉由利用適當的蝕刻劑進行蝕刻而從基材上被 移除。 B ·包含碳化矽層之鑲嵌結構 經濟部智慧財產局員工消費合作社印製 第3a圖至第3d圖概略繪示基材300在製造鑲嵌結構 之不同階段的截面圖，其中包含碳化矽層。鑲嵌結構通常 用於形成積體電路上的多層金屬内連線。隨著製程階段的 不同，基材300可能對應已經形成於基材3〇〇上的矽晶圓 或其它材料層。例如，第3a圖繪示基材300，其上已形成 第一介電層302。第一介電層302可為氧化層（例如二氧化 矽、有機矽烷化合物、氟玻璃（FSG)、摻雜碳之FSG等）。 概括而言，基材可包含一層矽、矽化物、金屬或其它材料。 第3a圖繪示一實施例，其中基材3〇〇為矽，其上形 第16頁 本紙張尺度翻中國國家標準（CNS)A4規格⑵0 X 297公f 7 1259850
經濟部智慧財產局員工消費合作社印製 五、發明說明（） 有氣破璃層。第一介電層的厚度約5,000埃至10,000 埃’並取決於所製造的結構大小而定。 %化秒層3 0 4係形成於第一介電層3 〇 2之上。碳化矽 層304係按照以上所描述之製程參數而形成於第一介電層 3〇2炙上。碳化矽層304之介電常數小於約4.5，因而能夠 避免或減少形成於鑲嵌結構内之金屬内連線之間的電容 耦合。碳化矽層的介電常數可以調整，因為介電常數可為 开y成膜層過程中的氣體混合物成分以及施加電場之功率 比值的函數而在所想要的範圍内改變。 碳化碎層304的厚度係隨著製程的特定階段而改變。 在典型情況下，碳化矽層304的厚度約200埃至1〇〇〇埃。 叫參照第3b圖，碳化矽層304被圖案化及蝕刻，以 界疋出接觸孔/介層孔開口 3 〇6，並在介層孔被形成的區域 内暴露出第一介電層302。碳化矽層3〇4係利用參照第 2 d圖所描述之習知微影技術而加以圖案化。碳化矽層 可利用四氟化碳（CF4)或含有三氟甲燒和氧氣的氣 月豆匕5物進行I虫刻。當碳化碎層3 〇 4被圖案化之後，第二 ’I甩層308被沉積在其上方。第二介電層3〇8可為氧化物 (例如二氧化矽或氟玻璃（FSG))。第二介電層3〇8的厚度約 5,〇〇〇 埃至 1〇,〇〇〇 埃。 接著如第3c圖所不，第二介電層308被圖案化界 疋内連、、泉3 1 〇 ’且最好利用上述習知的微影製程來進行。 形成於第二介電層308的内連線31〇係位於碳化珍層304 中之接觸孔/介層孔開口 3Q6的上方。然後利用反應性離子 (請先閱讀背面之注意事項再填寫本頁) 訂-----------線康 1259850 A7 -—^ ___B7_ ' ---------- 五、發明說明（） 1虫刻或其它非均向性蝕刻技術來蝕刻内連線3 1 〇及接觸孔 /介層孔3 0 6。 請參照第3d圖，内連線310及接觸孔/介層孔3〇6係 以如銘、鋼、鎢或其組合等導電材料3 14加以充填。在較 佳情況下’内連線3 1 0及接觸孔/介層孔306所充填的材料 為銅’因為銅的電阻較小（約1·7// Ω -cm)。導電材料314 係利用化學氣相沉積（CVD)、物理氣相沉積（PVD)、電錄戍 其組合進行沉積，藉以形成鑲嵌結構。此外，阻障層3丨6(例 如叙、氮化叙或其它合適的阻障層材料）首先被均勻地沉 積在内連線3 1 〇及接觸孔/介層孔306的側壁上，以防止金 屬遷移到周圍的介電層302、308以及碳化矽層3〇4。 C.碳化矽抗反射塗層（ARC) 第4a-4e圖描繪基材400在積體電路製造之不同階段 的截面圖，其中該結構係以碳化矽做為抗反射塗層 (ARC)。概括而言，基材4〇〇可代表任何進行處理膜層的 工件’而基材結構450則概括代表基材以及形成於基材 400上方的其它材料層。基材4〇〇可能對應矽晶圓或其它 已經形成於矽晶圓上的材料層，並取決於製程的特定階段 而定。例如，第4a圖繪示基材結構450的截面圖，其中 基材400為矽晶圓。 碳化矽層402係形成於基材結構450之上方。此碳化 碎層402係依照上述製程參數而形成於基材結構45〇之上 方。此碳化矽層在波長小於約250 nm時，其吸收係數（κ、 (請先閱讀背面之注意事項再填寫本頁) -ϋ -H ϋ -ϋ i«i 11^OJ n ϋ ·1 4ΦΙ 經濟部智慧財產局員工消費合作社印製 第18頁
1259850 A7 B7 五、發明說明（ 經濟部智慧財產局員工消費合作社印製 約在0.1 i 0.7之間，I其適於在紫外線波長之下做為抗 反射塗層(ARC)。石炭化矽層的吸收係數可加以調整，因為 在碳化矽的形成過程中，吸收係數可為沉積溫度和氣體混 合物中之碳濃度的函數而隨著所想要的範圍改變。碳化矽 層402的厚度係隨著特定製程階段而改變。在典型情況 下，此碳化矽層的沉積厚度約2〇〇埃至2〇〇〇埃。 第4b圖繪示一層能量敏感性光阻材料4〇4形成於 4a圖所示之基材結構45〇的上方。該層能量敏感性光阻 料可被旋塗於基材結構450之上，其厚度約介於2,〇〇〇 至6,000埃。此能量敏感性光阻材料容易受到波長小於 2 5 0奈米之深紫外輻射的影響。 將此層能量敏感性光阻材料4〇4經由罩幕4〇6暴露 深紫外輕射，即可將圖案影像引導至該層能量敏感性光 材料404。當圖案的影像被引導至該層能量敏感性光阻1 料404之後，碳化矽層402會抑制任何來自下方材料層（例 如氧化物或金屬）的反射，如此將會降低被引導至該層 量敏感性光阻材料404之圖案影像的品質。 如第4c圖所示，被引導至該層能量敏感性光阻材 404的圖案影像係在適當的顯影劑當中進行顯影，以界 出其中的圖案。然後，請參照第4d圖，界定於能量敏 性光阻材料404中的圖案轉移通過碳化矽層402。該圖 係利用能量敏感性光阻材料404當作罩幕而被轉移通過 化矽層402。該圖案係利用適當的化學蝕刻劑（例如四 碳或含有三氟甲烷（CHF3)和氧氣之氣體混合物）而被 第19頁 本紙張尺度適用中國國家標準（cns)a4規格（210 X 297公t ) 第 材 埃 於 阻 材 能 料 定 感 案 碳 氟化 轉移 (請先閱讀背面之注意事項再填寫本頁) --------訂-----------線4 1259850 A7 ----- —__B7___ 五、發明說明（） 至通過碳化矽層402。 如第4e圖所示，當碳化矽層4〇2經過圖案化之後， 此圖案通常會被轉移至基材4〇〇。該圖案係以碳化矽arC 層402當作硬罩幕而被轉移至基材400。該圖案係利用適 當的化學姓刻劑進行蚀刻而被轉移至基材4〇〇。然後，石户 化石夕層402可選擇性地利用適當的化學蝕刻劑（例 x四^ 化破或含有三氟甲烷和氧氣之氣體混合物）進行蝕 刈而從 基材4 5 0上被移除。 雖然以上已詳細說明本發明之多種較佳實施例， 凡熟 習該項技藝者當可利用在此揭露之教示設計其它i 施例。 (請先閱讀背面之、注意事項再填寫本頁)
經濟部智慧財產局員工消費合作社印製 第20頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）

Claims (1)

1259850 申請曰期 Λ 广 J 0 .心〆 案 號 f/ 類 别 (以上各攔由本局填註）
_11專利説明書 中 文 碳化矽層之雙頻電漿激發化學氣相沉積 發明 名稱 英 文 姓 名 國 籍 1. 史林尼法斯奈馬尼 2. 夏立群 3. 艾立耶和 1.印度2.中華人民共和國3.美國 裝 發明 人 住、居所 1. 美國加州聖荷西市懷特教柏大街494號 2. 美國加州聖大克勞拉市雷絲大街868號 3. 美國加州聖荷西市匹斯脫亞路5 8 8 8號 訂 姓 名 (名稱） 美商·應用材料股份有限公司 線 經濟部智慧財4笱員工消費合作社印製 國 籍 美國 三、申請人 住、居所 (事務所） 代表人 姓 名 美國加州聖大克勞拉市波爾斯大道3050號 瓊西J.史維尼 第1頁 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 1259850 {由本局填寫)
本案已向： A6 B6 國（地區）申請專利 / 叫日期· 案號： ，^有□無主張優先權 本案已向美國申請專 月号不J，申凊日：2000年9月12日案號：09/660, 268號 有關微生物已寄存於： 寄存日期： 寄存號碼. (請先閱讀背面之注意事項再填寫本頁各攔) I - I -I I - i - - —i * —i— ϋη ( HI I - - 經濟部智慧財產局員工消費合作社印製 苜 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 象——L_U---------
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