TWI259217B - High dielectric constant metal silicates formed by controlled metal-surface reactions - Google Patents

High dielectric constant metal silicates formed by controlled metal-surface reactions Download PDF

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Publication number
TWI259217B
TWI259217B TW090117816A TW90117816A TWI259217B TW I259217 B TWI259217 B TW I259217B TW 090117816 A TW090117816 A TW 090117816A TW 90117816 A TW90117816 A TW 90117816A TW I259217 B TWI259217 B TW I259217B
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Taiwan
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metal
insulating layer
semiconductor substrate
containing compound
substrate
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TW090117816A
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Gregory N Parsons
James J Chambers
M Jason Kelly
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North Carolina State Unviversi
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    • H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

1259217 A7 B7 五、發明説明（1 ) 相關申請案之交叉參考 本申請案主張7/20/2000申請之臨時申請案第60/220463號 之優先權，該揭示在此提出供參考。 發明領域 本發明一般係關於半導體基材上之絕緣層，及形成該絕 緣層之方法，及包含該絕緣層之微電子裝置。 發明背景 形成先進互補之金屬氧化物半導體（CMOS )裝置持續的受 到矚目。一般相信該裝置可能需要高介電常數（高-k)柙極 絕緣層，以維持足夠之電容，同時使隧道效應最小。高_ k 材料之物理蒸氣沉積（PVD)及化學蒸氣沉積（CVD)經常會 得到低-k之介面層，其相信係由於與碎基材不期望之反應 導致。例如鍵K. A. Son 等人之 J· Vac. Sci. Technol. A 16, 1670-1675 (1998)，Β· H. Lee 等人之 Appl. Phys. Lett· 76, 1926 (2000) ? G. B. Alers A Appl. Phys. Lett. 73. 1517-1519 (1998)，S. K. Kang 等人之 Thin. Sol. Film 363，8-11 (1999)及 T. M. Klein 等人之 Appl. Phys. Lett. 76, 4001-4003 (19 9 9 )。此等反應相信係由沉積之未平衡性質造成。金屬 有機源在透明矽（Si)上之高-K CVD —般包含使金屬配位鍵 斷裂，金屬錯合物之化學吸收，形成例如金屬-矽、矽-碳、矽-氫氧化物、等，接著氧化。 先前之努力未達理想下，該技藝中仍需要可用於現先進 之電子裝置中，而不會明顯的增加電流洩漏或經由相對應 之閘極堆疊隧道作用之高介電常數金屬矽酸鹽絕緣層。 -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 1259217 A7
登明概要 本發明之_目的伤 、、、 、 7你挺供一種在半導體基材上形成絕緣層 =方法邊方法包括以金屬或含金屬之化合物及氧將半導 to基材表面改^ ’在半導體基材之表面上形成絕緣層，其 中d緣層包括金屬或含金屬之化合物、氧及矽，使得絕 、、彖層《介電常數大於由二氧化矽形成之絕緣層，且其中之 絕緣層包括金屬·氧_矽鍵。 本發明心另一目的係提供一種包括矽之半導體基材，及 在半導體基材表面上形成之絕緣層之表面改質半導體基 1。該絕緣層包括金屬或含金屬之化合物、氧及矽，使得 絶緣層之介電常數大於由二氧化矽形成之絕緣層，且該絕 緣層亦包括金屬-氧-矽鍵。 本發明之另一目的係提供一種包括上述表面改質之半導 體基材之微電子裝置。 本發明之此等及其他目的及優點在本文中會更詳細的說 明。 世圖之簡要敍述 圖1說明依據本發明之用於濺射金屬且進行退火之系統之 具體例。 圖2說明依據本發明製造之各種薄膜之電容對電壓（c-V) 曲線。 圖3說明A/Y-O-Si/η-及p-類電容器之MHz C-V曲線。 圖4a及4b說明基材上之矽表面預處理之Si 2p及n Is光 -5- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 1259217
五、發明説明（3 圖5a至5c說明在各基材上形成之矽酸釔膜之χρ光譜之γ 3d、Si 2p 及 〇 is 區。 圖6a至6c过明各薄膜之γ刊、y邛及〇 is光譜。 之詳細敘述 本發明將參考包含（但不限）附圖所述具體例之本文所述 下M U詳細的說明。但應了解此等具體例僅用於說明 本發明’並未用於限制本發明之範圍。 、本發明 < 一目的係提供一種在半導體基材上形成絕緣層 之万法。該方法包括以金屬或含金屬之化合物及氧 體基材表面改質，在丰壤 为 在牛導體基材之表面上形成絕緣層。該 、、巴、彖層包括金屬或含金屬之化合物、氧及石夕，使得絕緣層 、丨私^數大於由一氧化矽形成之具有例如類似厚度之絕 緣層。絕緣層中含有金屬_氧_矽鍵。 、 本發明所用切半㈣基材可包含各種材料 矽、碳化矽、砷化鉸、备办Α V丨4 I艮） ^ 虱化鎵、及其結合物。該基材之選 擇為熟習本技藝者已知。 、 金屬之任一種性質均可用於本發明之 例包含（但不限）釔、鑭、钪、杜从麻 n氣 ^ 釔、給、铯、鋁及其|士人 物。含金屬之化合物可句入办、 、、口 口 物了包3例如本又所列金屬之合金及Λ 化物。合金包含（但；^ ^ - ）任一種上述金屬之銘酸鹽。亦i 使用任一種上述金屬之今屬畜 、 屬至屬虱化物。列舉之金屬氧化物包
r 但不限）Y202、Ta205、Hf02、及抓 Z 其結合物。 2 3以及 絕 本發明之絕緣層可製備成各種厚度。其-具體例中 -6- 1259217
緣層之厚度較好在約5埃至約丨〇〇埃之間。 較好’本發明之絕緣層相對於二氧化矽形成之層具有改 善之介電常數。其一較佳具體例中，、 ]中、、，巴、、彖層芡介電常數相 ί於未U至屬或含金屬化合物之絕緣層，亦即叫絕緣 層’其因子至少大3。更好’絕緣層之介電常數之因子比厚 度與本發明〈絕緣層類似，但不含金屬或含金屬化合物之 Si02絕緣層大約3、4或5至約7、8、9或1〇。再者，較佳 具體例中，本發明之絕緣層相對於叫絕緣層之缺陷較 低。較佳具體例中，絕緣層之缺陷密度少於1〇12缺陷 ’em2。更好之具體例中，絕緣層之缺陷密度低於ι〇ιι缺陷 /cm2 由審慎的選擇各成分之量可達到纟發明絕緣 層之效益。依其一較佳具體例，該絕緣層包括約2、“或 20至約25、30或40原子％之金屬，約4〇、45或5〇至約 55、60或65原子％之氧，及約或超過〇、5、1〇或15至約 2〇、25、30或33原子％之矽。另外，一較佳具體例，該絕 緣層之洩漏電流比類似厚度之Si〇2層低。如實例般，洩漏 電泥之降低因子較好至少為2，且夠好其降低因子在2、 10、100 或 500 至約 600、800 或 1000 之間。 本發明之方法可使用技藝中已知之設備，依許多具體例 進行。依其一具體例，本發明之改良步驟包含在半導體基 材上形成絕緣層；使半導體基材及絕緣層進行足夠之處 理’使金屬或含金屬之化合物與絕緣層反應，改良絕緣層 增加介電常數。較好，使半導體基才進行充分之處理，使 金屬或含金屬之化合物形成絕緣層包含使半導體基材進行
本紙張尺度適财_家標準(CNS) A4規格(21Qχ 297公董) 1259217 A7 B7 五、發明説明（5 ) 選自真空退火、氧化環境中退火、及合併真空/氧化環境退 火，形成絕緣層。另一具體例中，改良之步驟包含藉由化 學蒸氣沉積或反應性原子層化學蒸氣沉積，沉積至少一金 屬或含金屬之化合物。 依其一較佳具體例，本發明之改良步驟包含使半導體基 材表面氧化，於其上形成二氧化矽層，接著在半導體基材 之表面上沉積至少一基金屬或含金屬之化合物，於其上形 成層狀；接著使半導體基材退火，改良半導體基材之表 面。較好，在氧化步驟之前，可藉由使用接受之技術清洗 半導體基材之表面。 氧化步驟可使用熟習本技藝者已知之各種技術進行。較 好，氧化為電漿氧化。列舉之氧源包含（但不限）氧原子、 氧離子、暫安定之氧、氧分子離子、暫安定之氧分子、化 合氧分子離子、暫安定之化合氧、化合氧游離基、及其混 合物。可用之化合物原為（但不限）0 2、N 2 0、及其混合 物。氧化較佳之條件為溫度在約2 5 °C至約900 °C，且壓力 在約1 0 _ 3 torr至約760 torr之間。通常，較好其處理條件為 可得到之氧化厚度約2至1 5埃者。 金屬或含金屬化合物之沉積可依據許多技術進行。較佳 具體例中，金屬化含金屬之化合物係藉由使用化學蒸氣沉 積法或電漿化學蒸氣沉積法，沉積在半導體基材之表面 上。此等方法特定之實例包含（但不限）雷射協助之化學蒸 氣沉積、直接或遙控之電漿協助化學蒸氣沉積、電子粒子 迴旋加速器共振化學蒸氣沉積。此等方法之實例敘述於 -8- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 1259217 A7 ----——__B7 五、發明説明（6 ^ — _一 — ------ 申請之系列編號第〇9/434,607號中，該揭示在此 =參考。較好，金屬或含金屬之沉積步驟係在溫度約 土 800 C，且壓力在約丨〇-3 t〇rr至約⑺打下進行。 通常’較好該加工條件可得到之氧化厚度約2至15埃。 、^述具體例中所用之退火步驟可使用熟習本技藝者已知 之:備進行。較好该退火步驟係使半導體基材曝露在惰性 ，、袤克（例—如N2、Ar、H、及/或適度之真空）中，且較好 為含氮之氣體。較好，退火係發生在溫度約6〇〇。(：至約ιι〇〇 C且壓力在約1 〇_6 torr至約760 torr下約1秒至約1 〇分 鐘。 另一具體例中，氧化步驟可以以使半導體基材曝露在使 用電漿之含氮氣體（例如中，因而於其上形成含氮之薄 膜’且較好為單層形式之步驟取代。該步驟較佳之條件係 發生在溫度約25t至約900 °C，壓力約ΙΟ·3 torr至約760 torr之下。較好，基材上形成n2之單層膜。隨後，使含金 屬之化合物（此具體例中為金屬氧化物）沉積在含氮之膜 上’形成層，且使基材如上述般退火。該半導體基材之矽 相信會擴散經過氮層，且在層中與金屬及氧反應，在絕緣 層中形成金屬-氧-梦鍵。 本發明之另一目的係提供一種表面改質之半導體基材。 表面改質之半導體基材包括在半導體基材表面上形成之矽 及絕緣層。該絕緣層包括金屬或含金屬之化合物、氧、及 矽，使得絕緣層之介電常數大於不含金屬或含金屬化合物 之二氧化矽形成之絕緣層。該絕緣層包括金屬-氧-矽键。 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 1259217 A7
本目的中敘述之半導體基材及絕緣層可包括（但不限）本文 所列之所有具體例。本發明之另一目的包含包括表面改質 之半導體基材之微電子裝置。列舉之包括表面改質之半導 體基材之微電子裝置包含（但不限）薄膜電晶體、互補之金 屬氧化物半導體（CM0S)閘極電器裝置、記憶裝置、尾端積 體電路(IC)應用’分子電子裝置、及有機電子裝置。另」 舉體例中，為電子裝置可包含元素與半導體基材之電子或 物理偶合。通常，表面改質之半導體基材可用於為電子裝 置中且v亥裝置需使用具有相對於二氧化矽具有較高介電 常數介面之基材。 本發明將參考下列實例更詳細的敘述。應了解此等實例 僅用於說明，纟非用隸制本發明中請專利範圍中定義之 範圍。 此等實例中，金屬膜（例如此卜般係以如圖i中說明之包 含滅射標的物、電漿管2及氣體人口 3(例如Ar、N2MN2) 之裝置負荷鎖定及電漿加工室10之二室真空系統㈣。基 %壓力1 X 10 7 torr係使用混合鍋輪及乾燥隔膜泵浦系統， 於負荷鎖定中達成，品由負荷鎖定轉移到瑜加工室中 具有Χ、γ、ζ、及Θ移動之操作裝置中。加工室中之基礎 壓力5X10-W係以混合鍋輪及乾燥滿捲泵浦結合達成， 其重複形成加工氣體泵浦系統。製程壓力可經由含直接位 在混合滿輪之上之機械化23公分緩衝閥及緊鄰加工室中樣 品（電容計之密閉環系統自i控制至1〇〇。加工室裝置其構 _______ —______- 10 - 本紙張尺度適用巾a a f標準(CNS) A4規格(21。X 297公爱厂 ---- 1259217 A7 _ B7 五、發明説明（~-- 造可依遙控電漿模式操作，以進行就地矽表面預處理，及 依直接電漿模式濺射銥（或其他金屬或含金屬之化合物）薄 膜之圓桶電漿源。 圓桶形電漿源含500W、13.56MHz射頻（η，）電力供給，及 及自動調整符合之網路，電漿管5 x i 5·26公分（直徑χ長 度）、及0.95公分公稱直徑銅管之二轉127公分直徑，跨距 5公分，且已不銹鋼靜電套密封之氣冷激發線圈（一端接 地）。Αι;、Ν2及ΝζΟ加工氣體流經由電漿管前端供給到室 中’且以負流控制器至1碉節至1 〇〇 sccin (Ν2)。加工室裝置 可以以柙極閥與系統分離之可收縮金屬或含金屬化合物之 濺射標的。使用電濺射標的提供達到-1〇〇〇V之200w dc電 源及可使基材溫度達到650 °c之600W輕射熱。就地進行後 /儿和真空退火。廷漿加工室亦與就地電漿氧化相容。此等 實例中，氧化係自加工室之外，於標準丨〇公分直徑管爐 中’在500 C至900 C之溫度下，於1 Ν2 Ο或空氣中進 行。 基材為自市售晶圓切割成2·5 X 2·5公分樣品之η-(丨.〇至 2.0Qcm)或ρ-型（0.1至〇.3Qcm)之Si(100)。樣品係在以甲 酸鹽緩衝之以四甲基銨氫氧化物為主之鹼性溶液中浸潰5分 鐘’且以去離子水（DI)洗滌，以緩衝之氟化氫（H F )中蝕刻 3 0秒，最後不洗ίί条，且立即置於真空中。 此等樣品之濺射係在室溫中，於4.3mT Ar及420W之rf電 源中進行。濺射過程中，金屬標的物完全伸入電漿中，且 在約1000V dc下偏壓。在乾之例中，該金屬係經反應，且 -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 1259217 A7 ____________ B7 五、發明説明（9 ) 系統中殘留之氧及水可能影響到標的物表面及濺射速率。 為儘可能的控制該狀態，標的物可在置入樣品前經處理， 且在標準條件下，藉由濺射操作3 〇至6 〇分鐘。此時一般之 標的物電流經觀察自約1 〇降至5 m A，且當電流穩定在約 5 m A下時，標的物視同透明。針對各具體例，樣品係在約 1 · 2 5公分之距離下，自》賤射標的物旋轉入標的物之視線 中〇 為調整金屬（例如釔）之濺射速率，因此將一系列厚度自 200埃至1〇〇〇埃之金屬（例如釔）膜空白的沉積在1〇〇〇埃濕潤 氧化之SiCh上。沉積後，將一半該樣品以光阻劑遮蔽，且 在7 0 C下軟烘烤2分鐘。遮蔽之樣品在於A丨蝕刻劑（磷酸/ 硝酸/乙酸混合物）中蝕刻，以DI水洗滌，且以烘乾。蝕 刻後，光阻以丙酮去除，但亦可使用其他溶劑。樣品再以 DI水洗ί條且以N 2烘乾。薄膜厚度以具α _步驟5 〇 〇之穿過樣 品之五步驟兩度測量’且取其平均值測定。樣品之均勻度 經評估約為8 5 %。以平均厚度對濺射時間作圖，取其斜率 當作、濺射速率。在零處設定之y截斷為極佳（r 2約等於 0.998)。濺射沉積速率約為40埃/分鐘。各操作之金屬（例 如紀）膜厚度係在維持固定之濺射速率下藉由監測鹼射時間 測足。電漿激發及穩定之狀態係使用自動調節一致之網路 達成。一般之薄金屬（約8埃）膜所需之濺射時間為12秒。電 漿啟動快速（低於1秒），且因此未經曝曬而影響其起初之賤 射速率。 此等貫例中之石夕化物膜係藉由在室溫下將金屬（例如I乙） _ - 12- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 1259217 A7 B7 五、發明説明（1〇 ) 濺射到最後為HF之矽上，且於真空終究第退火（最大壓力 约為5 X 1〇·6 torr)。退火步驟之溫度上升係在約〇.5。〇/3下 進行，達到溫度約600 C，，且使樣品在此溫度下維持2 〇 分鐘。退火步騾之過程中，使金屬濺射標的物（例如釔）與 系統分離。退火後，使矽化物膜於真空中冷卻5分鐘，且在 1 atm之N2中在冷卻5分鐘。金屬/矽系統係在具體使用之釔 中形成下列之相：YSiu、YSi0.8、YSi及YSiK6#，且 當釔在矽上退火時會形成YSh μ。例如見γ· K. Lee等人之 j· Alloys Compd· 193 289 (1993)及雙相合金相圖，第 2 冊， Τ· B. Massaiski 編輯（American Society for Metal，Metals
Park，OH 1986)。 氧化係離線於本文所述之爐中，在500艺至9〇〇 之溫度 下進行6至20秒。將樣品置於石英船中，且以手快速（約i 秒）推向爐之中心，且氧化時間為樣品在爐心之時間。使用 N2〇及空氣當作氧化劑。當使ffiN2〇當作氧化劑時，流速 為 5 sim(N2) 〇 評估各種薄膜及樣品性質之X -射線限光電光譜，介質能 離子散射，電測量，復立葉轉換紅外線光譜，原子力顯微 鏡’及傳輸電子顯微鏡均如J· j· Chambers等人之j〇Umal
Appied Physics，90(2)第 918-933 頁（2001 )中所述般進行。 實例1 半導體基材之表面改質 將係半導體基材曝露在電漿N2氣體中，於其上形成薄的 N2層。隨後，使用CVD或電漿CVD製程，在4〇〇°C下將金 -13- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) ' ------- 1259217 A7 B7 五、發明説明（11 ) 屬氧化物沉積在基材表面上。接著使該層SN2中，900它 下退火1 0分鐘。矽經過氮層擴散，且與金屬氧化物反應， 因此於其中形成金屬-氧·矽鍵。 C - V曲線列於圖2中。如所見，該曲線相當於該樣品（標 示（2))主現25埃之EOT ’亦即與裸露§丨之24 ·4埃之EOT相 比，相當於標示（1)之曲線。 實例2 半導體基材之表面改質 重k貝例1之程序。但使基材稀進行電漿氧化取代氮。接 著藉由CVD或電漿CVD法將金屬沉積於其上，且使基材退 火0 C-ν曲線列於圖2中。如所見，該曲線相當於該樣品（標 示（3))呈現37.7埃之EOT，其對於曲線標示〇)有利。 實例3 Υ-Ο-Si膜之電容-電壓（c_v)曲線 广使約8埃之釔在矽上氧化形成Y_〇_Si膜（厚度約4〇埃卜 氧化係在900 °C及1 atm N2 0下進行1 5秒。 在η-型Si基材上形成之薄膜C_v曲線之分析示於圖3中 得到12埃之E0T。可議之可相容薄膜之一般呈現之洩漏 流為0.5埃/cm。因為42埃之厚度約為薄膜經歷類似之 程，因此Y-o-Si膜之k經計算大約為14。平板電壓（Vb) 在-0.74 V下測量，其對於理想之電容器會自期望之v 成-0.68V。 b 實例4 -14- 1259217 A7 B7
γ - 〇 - S i膜之電容·電壓（c - v)曲線 在p-型Si基材上進行實例4之程序，且其c-v曲線列於圖 3中。分析該薄膜之C-V曲線，得到1 1埃之Εοτ。平板電壓 (V b)係在-1 ·63 V下測量，其對於理想之電容器會自期望之 Vb 轉成-0.84V。 實例5 氧化過程中之矽消耗 釔膜氧化過程中消耗之矽係依下列標示4a及4b之具體 例，使用下列預處理揭示··（ 1 )清洗矽，（2 )使矽氧化，（3 ) 使氧化之矽氮化物化，及（4)使矽半化物化。電漿表面處理 之厚度使用矽基材峰值衰減器劑酸為5埃至1〇埃。圖“說 明Si 2p光譜，且圖4b說明釔沉積及氧化前，矽表面預處理 之N Is光譜。Si 2p光譜（圖6a)中之矽基材峰值（99.3eV)對 各預處理清晰可見。對於各電漿處理之表面（圖4 a曲線（2)_ (4 ))，相信在Si 2p光譜中可觀察到高的結合能特性（丨〇2 _ 103eV)’但對於透明之碎表面（圖4 a曲線（1))則否。針對 電漿氧化之矽（圖4a曲線（2))及電漿氧化係接著氮化物化 (圖4 a曲線（3 ))在103_3e V處之特性係指Si02。電漿氮化物 化矽（圖4 a曲線（4 ))表面上102.4eV處之特性係指係與氮之 鍵結。氮化之矽及氮化係層之厚度由S iG特性之衰減器估算 為5埃至1 0埃。若在透明之矽表面（圖4 b曲線（1 ))上觀察到 可偵測之氮，則會變低。電漿氧化矽（圖4 b曲線（2 ))，電聚 氧化接的氮化（圖4 b曲線（3 )與電漿氮化矽（圖4 b曲線（4)) 之N Is光譜均呈現氮之特性接近398eV。電漿氮化之矽相信 -15- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 1259217 A7 B7 五、發明説明（13 ) 含有最多之氮’氮電漿氮化氧化矽預處理之N 1 s特性之面 積比電漿氧化之矽之N 1 s大（約7 0 %)。 實例6 沉積薄膜之元素光譜 圖5 a至5 c說明實例5中曲線（1) - (4)表示之具體例中，釔 >儿和及氧化後γ 3d(圖5a)、si 2p(圖5b)及〇 is(圖5c)光 邊。針對沉積在透明硬上之紀之氧化（圖5 a曲線（1))，γ 3 d 5 / 2峰值係在與γ _ 〇 _ s i膜一致之1 5 $ · 3 e ν下測量。γ 3d5/2奪值位置針對在氧化之矽（圖5a曲線（2))上形成之膜 及氮化之氧化之矽（圖5 a曲線（3 ))測量接近15 8 · 3 eV，但對 於在氮化氧化物上形成之膜，則可能稍轉移到較低之結合 月匕。然而’當妃沉積在氮化之碎上且氧化時（圖5 a曲線 (4)) ’ Y 3d5/2峰值相對於在透明之矽上形成之Y-〇-Si薄膜 之Y 3d配置，經觀察會轉移0.8eV到較低之結合能上。當γ 3 d峰轉移到較低之結合能上時，相信會移向γ2 〇 3之期望高 學位置（156.8eV)，其建議增加Υ-〇_γ之鍵結。碎鍵結在 99.3eV下之特性及在約i〇2eV下之特性係針對各矽表面預 處理形成之薄膜上，於Si 2p光譜（圖5b曲線（1 - 4))上觀 察。在透明之矽（圖5b曲線（1))上形成之薄膜之81 2p光譜 呈現與Υ-Ο-Si膜一致之102.26¥處之高峰。在氧化之珍（圖 5 b曲線（2))及氮化-氧化之矽（圖5 b曲線（3 ))上形成之薄膜 之Si 2p光譜在約102eV處呈現類似之特性。圖5a曲線（2)之 電漿氧化矽之光譜重建在兔5b曲線（2)中供參考用。氮化之 矽（圖5b曲線（4))上形成之薄膜之102.OeV處之特性向著較 -16-
1259217 A7 B7
五、發明説明（U 低惑結合能量轉移〇.2eV，且約50%面積之薄膜在透明之矽 上形成。針對在透明Si0上形成之Y_〇-SUi(圖&曲線（1 測量之在532.〇eV下之〇 1§高峰在本例中之觀察為寬廣之 峰，相信其係由於氧對釔之鍵結及氧對矽之鍵結之作用。 當對在氧化之矽（圖5c曲線（2))、氮化_氧化之矽（圖5c曲線 (3))、及氮化之矽（圖5c曲線（4))上形成之薄膜進行比較 時，會觀察到Ο Is最高峰稍轉移到在透明之矽（圖5c曲線 (1 ))上形成之膜之光譜。然而，觀察此等光譜最主要之声 異為在氮化-氧化矽及氮化矽上形成之薄膜之〇 ls光譜中^ 察係在約530.0eV下之肩。約53〇.〇eV下之肩接近 Y2〇3 (529.5eV)中〇 Is之期望結合能，且顯示薄膜中〇_乂_ Ο键結之增加。 實例7 沉積薄膜之元素光譜 Y 3d、Si 2p及0 Is光譜係分別說明於圖以至以中。此等 光瑨係針對40埃厚之Si〇2及在40埃Si02上之厚度約2 5埃之 紀膜，在真空、600 °C下退火2分鐘測量。 通常’此等圖說明在600 °C下，於真空中退火2分鐘後之 Si〇2上釔膜之xps結果。40埃Si02光譜係用作比較用。於 真2中退火之Si02上釔之γ 3d5/2(圖6 a)、Si_0 Si 2p(圖6b) 及 O Is(圖 6c)高峰為 158·2、103.0 及 53L7ev，與在 600 °C 及900 C下氧化之Si〇2上釔膜之高峰類似。於真空中退火之 石夕上之纪之Si-Ο特性（FWHM = 2.3eV)僅呈現一點點，若存 在si〇2。〇 is高峰由氧鍵結釔及矽形成之寬廣高峰（FWHm -17 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 1259217 A7 B7 五、發明説明（15 ) = 3.1eV)。 此等圖中存在之光譜相信係建議在矽上之釔暴露在氧化 或真空退火條件時，Si02成為Υ-Ο-Si之轉化。 本發明將參考申請專利範圍敘述，其範圍並不受上述之 具體例限制。 元件符號對照表 1 濺射標的物 2 電漿管 3 氣體入口 10 電漿加工室 -18- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)

Claims (1)

1259217 申請專利範圍
A8 B8 C8 D8 ι· 一種在半導體基材上形成絕緣層之方法，該方法包括： 使半導體基材氧化，於其上形成二氧化矽層； 於該氧化步驟後，將至少一今屦劣入入 了芏乂至屬或含金屬之化合物沉 和在半導肖豆基材之表面上；及 •使半導體基材退火，改質半導體基材之表面，在半導 體基材之表面上形成絕緣層’其中之絕緣層包括金屬或 含金屬之化合物、氧及矽，使得絕緣層之介電常數大於 由二氧化矽形成之絕緣層，且其中之絕緣層包括金屬_ 氧-矽鍵。 2.如申請專利範圍第”貝之方法，丨中之+導體基材包括 至少一種選自矽、氮化矽、坤化鎵、氮化鎵及其結合物 之材料。 3 ·如申請專利範圍第丨項之方法，其中之金屬係選自包含 釔、鑭、鲒、鈴、铯、鋁、及其結合物。 4 ·如申請專利範圍第1項之方法，其中之含金屬化合物為 鋁酸鹽之合金。 5 ·如申請專利範圍第1項之方法，其中之含金屬化合物為 包括至少一種選自包含釔、鑭、锆、銓、铯、鋁、及其 結合物之合金。 6 ·如申請專利範圍第1項之方法，其中之含金屬化合物為 金屬氧化物。 7 ·如申請專利範圍第1項之方法，其中絕緣層之缺陷密度 不大於1012原子/ cm2。 8·如申請專利範圍第1項之方法，其中之絕緣層包括2至4 〇 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 8 8 8 A BCD 1259217 六、申請專利範圍 原子％之金屬，4 0至6 6原子％之氧，及超過〇至3 3原子 %之碎。 9 ·如申凊專利範圍第1項之方法，其中絕緣層之介電常數 比未包含金屬或含金屬化合物之絕緣層大至少3個因 子。 1〇·如申請專利範圍第1項之方法，其中絕緣層之厚度在5埃 至100埃之間。 11·如申請專利範圍第1項之方法，其中該改質步驟包括在 半導體基材上形成絕緣層；使半導體基材及絕緣層進行 處理’使金屬或含金屬之化合物與絕緣層反應，將絕緣 層改質，以增加其介電常數。 12·如申請專利範圍第1 i項之方法，其中使半導體基材進行 處理’使得金屬或含金屬之化合物形成絕緣層之步驟包 括使半導體基材進行選自包含於真空中退火、於氧化環 境中退火，及在合併真空/氧化環境中退火，形成絕緣 層。 13·如申請專利範圍第1項之方法，其中該改質步驟包括使 半導體基材進行退火/氧化，形成絕緣層。 14·如申請專利範圍第1項之方法，其中該改質步驟包括藉 由化學蒸氣沉積或反應性原子層化學蒸氣沉積，沉積至 少一種金屬或含金屬之化合物。 15·如申請專利範圍第1 4項之方法，其中使半導體基材氧化 形成二氧化矽層之該步驟為電漿氧化。 16.如申請專利範圍第1 4項之方法，其中少一金屬或含金屬 -2- 本紙張尺度適用中國國豕標準(CNS) A4規格(210X297公复） 1259217
中凊專利範 〈化合物為金屬氧化物，且其中使至少一金屬或含金屬 =化合物沉積在半導體基材表面上知該步驟包括使用化 學蒸氣沉積或電漿化學蒸氣沉積法。 17·如申請專利範圍第i 4项之方法，其中使半導體基材退火 之步驟包括使半導體基材曝露在含氮之基材中。 如申，專利範圍第1項之方法，其中該改質步驟包括·· 使半導體基材暴露在含氮之氣體中，於其上形成含氮 之薄膜； 使土 ^金屬氧化物沉積在含氮薄膜之表面上；及 使半導體基材退火，將半導體基材之表面改質。 19·—種表面改質之半導體基材，包括·· 一半導體基材包括石夕；及 在半導體基材之一經氧化上表面形成之絕緣層，該絕 緣層包括金屬或含金屬之化合物，氧及矽，使得絕緣層 <介電常數大於由二氧化矽形成之絕緣層，且其中之絕 緣層包括金屬-氧_碎鍵。 2〇·如申請專利範圍第19項之基材，其中之半導體基材包括 至少一種選自矽、氮化矽、砷化鎵、氮化鎵及其結合物 之材料。 21.如申請專利範圍第19項之基材，其中之金屬係選自包含 釔、鑭、锆、給、铯、鋁、及其結合物。 22·如申請專利範圍第1 9項之基材，其中之含金屬化合物為 鋁酸鹽之合金。 … 23·如申請專利範圍第19項之基材，其中之含金屬化合物為 1259217 - C8 ____ D8 六、申請專利範圍 包括至少一種選自包含允、鑭、锆、給、铯、鋁、及其 結合物之合金。 24·如申請專利範圍第19項之基材，其中之含金屬化合物為 金屬氧化物。 25·如申請專利範圍第1 9項之基材，其中絕緣層之缺陷密度 不大於1012原子/cm2。 26.如申請專利範圍第1 9項之基材，其中之絕緣層包括2至 40原子％之金屬，40至66原子％之氧，及超過〇至33原 子％之硬。 27·如申請專利範圍第1 9項之基材，其中絕緣層之介電常數 比未包含金屬或含金屬化合物之絕緣層大至少3個因 子。 28. 如申请專利範圍第1 9項之基材，其中絕緣層之厚度在5 埃至100埃之間。 29. —種微電子裝置，包括一表面改質之半導體基材，該表 面改質之半導體基材包括： 一半導體基材包括矽；及 在半導體基材之一經氧化上表面形成之絕緣層，該絕 緣層包括金屬或含金屬之化合物，氧及矽，使得絕緣層 之介電常數大於由二氧化矽形成之絕緣層，且其中之絕 緣層包括金屬-氧-石夕鍵。 30·如申請專利範圍第2 9項之微電子裝置，其中之微電子裝 置係選自包含薄膜電晶體、CMOS匣及電介質裝置、記 憶裝置、分子電子裝置、及有機電子裝置。 -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 8 8 8 8 A BCD 1259217 六、申請專利範圍 31·如申請專利範圍第29項之微電子裝置，其中之微電子裝 置包括與半導體基材元素電子或物理偶合。 32·如申請專利範圍第2 9項之微電子裝置，其中之半導體基 材包括至少一選自包含氮化矽、砷化鎵、氮化鎵及其結 合物之材料。 33·如申請專利範圍第29項之微電子裝置，其中之金屬係選 自包含釔、鑭、結、銓、铯、鋁、及其結合物。 34·如申請專利範圍第29項之微電子裝置，其中之含金屬化 合物為鋁酸鹽之合金。 35.如申請專利範圍第29項之微電子裝置，其中之含金屬化 合物為包括至少一種選自包含氣、鑭、锆、铪、铯、 銘、及其結合物之合金。 36·如申請專利範圍第29項之微電子裝置，其中之含金屬化 合物為金屬氧化物。 37·如申請專利範圍第29項之微電子裝置，其中絕緣層之缺 陷密度不大於1〇12原子/ cm2。 38.如申請專利範圍第29項之微電子裝置，其中之絕緣層包 括2至40原子％之金屬，40至66原子％之氧，及超過〇至 3 3原子％之石夕。 39·如申請專利範圍第2 9項之微電子裝置，其中絕緣層之介 電常數比未包含金屬或含金屬化合物之絕緣層大至少3 個因子。 40.如申請專利範圍第2 9項之微電子裝置，其中絕緣層之厚 度在5埃至1 〇 〇埃之間。 -5- 本紙張尺度適用中國國家標準(CNS) A4規格(210 x 297公釐)
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