TWI256108B - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
TWI256108B
TWI256108B TW093121152A TW93121152A TWI256108B TW I256108 B TWI256108 B TW I256108B TW 093121152 A TW093121152 A TW 093121152A TW 93121152 A TW93121152 A TW 93121152A TW I256108 B TWI256108 B TW I256108B
Authority
TW
Taiwan
Prior art keywords
oxide film
region
voltage device
high voltage
forming
Prior art date
Application number
TW093121152A
Other languages
English (en)
Other versions
TW200524091A (en
Inventor
Seung-Cheol Lee
Sang-Wook Park
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200524091A publication Critical patent/TW200524091A/zh
Application granted granted Critical
Publication of TWI256108B publication Critical patent/TWI256108B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Element Separation (AREA)
  • Weting (AREA)
TW093121152A 2004-01-09 2004-07-15 Method for manufacturing semiconductor device TWI256108B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-2004-0001656A KR100533772B1 (ko) 2004-01-09 2004-01-09 반도체 소자의 제조 방법

Publications (2)

Publication Number Publication Date
TW200524091A TW200524091A (en) 2005-07-16
TWI256108B true TWI256108B (en) 2006-06-01

Family

ID=34738016

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093121152A TWI256108B (en) 2004-01-09 2004-07-15 Method for manufacturing semiconductor device

Country Status (4)

Country Link
US (1) US7067389B2 (zh)
JP (1) JP4843205B2 (zh)
KR (1) KR100533772B1 (zh)
TW (1) TWI256108B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100676599B1 (ko) * 2005-02-28 2007-01-30 주식회사 하이닉스반도체 플래쉬 메모리 소자의 제조방법
KR100647001B1 (ko) * 2005-03-09 2006-11-23 주식회사 하이닉스반도체 플래쉬 메모리 소자의 플로팅 게이트 전극 형성방법
JP2007180482A (ja) * 2005-12-28 2007-07-12 Hynix Semiconductor Inc フラッシュメモリ素子の製造方法
US20070281403A1 (en) * 2006-06-01 2007-12-06 Mon-Chin Tsai Method of enhancing gate lithography performance by polysilicon chemical-mechanical polishing
KR100849362B1 (ko) * 2006-07-12 2008-07-29 동부일렉트로닉스 주식회사 플래시 메모리 및 그 제조 방법
US20080237740A1 (en) * 2007-03-29 2008-10-02 United Microelectronics Corp. Semiconductor device and the manufacturing method thereof
JP2010183003A (ja) * 2009-02-09 2010-08-19 Renesas Electronics Corp 半導体装置の製造方法および半導体装置
TWI818928B (zh) * 2018-11-02 2023-10-21 聯華電子股份有限公司 一種製作半導體元件的方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100243302B1 (ko) * 1997-12-05 2000-03-02 윤종용 반도체장치의 트렌치 소자분리 방법
KR100350055B1 (ko) * 1999-12-24 2002-08-24 삼성전자 주식회사 다중 게이트 절연막을 갖는 반도체소자 및 그 제조방법
JP3621321B2 (ja) * 2000-01-17 2005-02-16 Ｎｅｃエレクトロニクス株式会社 半導体装置とその製造方法
US6465306B1 (en) * 2000-11-28 2002-10-15 Advanced Micro Devices, Inc. Simultaneous formation of charge storage and bitline to wordline isolation
KR100364600B1 (ko) * 2001-02-12 2002-12-16 삼성전자 주식회사 반도체 소자 제조방법

Also Published As

Publication number Publication date
US7067389B2 (en) 2006-06-27
TW200524091A (en) 2005-07-16
KR100533772B1 (ko) 2005-12-06
US20050153520A1 (en) 2005-07-14
KR20050073301A (ko) 2005-07-13
JP4843205B2 (ja) 2011-12-21
JP2005197652A (ja) 2005-07-21

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees