TWI255561B - Manufacturing process for chip package without core - Google Patents

Manufacturing process for chip package without core Download PDF

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Publication number
TWI255561B
TWI255561B TW094124656A TW94124656A TWI255561B TW I255561 B TWI255561 B TW I255561B TW 094124656 A TW094124656 A TW 094124656A TW 94124656 A TW94124656 A TW 94124656A TW I255561 B TWI255561 B TW I255561B
Authority
TW
Taiwan
Prior art keywords
layer
wafer
patterned
opening
film
Prior art date
Application number
TW094124656A
Other languages
English (en)
Other versions
TW200705682A (en
Inventor
Yu-Tang Pan
Geng-Shin Shen
Chun-Hung Lin
Original Assignee
Chipmos Technologies Inc
Chipmos Technologies Bermuda
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipmos Technologies Inc, Chipmos Technologies Bermuda filed Critical Chipmos Technologies Inc
Priority to TW094124656A priority Critical patent/TWI255561B/zh
Priority to US11/326,749 priority patent/US7560306B2/en
Application granted granted Critical
Publication of TWI255561B publication Critical patent/TWI255561B/zh
Publication of TW200705682A publication Critical patent/TW200705682A/zh
Priority to US12/270,655 priority patent/US7795079B2/en
Priority to US12/270,574 priority patent/US7851262B2/en
Priority to US12/270,642 priority patent/US20090068797A1/en
Priority to US12/270,602 priority patent/US7851270B2/en
Priority to US12/270,679 priority patent/US7803667B2/en
Priority to US12/270,666 priority patent/US7803666B2/en
Priority to US12/270,627 priority patent/US7790514B2/en

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)

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1255561 16667twf.doc/m 九、發明說明： 【發明所屬之技術領域】 本發明是有關於— 於一種薄化晶片封裝體 【先前技術】 種晶片封裝體製程，且特別是有關 之厚度的晶片封裝體製程。
所f現今的資訊社會中，使用者均是追求高速度、高品 貝、夕工&㈣電子產品。就產品外觀而[電子產 設計f朝向輕、薄、短、小__進。為了_上述目 的〜Λ司在進行電路設計時，均融人系統化的概念， 使仔單顆晶片可以具備有多種功能，以節省配置在電子產 品中的晶片數目。料’就電子封裝技術而言，為了配合 輕、薄、短、小的設計趨勢，亦發展出多晶片模組（ m〇dUle，MCM)的封裝設計概念、晶片尺寸構裝（chip scale package，CSP)的雜設計概念及堆疊财以封裝設計 的概念等。以下就分別針對幾_知堆疊型晶片封裝結構 進行說明。 圖1繪示習知堆疊型晶片封裝結構的剖面示意圖。請 參考圖1，習知的堆疊型晶片封裝結構50包括一封裝基板 (package substrate ) 1 〇〇 與多個晶片封裝體 2⑻a、2〇〇b， 其中這些晶片封裝體200a、200b堆疊於電路基板10〇上， 亚與電路基板100電性連接。每一晶片封裝體200a、200b ^括封裝基板210、晶片220、多個凸塊（bump) 23〇、底 膠（under fill) 240與多個焊球250。晶片220與這些凸塊 230配置於封裝基板21〇上，而這些凸塊23〇配置於晶片 Ι25551·_ 220與封裝基板210之間，且晶片220經由這些凸塊電性 連接至封裝基板210。底膠240配置於晶片220與封裝基 板210之間，以包覆這些凸塊23〇。 封裝基板210具有多個導電柱212與多個焊墊214， 其中這些導電柱212分別貫穿封裝基板21〇，且這些焊墊 214分別配置於這些導電柱212上。此外，這些焊球25〇 ’ 配置於這些焊墊214上。如此一來，晶片封裝體200a與 φ 200b便旎夠經由焊球250彼此電性連接，而晶片封裝體 200b經由焊球250電性連接至電路基板丨⑻。 ” 一般而言，封裝基板210的製作方式通常是以核心介 電層（core)作為蕊材，並利用全加成法（历办
Pr〇CeSS )、半加成法（semi-additive process )、減成法 jsubtractive process)或其他方式，將圖案化線路層與圖 . 案化介電層交錯堆疊於核心介電層上。如此一來核心介電 '層在縣基板210的整體厚度上便會佔著相當大的比例。 _ 有效地縮減核心介電層的厚度，勢必會使晶片 _ 封衣=2〇〇a與鳩於厚度縮減上產生極大的障礙。 — 而2 旦晶片封裝體200a與2〇〇b在厚度的縮減方 -有碩’堆疊型晶片封裝結構％的整體厚度便難以 :===*她片封裝結構5。的封裝積 【發明内容】 本發明的目的就是在提供—種晶片封裝體製程，以減 7 1255561 16667twf.doc/m 少晶片封裝體的厚度。 本發明提出一種晶片封裝體製程，其步驟包括先提供 導電層，其中導電層具有第—表面與第二表面。接著於第 一表面形成焊罩層，並將焊罩層圖案化，以暴露出導電層 之部分區域。然後於料層上形成―㈣，並且將導電^ 圖案化，以形成圖案化線路層。然後將晶片配置於第二表 $，並使晶片電性連接於圖案化線路層。之後形成封裝膠
版，以包覆圖案化線路層，並將晶片固定於圖案化線路層 上，然後移除此膜片。 *依照本發明的較佳實施例所述之晶片封裝體製程，其 中膜片例如藉由第一黏著膠體貼附於焊罩層上。 依照本發明的較佳實施例所述之晶片封裝體製程，例 如更包括將膜片固定於框架上，以進行導電層的圖案化 驟。 依照本發明的較佳實施例所述之晶片封裝體製程，例 j包括先藉由焊罩層之®案化倾，於焊罩層上形成多 ^開口。之後於膜片中形成多個對應於這些第一開口 ’其中這些第—開口以及這些第二開口係暴露 出V電層或圖案化線路層之部分區域。 如μ?1 ?_較佳實施例所述m慣體製程，例 此^母—第—開π中形成—外部連接端子，以使這 ς Μ連接端子經由這些第―開口電性連接於圖案 依照本發明的紐實施儀狀w封裝體製程，例 8 1255561 16667twf.d〇c/n 先tr罩層之圖案化步驟於焊罩層上形成多個 第二多個對應於這些第一 曰片夕#八^上一弟—開口以及這些第四開口係暴露出 曰曰 \刀區域與圖案化線路層的部分區域。 如更Ξίίϊ/Ι，佳實施例所述之晶片封装體製程’例 間，以將曰黏著膠體於晶片與圖案化線路層之 晶片化線路層。之制料條導線將 日日月屯性連接於圖案化線路層。 如更佳實施例所述之晶片難體製程，例 路層之部分區2體上形成多個貫孔，以暴露出圖案化線 如更難實施_述之㈣細製程，例 些外部連:端子、 如更較佳實施例所述之晶片 二：：案化線路層之間形成多個凸塊。 如更包較佳實施例所述之晶片封裝體製程，例 些括方、片與圖案化線路層之間形成底膠，以包覆這 ，照本發明的較佳實施例所述之 1=片屮的方式包括钱刻、撕除或灰二:二)。 供導1^另—種晶片封裝體製程’其步驟包括先提 h>兒層，其中導電層且右 第-表面形成第一膜片：並且將導:二：:表面。之後於 且财¥兒層圖案化，以形成圖 9 1255561 16667twf.d〇c/m iinr接著Γ案化線路層上形成科層，並將痒 罩g圖案化，以暴露出圖案化線 详罩層上形成第二膜片，並且移其後於 配置於第-表面，並使晶、^後將晶片 二 甩庄連接於圖案化線路層。鈥 後开/成封切體，以包覆圖案化線 圖案化線路層上，之後移除此第二膜片。曰曰片固疋於 程，月片的以另及一第較佳實施例所述之晶片封裝體製 分別貼^第係經由第—黏著膠體 依π本發明的另—較佳實施例所述之晶>j 程，例如更包括將第二膜片固定於框架上。片封衣體製 依照本發明的另—較 程，例如更包括先夢由Λ / _㈣之晶片封裝體製 口片㈣成多個對應於這這 開口錄露出圖案化導電層之部分區域。 -弟一 、本纟日㈣$ —較佳實施例所述之㉟ >；封裝體jg 使這些外部連接端二二開口中形成:部連接端子’以 線路層。 輕於圖案化 _ 月的另—較佳實施例所述之晶片封裝體製 ί化=於封裝膠體上形成多個貫孔，以暴露出圖 案化線路層之部分區域。 ^ 依知本發㈣另—較佳實施綱述之晶片封裝體製 I2555l^l7twf.d〇c/m 耘，例如更包括分別於每—貫孔中形成/外部連接端子， 以使這些外部連接端子經由這些貫孔電性連接於圖案化線 路層。 依照本發明的另一較佳實施例所述之晶片封裝體製 私’例如更包括於晶片與圖案化線路層之間形成多個凸塊。 依照本發明的另一較佳實施例所述之晶片封裝體製 权例如更包括於晶片與圖案化線路層之間形成底膠，以 包覆些凸塊。 依照本發明的另一較佳實施例所述之晶片封裝體製 私’例如更包括先藉由焊罩層之圖案化步驟，於焊罩層上 开二成二個第二開口。之後於第二膜片中，形成多個對應於 這些第二開口之第四開口，其中這些第三開口與這些第四 開口係曝露出晶片之部分區域與圖案化線路層之部分區 域。 依照本發明的另一較佳實施例所述之晶片封裝體製 私’例如更包括先形成第二黏著膠體於晶片與圖案化線路 層之間，以將晶片固定於圖案化線路層。之後利用多條導 線將晶片電性連接於圖案化線路層。 。依照本發明的另一較佳實施例所述之晶片封裝體製 耘，其中移除膜片的方式例如包括蝕刻、撕除或灰化。 由於晶片封裝體製程中，本發明係利用膜片作為圖案 化線路層以及料層的細，並且能夠於⑼封裝體完成 =將此膜移除’因此本發明能夠在不使用核心、介電層的 f月況下，製作出晶片封裝體。由於此晶片封裝體不具有核 I25m twf.doc/r 〜電層，因此相較 片封裝體具有較薄!言’本發明所製作之晶 易懂為ίΐ::二之i?和其他目的、特徵和優點能更明顯 明Ξ下舉車父佳貫施例’並配合所附圖式，作詳細說 【實施方式】 [苐一實施例] 圖2A〜圖2F !會示為本發明第邮 製程的絲示意圖。請參照圖2a先L ^封^ 其中導電層310具有相對之第本百先“Ή層310， Ή4 對 表面312與第二表面 ^ 材質為銅。接著於312 . 二二 亚且例如利用微影/钱刻製程對焊罩層320 ^化’以形成第三開口 322與多個第一開口似， 中=開口 322與第一開口似係曝露出導電層31〇的 箱區域。在—較佳的實施方式中，本實施例更可以對導 私層310進订掠氧化（blOwn⑽咖加）或是黑氧化⑽成 oxHlatum)處理，以提高導電層31〇之表面粗糙度，並使 得導電層310與焊罩層320之間的接合更良好。 明參恥圖2B，接著於焊罩層32〇上形成膜片33〇，以 作為導電層310與焊罩層320在後續製程中的載體，其中 膜片330例如可以經由黏著膠體而貼附於焊罩層32〇上， 或是以其他的方式直接形成於焊罩層32〇上。因此，導電 層310與焊罩層320能夠在後續製程中獲得足夠的支撑， 使知後續的製程能夠順利進行。在一較佳的實施方式中， 12 1255561 16667twf.doc/m 本實施例更可以將膜片330固定於框架34〇上，以使得導 電層3=與详罩層32〇所受到的支樓更為良好。之後，例 如利用微影/钱刻製程，將導雷爲 化線路層350。 电層310圖案化，以形成圖案 ,33〇/::圖2C ’然後例如利用微影/蝕刻製程，在膜片 330形成弟四開π 332以及多 ， 片360配置於篦-矣而μα L I俊財日日 365 胃、一'^ 上，其方式例如是將黏著膠體 • 去/門^曰曰片360與圖案化線路層350之間，以固定兩 二 =的相對位置。接著例如利用打線結合㈣ w、= 電性連接於圖案化 ϋ 中，導線37g之材質例如為金，第一開口 :開口 334係暴露出圖案化線路層350之部份區 .圖322與第四開口 332係暴露出同時暴露出 固木^路層35〇之部份區域以及晶片之部份區域。 334的^機在^實施例中形成第四開口 332以及第二開口 齡也可以在對、It 了可以在對導線層310進行圖案化之後， 310進行η ^層310進灯圖案化之前。然後再對導線層 _ G進仃_化’⑽成_化導線層35〇。 、上开圖2D，經由適當的模具，於圖案化線路層350 細成，谬體38〇，以包覆圖案化線路層35〇以及晶片 本’^將晶片遍固定於圖案化線路層350上。此外， Η 口 399更可以經由適當的模具將封裝膠體380填入第二 :2^ ’以包覆導線37〇。另外，本實施例更可以在 4 〇 324上形成外部連接端子39〇，並使外部連 13 1255561 I6667twf.doc/n 接端子390經由第一開口 由处（reflow)而電性連接於圖案化線路居350 乂麵 请參照圖2E，然後將膜片33〇移除θ 體300，其中移除膜片33()的方式例如了 =， 蝕刻或灰化或者是直接勝 于馭片330進行 式將膜片330移除。雖妙太奋由矛、亦或是以其他的方 出曰h ”雖μ本貝粑例中封裝膠體380係暴霰 出曰曰片360之部份區域，但顯而易見地 =路 經由適當的模具，使得封Λ細例亦可以 片360。 便仔封衣知月豆380如圖2F所示包覆晶 宰化施例所製作之晶片封裝體300主要包括圖 ^中ΰ 3 Ζ晶片、谭罩層320以及封裝膠體380。 =3案化線路層350具有相對之第一表面 Γ二:f片360係配置於 連接於圖案化線路層350。焊罩層320則配置於第 以上’並且焊罩層320具有多個第—開口 324， ς:圖案化線路層35〇之部份區域。封裝 卯 路層35。’並且將晶…定於圖“ 呈由於本實施例可以藉由膜片330的使用，而製作出不 j核心介電層之晶片封裝體3〇〇，因此相較於習知技術 a，晶片封裝體300具有較薄的厚度。 [第二實施例] 曰曰片封I體製程中，晶片360除了可以如第一實施 14 1255袍 7twf.doc/n 斤=^即㈣打線結合技術❿紐連 層现，更可以以覆晶（叫_ )技術、薄膜=匕、·泉路 〇F )技術或其他技術來完成晶片360與 ':宰化ί ，350之間的電性連接。以下將針採用對覆曰：；1ί 片封裝體製程來舉例說明。 ㈣b技術之晶 製程:二二圖以她^ :4=Γ3!〇且ίΓ圖3A ’首先提供導電層训， 八中¥%層310具有相對之第一表面312鱼 3H。接著於第-表面312上形成焊罩層32g，並^^ 刻製程來圖案化焊罩層320，以形成多個第一開 β 其中第一開ϋ 324係曝露出導電層310的部份區 :里Si ’本實施例亦可以對導電層310進行棕氧化或 =.、、乳化處理’以提高導電層·之表面粗糙度，並 ¥電層310與焊罩層320之間具有更良好的接合。于 請參照圖3Β，接著於焊罩層32〇上形成臈片33〇，以 作為^私層310與焊罩層32〇在後續製程中的载體。其中 膜片330例如可以經由黏著膠體而貼附於 /' 或是以其他的方式直接形成於焊罩層32〇上。^樣地，本 實施例更可以將膜片330固定於框架34〇上，以使得導帝 層310與焊罩層320獲得更良好的支撐。之後，例如利用 微影/1 虫刻製程，將導電層31〇圖案化，以形成圖案化線路 層 350 〇 請參照圖3C，然後例如利用微影/蝕刻製程，在膜片 330形成多個第二開口 334。之後，利用覆晶技術，將晶片 15 I2555^ 7twf.doc/m 置二表面314上，其方式例如是將多個凸塊奶 ==曰:片360與圖案化、線路層35〇之間，並且對凸塊Μ 圖宰=二=:經由多個凸塊372而電性連接於 口木化、泉路層350。其中，凸塊372之材 =其他導電材質’而第—開口 324與 ；:係 ^案=物50之部份區域。另外，本實施例= = 化細％㈣職㈣，以 上开’經由適當的模具’於圖案化線路層35〇 j封衣減380 ’以包覆圖案化線路層35G，並 3=^定牛於圖案化線路層350上。值得一提的是，在^ 之間^成；右沒有在晶片遍與圖案化導線層350 374來包覆這也凸塊372Hl體380更可以取代底勝 一 M 。 一鬼372。此外，本貫施例更可以在每一第 390妳由成外部連接端子，並使外部連接端子 而」二開口 324電性連接於圖案化線路層350。舉例 二二連接端子390為焊球時，其可以經由迴;而 電性連接於_化線路層35()。 、于而 體3〇rd f’然後將膜片330移除’以得到晶片封裝 在此片330的移除方式請參照圖2E之說明， 由適各的;j^JL 5但頒而易見地，本實施例亦可以經 36〇。、，使得封裝膠體380如圖3F所示包覆晶片 16 125呵1 7twf.doc/m [第三實施例] 除了晶片封裝體300與3〇〇’，本發明所揭露之曰曰 裝體製程更可以製作出另一種適於製作堆疊式晶片封 構之晶片封裝體，其製作方式將於下述作詳細的說明，結 圖4A〜圖4E繪示為本發明第三實施例之晶片 製程的流程示意圖。請苓照圖4A，首先提供導電層3ι〇 ~ 其中導電層310具有相對之第一表面312與第二 314。接著於第〆表面312上形成烊罩層32〇，並且例 用微影/蝕刻製程來圖案化焊罩層32〇,以形成第三 322與多個第一開口 324，其中第三開口 322與第一開口 U4係曝露出導電層310的部份區域。在一較^的實ς方 式中，本實施例更可以對導電層310進行棕氧化或是黑气 化處理，以提高導電層310之表面粗糖度，並使得導電^ 1 〇與干罩層320之間具有更良好的接合。 、請芩照圖4B，接著於焊罩層32〇上形成膜片33〇，以 作為導電層310與焊罩層320在後續製程中的載體。其中 犋片330例如可以經由黏著膠體而貼附於焊罩層32〇^， ^是以其他的方式直接形成於焊罩層32〇上。:此一來， 去=層310與；t干罩層320便能夠在後續製程中獲得足夠的 撐，使彳于後縯製程能夠順利進行。在一較佳的實施方式 〜、、’本實施例更可以將膜片330固定於框架340上，以使 ^導電層310與焊罩層32〇獲得更良好的支撐。之後，例 :利用微影/侧製程，_化導電層31Q，卿成圖案化 、、展路層350。 17 1255561 16667twf.doc/m 請參照圖4C，之後將晶片36〇配置於第二表面314 上，其方式例如係將黏著膠體365配置於晶片36〇與圖案 化線路層350之間。接著並且例如利用打線結合技術，使 曰曰片360經由多條導線37〇而電性連接於圖案化線路層 350。其中，第三開口 322與第四開口 332係暴露出同時暴 露出圖案化線路層35〇之部份區域以及晶片細之部份區
、當然，在本實施例中形成第三開口 332的時機，除了 可以在料線層31G進行圖案化之後，也可以在對導線層 31〇進行圖案化之前。之後再對導線層31()進行圖案化: 以形成圖案化導線層350。 請參照目4D，經由適當的模具，於圖案化線路層35〇 形成封裴膠體380，以包覆圖案化線路層35〇以 _ ’並且將晶片3則定於圖案化線路層35〇上。此曰夕曰卜， =貫施例更可以經由適當的模具將縣膠體則殖入第二 ^ 322Θ，以包覆導線37〇。另外，本實施例更在封裝 =380上形成多個貫孔搬，以暴露出圖案化線路層⑽ *區域。其中，貫孔382的形成方法例如包括在模造 ^okhng)封裝雜38〇日寺，即形成這些貫孔搬，或者 裝膠體遍後’再利用機械鑽孔（― 380卜射祕〇順祕細）的方式，在封裝膠體 法⑽场成這些貫孔撕’亦或是其他種形成貫孔搬的方 接著，在每一貫孔382上形成外部連接端子，並 18 1255561 16667twf.doc/m 使外部連接端子390經由貫孔 層350。在-較f t⑦叫接於圖案化線路 導, 中’外部連接端子390係包括 V电柱392與焊球394。導電柱3 且與圖案化線路層3兄電性連接，其中將 开，成主3^，或是直接將導電材料填入貫孔382内以 預定要形成貫孔382的位置，並且 J = j 造製程，如此—來逆仃訂衣私脰382的拉 ♦奸叫96Λ末在形成貝孔382的同時，亦完成了導 軸置。而焊球394則位於導電柱392上，並且 與V电柱392電性連接。 請參照圖4Ε，將膜片33〇移除，以得到 =再其&膜730的移除方式請參照圖沈之說明，找 ! ㈣—實施例與第二實施例可知，本 ^中的晶片36〇與圖案化線路層32〇之間的電性連 來^可2用覆晶技術、薄膜晶片封裳技術或其他技術 末兀成，於此便不再多作贅述。 安Γί述，本實施例所製作之晶片封裝體_主要包括 t固Ϊ路層350、晶片360、焊罩層320、封裝膠體380 卜，接端子39()。其中圖案化線路層35〇具有相 SC 與第二Μ 314。而晶片_係配置於 14上，並且晶片360電性連接於圖案化線路声 =^__於第-表面312上，並且= ”有夕個弟-開口 324,以暴露出圖案化線路層35〇 19 1255561 16667twf.doc/m 之部份區域。封裝膠體則則包覆於圖案化線路層35〇， 亚且將晶片36〇固定於圖案化線路層35〇上，其中封裝膠 版具有多個貫孔382。外部連接端子390則分別配置 於貝孔382内，並且電性連接於圖案化線路層。 田基於上述的晶片封裝體4〇〇,本實施例更提出 一種堆 ^里曰a片封裝結構。請參照圖5，其纷示為本發明第三實 施例之堆疊型晶片封裝結構。堆疊型晶片封裝結構，主 要包括多個相互堆疊的晶片封裝體4〇〇，且中較上声 ：!外部連接端子需對應於較下層^晶片 的第—開口 324’而且較上層之晶片封裝體400 二! ί接端子390係與較下層之晶片封裝體400的圖案 争勺350電？連接。此外’堆疊型晶片封裝結構500 ^ 同承f器510 ’以使這些晶片封裝體400能堆疊 裝^ _^且=些晶片封裝體彻能經由最下層之晶片封 5^0 0 、。卩連接端子39G而電性連接於共同承載器 严产由：:f體400相較於習知技術而言具有較薄的 ί 晶片龍體獅堆疊而成的堆疊型晶片 [Γ四實施例]的表現上具有更__減效果。 例之 夕另一括曰μ & 之机私不忍圖。本貫施例揭露本發明 310苴裝體製程’請參照圖6A，首先提供導電層 3川，其中導電層31〇具有相對的第一表面312與第二= 20 1255561 16667twf.d〇c/m 314。2灸，於第二表面314上形成膜片_。 π參照圖6B，例如利用微影/钱 圖案化以形成_化線路層35G。接著m層 上形成焊罩層320，並且 表面 320 Μ扪用铽衫/蝕刻製程對焊罩層 324 /中 以形成第三開口 322與多個第一開口 4 其中弟二開口 322鱼第一問σ D/i〆 31〇的部份區域。，、弟開口 324係曝露出導電層 片3m^c與仍，綠在烊罩層创上形成膜 =μ成圖6C所示之結構。之後如仍所示，將膜 如第例= 旱到如圖2b所示之結構。接下來的步驟 不再多^ “ 〜圖2e所述’因此本實施例在此便 灰化或是其^式移_ _的方式包_、撕除、 τ上所述，在本發明所揭露的晶片封裝體势避中，夫 ==ί成後將此膜片移除，因此本發明能夠製 =有r介電層，因此相較於習知技術而言= 本發“ 體具有較薄的厚度。此外’在製程上 f作沒=去核心介電層的製作流程，因此本發明之 效率 為間便’是以能夠降低生產成本並且增進生產 限定發Λ已以較佳實施例揭露如上，然其並非用以 X月，任何熟習此技藝者，在不脫離本發明之精神 21 1255561 16667twf.doc/m
250、 394 :焊球 310 ： 導電層 312 ： 第一表面 314 ： 第二表面 320 ： 焊罩層 322 ： 第三開口 324 ： 第一開口 332 ： 第四開口 334 ： 第二開口 330、 600 :膜片 340 ： 框架 350 ： 圖案化線路層 360 ： 晶片 365 ： 黏著膠體 370 ： 導線 380 ： 封裝膠體 382 ： 貫孔 390 ： 外部連接端子 510 ： 共同承載器 23

Claims (1)

1255561 16667twf.doc/m 丁、r砑寻利範面·· i一種晶片封裝體製程，包括· 二表:供-導電層，其中該導電層具有-第—表面與1 以暴叫圖案化， 於該焊罩層上形成—膜/片； 將该導電層圖案化， 一 將-晶片配置於該第化線路層； 該圖案化線路層； ^亚使该晶片電性連接於 封震膠體，以包覆該 片固疋於該圖案化線路層上；以及⑽滑亚將該晶 移除該膜片。 中該膜#二^利㈣第1項所述之晶片封裝體製程，其 ^ ’、糟由一第一黏著膠體貼附於該焊罩層上。“ 3·如申睛專利範圍第1項所述之晶片封裝體製程，更 包括將4膜片固定於一框架上，以進行該導電層的圖案 步驟。 一 卞 4·如申請專利範圍第 包括： 藉由該焊罩層之圖案化少 第一開口，·以及 、 1 ί 負戶斤述之日日片封I體製程 雜於該知罩層上形成多 Π ， 於該膜片中形成多個對應於该些第:開口之第： 其中該些第—開口以及該竣第>開口係暴露出該② 24 I25554i 7twf.d〇c/m 層或該圖案化線路層之部分區域。 包括!^申請專利範圍第4項所述之晶片封襄體製程，更 形成一外部連接端子，以使該 路層。^ t由该些第—開口電性連接於該圖案化線 包括·/申°月專利视圍第4項所述之晶片封裝體製程，更 第三=該=層之圖案化步驟於該焊罩層上形成多個 口，ί:?片中形成多個對應於該些第：開口之第四Η 口，其中該些第三開口以 ^ 不一间口之弟四開 之部分區域與該圖案化線^二第四開口係暴露出該晶片 7.如申請專利範圍第^的部分區域。 包括： 項所述之晶片封裝體製程，更 形成一第二黏著膠體於 間，以將該晶片固定於哕问；曰曰片14該圖案化線路層之 利用多條導線將該路層」·以及 &如申請專利範圍第】^連接於该圖案化線路層。 包括於該封裝膠體上形成多員^斤述之晶片封裝體製程，更 路層之部分區域。 固貝孔，以暴露出該圖案化線 9·如申請專利範圍第8 4b 層 ^括分別於每一該些貫孔中、、斤述之晶片封裝體製程，更 外部連接端子經由該些成外部連接端子，以使該 。 、電性連接於該圖案化線路 25 ί255ι·“ 更包括二Τ;湖範圍第1項所述之晶片封裝體製径 η曰片與該圖案化線路層之間形成多個凸塊 程，更包圍第w項所述之晶片封裝體製 以包覆該些r塊與該_化線路層之卿成—底膠， 其中二1項所述之晶片封裝體製程， 片的方式包括蝕刻、撕除或灰化。 \3· 一種晶片封裝體製程，包括·· 二表ί供—導電層’其中該導電層具有—第—表面與-第 於該第-表面形成一第一膜片； 將该導電層圖案化，以形成一圖案化線路層； 於口亥圖案化線路層上形成一罩声， 案化’崎露出該圖案化線路層之部^區域广 > 罩層圖 片；於糾罩層上形成—第二膜片，並且移除該第—膜
該圖置於該第—表面，吏該晶片電性連接於 形成-封裝膠體，以包覆該圖案化線路厚 片固定於該圖案化線路層上；以及 亚將该晶 移除該第二膜片。 程，其巾t㈣—^ ^ #封裝體製 體分別貼附於該第-表====由—第一黏著膠 26 I255m twf.doc/] m I255m twf.doc/] m Γ包㈣13項所述 之 片封裝 晶 程，更包括“Γ 13項所述： 栝將邊弟二臈片固定於一框 體I 程，更包ί申請專利範圍第13項所述之晶片封裝 第狀_化步料、料上形成多也 於该第二臈片中形成多個對應 ;二：其中該些第-開-以及該些第開口之1 圖案化V電層之部分區域。 一開口係暴露出言I 17·如申請專利範圍第16 、 私’更包括於每-該些第-開口切奴晶片封裝體製 ^吏該些外部連接端子經由該些第部連接端子， 木化線路層。 $口電性連接於該圖 18. 如申請專利 ;，更紐於_轉^彡13;：;^^封裝體製 案化線路層之部分區域。 、孔，以暴露出該圖 19. 如申請專利範圍第18項 程，更包括分別於每一該些貫孔中心之晶片封裝體製 以使該些外部連接端子經由該些貫孔部連接端子， 線路層。 、电性連接於該圖案化 2〇.如申請專利範圍第13 程，更包括於該晶片與該宰路斤迷之曰曰片封裝體製 程’更包括於該晶片與該圖案化線路二= 27 12555^1 7twf.doc/m 以包覆該些凸塊。 22. 如申請專利範圍第13項所述之晶片封裝體製 程，更包括： 藉由該焊罩層之圖案化步驟於該焊罩層上形成多個 第三開口；以及 於該第二膜片中形成多個對應於該些第三開口之第 四開口’其中該些第三開口與該些第四開口係曝露出該晶 片之部分區域與該圖案化線路層之部分區域。 23. 如申請專利範圍第22項所述之晶片封裝體製 程，更包括： 形成一第二黏著膠體於該晶片與該圖案化線路層之 間，以將該晶片固定於該圖案化線路層；以及 利用多條導線將該晶片電性連接於該圖案化線路層。 24. 如申請專利範圍第13項所述之晶片封裝體製 程，其中移除該膜片的方式包括蝕刻、撕除或灰化。 28
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