TWI247367B - Semiconductor package free of carrier and fabrication method thereof - Google Patents

Semiconductor package free of carrier and fabrication method thereof Download PDF

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Publication number
TWI247367B
TWI247367B TW093137145A TW93137145A TWI247367B TW I247367 B TWI247367 B TW I247367B TW 093137145 A TW093137145 A TW 093137145A TW 93137145 A TW93137145 A TW 93137145A TW I247367 B TWI247367 B TW I247367B
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carrier
semiconductor package
package
manufacturing
electrical contact
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TW093137145A
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English (en)
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TW200620496A (en
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Yu-Wei Lin
Fu-Di Tang
Chun-Yuan Li
Terry Tsai
Yu-Ting Ho
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Siliconware Precision Industries Co Ltd
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Priority to TW093137145A priority Critical patent/TWI247367B/zh
Priority to US11/042,939 priority patent/US7314820B2/en
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Publication of TWI247367B publication Critical patent/TWI247367B/zh
Publication of TW200620496A publication Critical patent/TW200620496A/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H01L2224/48996—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/48997—Reinforcing structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

1247367 九、發明說明： 【發明所屬之技術領域】 本於一種無承載件半導體封裝件及其製法， ，曰-抓泉式之無承載件半導體 【先前技術】 對傳統無接腳四方扁平導綠加 χτ ,,, 砀十¥線条式封裝件（Quad Flat
Non-leaded，QFN)而言，苴晶片庙田㈤ ,^ ^ ^ 日日片庄周圍之多數導腳（Lead) 上在在故計有階梯或鎖固結 以拉筮、蓄 再女乐！A、IB、1C圖所示， 以猎苐1B圖之導腳階梯結構 構仏增加封裝夥體43盘導腳;圖之導腳鎖固結 升…力，以… 間的接觸面積，進而提 1:二？ 腳4〇脫離或封編43之脫層； 靠度與電性品質。ά線45’顧及封裝件之結構可 然而’隨著半導體產品輕薄短小之趨 傳統導線架往往因其厚度、|重要’ 古择一7 限制而無法更進一步縮小1 -度’热承載件之半導體封農結 載件之半導體封裝件而言，出現，此因對無承 度’進而可令其整體厚度較傳統導 免習知上無法降低厚度之結構限制式封衣件為薄，避 有減載件之半導體封裝件而言，其雜具 ^ …、也因其亚未具有習知導線架之
圖所干Λ 虎案所示，其封褒件係如第2A、2B 口汁不先於一銅質承載件 上依線路佈局形成多數電鍍 18203 5 1247367 在干墊51 (Pad) ’该電鍍銲墊之鍍層係包括Au/pd/Ni/p 鈀/鎳/把）層，且其厚度大約為6//m;接著，再於 至 5 〇上設置晶片5 2並進行銲線5 3連接作業，復^第2 B載圖牛 般，於形成封裝膠體54後移除該銅質承載件5〇， 該多數録堅5 i上植接銲球55 (s〇lder咖），與外界電性連 接’即可進彳T切割並完成無承載件封裝件之封裝步驟。 相較於第1A圖所示之f知封裝件係將料4 5固接於 對應導腳4〇上，此一將銲線53接置於電鑛銲墊51之 中’其電鍵銲塾51顯然無法如第1A圖之導腳如般為膠 體43穩固夾持（因銲塾51之厚度僅約薄，遠不若1 般厚達20(^m之導腳般易於夹持），因而導致電料㈣
遇屈’從而導致銲線53㈣，並因封裝膠體M ㈣間”合力不足，而於表面黏著步驟後出現電料： 5 1自封I膠體54剝離之現象。 此外’該電鍍銲墊51最上層之pd鐘層與膠體 献 數差距甚大（12:18)且附著力差，亦可能出現熱膨服 =匹配（CTE M職atch)而脫層之問題，導致銲線$3之斷 :，=，當該封裝件以電鑛料51接置於—印刷電路板上 "’右該膠體54無法穩固夾持該料5卜該銲墊51亦將 因封裝件與印刷電路板間之熱膨脹不匹㈣脫層，產 重的品質問題。 再如美國專利第6,77〇,959號案所揭示，其封裝件係 °弟3圖所揭露，先形成一由拒鮮劑層6ι…此以址） 所定義之導腳層62 (Lead Layer)與晶片座層叫心_ 18203 1247367 laye〇 ’復將晶片64接置於該晶片座層上，並藉多數銲. 線65電性連接至對應之導腳層62位置，達至封裝之要求。h 此白知技術亦同樣具有前述結合力不足等問題，若相較 於傳統上具有階梯或鎖固結構的導線架，本技術中之封果· 膠體66與導腳層62顯然仍將出現脫層剝離之現象，而導 致銲線6 5斷線。 ’ 或再如白知上所提出的另一無凸塊式晶片承載件
(BUmplessChipCarrier BCC)封裝技術，如第4圖所揭示 Μ國專利第6’〇72’239號案’係形成—凹狀魏鮮塾？！ =糟銲線72連接該凹狀電鐘銲塾71與晶片^，進而以逢 ^體74包覆晶片73與該多數銲線72,完成封裝之要 ^此-技㈣相較於傳統導線架式封裝件 靖/ 接合不良的問題，而可能導致銷 ^之^與钱料71^離，形成結 構缺點。 | 〜 囚此 如何開發-種無承載件半導體封裝件及其製 法’以在降低封裝件厚度 紝 而求下，同時兼顧封裝膠體 ^力’進而保護封裝件之結構與銲線電性，確已為此 關領域所迫切待解之課題。 … 【發明内容】 題’本發明之主要目的即 膠體黏著力的無承載件半 因此，有鑑於前述及其他問 在於提供一種可提升銲墊與封裝 導體封裝件及其製法。 本發明之另一 目的在於提供—種可避免銲墊與封裳膠 18203 7 !247367 製 月五之熱膨脹不匹配現象的無承載件半導體封裝件及其 本發明之復-目的在於提供一種可避免 承载件半導體封裝件及其製法。 畊衣勺，，，、 本發明之再—目的在於提供—種可避免 承載件半導體封裝件及其製法。 /a的‘、、、 "本發明之又-目的在於提供一種可降低封 热承載件半導體封裝件及其製法。 ^子又勺 ” 載件半導體封裝件製法，係包括 性接點，·將至少、該承載件上係形成有多數個電 以藉多數銲缞1性曰;1接置於該承载件上；進行銲線製程， 數電性接點上分別形成_覆蓋声點，於該多 銲線連接端，·進行模屙已復该琶性接點上之 覆該晶片、銲線以於該承載件上形成用以包 件，以令該夕^ 的封裳膠體，·以及移除該承載 x电性接點外露出該封裝膠體。 括:二二二提;之無承載件半導體封裳件，係包 連接該晶片與該夕2电11接點’多數銲線’係用以電性 點上的覆蓋層，以勺點，分別形成於該多數電性接 一封裝膠體，係用、=°亥电性接點上之銲線連接端；以及 該多數電性接點外片、銲線與電性接點，並令 本發明之製法;封裝膠體。 - 封裝膠體的多數♦:L於移除δ亥承载件後，於外露出該 电性接點上分別植設銲球，同時，復進行 18203 8 1247367 切割步驟以形成多數個半導體封裳件。 材料：外立，蓋層係為例如樹脂、Ρί、或矽膠之高分子 薄型‘點凡王復盖该電性接點；而該電性接點係為-uad)計而選用電鑛銲塾㈣）或凸塊式導腳 因此’藉由前述覆蓋層之形成與 銲線之銲結力，並 將了充刀㈣ _步驟中脫落，二 == 生=後續表 或剝離，解決習知技術的諸多問題。’之脫層 【實施方式】 “：:系藉由特定的具體實例說明本發明之實施方式， :=技Γ人士可由本說明書所揭示之内容輕易地睁解 !!之其他優點與功效。本發明亦可藉由其他不同的且 體貫例加以施行或應用，本說明書中的各項細節亦可二： ==應用’在不捧離本發明之精神下進行各種料 又乐）A圖，提供一銅質 :〇’該承載件ίο上依線路佈局而被圖案化成多數個電性接 ^及晶片座塾u’該些電性接點11#、為薄型的電社 (Pad)如金/絶/錄/絶電鍍層，以符封裝件薄型化之^〒— 接著，再如第5B圖，將一晶片15接置於該承载件=， '^座f 12上，並進行料製程，以藉多數銲線20二 接5亥曰曰片15與，亥晶片15周圍的多數電性接點⑴此 18203 9 1247367 二避免銲線2。之固結力不
Layer) t it:別塗佈形成—覆蓋層叩一 y ^ U兀全覆盍於該雷性桩a： ! t , 點η上之銲線20連接端，提升。1上’並包覆該電性接 性接點u脫落，而該覆蓋^之固結並避免該電 石夕膠的高分子材料層。曰^為—例如樹脂、打、或 再如第5D圖，進；^干描兩告“ 成用以包覆該晶片15而於該承載件10上形 3〇,以保護晶片15盘”=;性接點11的封裝膠體 ^ 5 3〇 與封裝膠體3G之間，·再;5將介於該電性接點U (咖ng)之方式移除_載^圖=，㈣虫刻 1 1將外露出爷封壯脒_ U T ^夕數電性接點 亦可如第mi卜，而與外界電性連接；或者， (S_B·以藉該些銲球 植；^球35 割一—步驟，沿該封裝夥體心^ | 得所需之半導體封料。 域切’即可製 本冬明之设計除了於該承载件10 鑛銲塾外，亦可將該電錢料改為導電凸成圖;;化之電 數銲線2G電性連接該q 猎由多 收相同之功效;此外，本發明之曰=:式導腳，亦可· 10之雷^ 15除接置於該承载件 接點U上，亦可直接接置於該承載件1〇上的預 18203 10 1247367 1 1 迢位置，而藉該預留位置 壓製程後移除該承载件1Q即可ί ^承載件’再於模 因此’經由本發明之萝/日 料’即如第5G圖所示，：括斤Τ片:婦半導體封 …該晶片u與該多數電性接心曰广多數電性接點 性連接；同時，該多數電性⑨二猎夕數鲜、線20而電 爲〇 c ^ 接點11上係分別塗布右一舜焚 層25 ’以包覆該電性接點u 有设现 線2〇之固著，該承載件、之^線2()連接端，提升銲 包覆該晶片15、辉線2。與二成二：”-’以 接點11外露出該封裝膠趙 夕數電性 植設有一銲球35。 母毛性接點11上均 综上所述，即知藉由前述 -緩衝—層之功能，以減二曰提供 體30間熱膨脹不匹配 丨接^11與封裝膠 膠體30之緩衝區，以為該電性接點Π與封褒 巧n 牛低熱應力，避免脫層之發味· “盍層25亦可對該電性接點u :广 :封裝膠體3〇對該覆蓋層亦有較佳之附著:=，且 电性接點11與封裝膠體30間之為菩 σ強化忒 11被穩固地夾持於該封裝谬體^中，’進而=些電性接點 輝結力，避免電性接點II脫落、_ 升1于線20之 體30脫層等諸多問題。 . _、、表或自封裝膠 限定並㈣《 因此’舉絲u顧料^絲; 18203 11 1247367 ’仍應由後述 與技術思想下所完成之一切等效修飾或改變 之申請專利範圍所涵蓋。 【圖式簡單說明】 第1A至1C圖係習知導線架式封裝件的示意圖； 第2A及2B圖❹國專利第5,83G，卿號案所°揭示之 封裝件製法流程圖； 第3圖係美國專利第6,77〇,959號案所揭 剖視圖； <封衣件 封裝件 法流種 第4圖係美國專利第6,〇72,239號案所揭示之 剖视圖；以及 第5A至圖係本發明之半導體封裝件的製 【主要元件符號說明】 10 承載件 11 電性接點 晶片座塾 15晶片 20 銲線 25 覆蓋層 30 封裝膠體 35 銲球 40導腳 41 階梯結構 鎖固結構 18203 12 42 1247367 43 封裝膠體 44 晶片 45 銲線 50 承載件 51 銲墊 52 晶片 53 銲線 54 封裝膠體 55 銲球 61 拒銲劑層 62 導腳層 64 晶片 65 銲線 66 封裝膠體 71 凹狀電鍍銲墊 72 銲線 73 晶片 74 封裝膠體

Claims (1)

1247367 十、申請專利範圍·· 1.種無承載件半導體封裝件製法 提供—τ已栝以下步驃·· 點，· 载件，該承载件上係形成有多數個電性接 將至少—B U , ^ 日日片接置於該承载件上； 户I 藉彡數料電料接該曰片也 多數電性接點； 心條4日日片與該 於忒多數電性接點上分別形 電性接點上之銲線連接端； U以包覆該 進行_程，以於該承载件上形成 片、銲線與電性接點的封裝膠體；以及 设^曰曰 膠雜移㈣承料，《令該w接料㈣該封裝 2. ::請Π圍Γ項之無承載件半導趙封裝件製法， 壯、中5亥衣法使包括於移除該承載件後，於外露 衣膠體的多數電性接點上分別植設銲球。 … 3. Π請專f範圍第1項之無承載件半導體封裝件製法， 2中’該製法復包括於移除該承載件後，進行 而形成多數個半導體封裝件。 j/v 4. 如申請專利範圍第1項之盔承巷 …承載件+導體封裝件製法， 其中，該覆蓋層係為一高分子材料層。 =申請專利範圍第i項之無承載件半日導體封裝件製法， 田树月曰、pI、及矽膠所組成之組 野之一者。 18203 14 1247367 6. 如申請專利範圍第1 貝之”、、承载件半導體封裝件製法， 其中，該覆蓋層係完全覆蓋該電性接點。 7. ^申請專利範圍第㈣之無承载件半導體封裝件製法， 八 4琶性接點係為一薄型接點。 & ^申請專利範圍第7項之無承载件半導體封裝件製法， -令，該薄型接點係為金/鈀/鎳/鈀之電鍍金屬層。 9.如申請專利範圍第！項之無承载件半導體封裝件製法， 其甲，該電性接點係為一電鍵銲墊（pad)。 10·如申請專利範圍第i項之無承载件半導體封裝件製法， /、中。亥电性接點係為一凸塊式導腳（Bump Lead)。 U·如申請專利範圍第丨項之無承載件半導體封裝件製法， 其中，該承载件係為一銅質承載件。 12. 如申請專利範圍第丨項之無承載件半導體封裝件製法， 其中，該封裝膠體係為一樹脂材料。 13. -種無承載件半導體封裝件，係、包括： 至少 片； 曰曰 多數電性接點； 點 多數銲線’係用以電性連接該晶片與該多數電性 设ι層，係分別形成於該多數電性接點上，以 5亥電性接:點上之銲線連接端；以及 包 教八封裝膠體’係用以包覆該晶片、銲線與電性接點 14·如7 5亥多數電性接點外露出該封裝膠體。 。申請專利範圍第13項之無承載件半導體封裝件， 15 18203 I * 1247367 中X封衣件復包括多數I旱;求，其係、分別植設於外露出 S亥封裝膠體的多數電性接點上。 15. 如申請專利範圍第13項之無承載件半導體封裝件，其 中，5亥覆蓋層係為一高分子材料層。 16. 如申請專利範圍第13項之無承載件半導體封裝件，其 中’遠覆A層係選自由㈣、ρι、切膠所組成之组 之一者。 、 17. 如申請專利範圍第13項之無承載件半導體封裝件，其 中，該覆蓋層係完全覆蓋該電性接點。 18. 如申請專利範圍第13項之無承載件半導體封裝件，盆 中，該電性接點係為一薄型接點。 /、 19. 如申請料範圍㈣項之無承載件半導體封裝件，其 中。亥薄型接點係為金/把/錄/把之電鍵金屬層。 2〇.如申請相範㈣13項之無承载件半導體^件，其 中，該電性接點係為一電鍍銲墊（Pad)。 21. 如申請專·圍第13項之無承載件半導體封裝件，盆 中，該電性接點係為一凸塊式導腳（BumpLead)。/、 22. 如申請專利範圍第13項之無承載件半導體封裝件，盆 中，該封裝膠體係為一樹脂材料。 〃 18203 16
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