TWI245593B - Embedding resin, wiring substrate using same and process for producing wiring substrate using same - Google Patents
Embedding resin, wiring substrate using same and process for producing wiring substrate using same Download PDFInfo
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- TWI245593B TWI245593B TW91100717A TW91100717A TWI245593B TW I245593 B TWI245593 B TW I245593B TW 91100717 A TW91100717 A TW 91100717A TW 91100717 A TW91100717 A TW 91100717A TW I245593 B TWI245593 B TW I245593B
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- Prior art keywords
- resin
- wiring
- embedded
- substrate
- circuit board
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
1245593 五、發明說明(1) 發明背i 本發明係關於一種用來將諸如晶片電容器,晶片誘導器 (chip inductor)與晶片電阻器(chip resistor)之類的電 子零件嵌入一佈線電路板(佈線電路板或是佈線基板)中的 甘欠入树脂(填充樹脂),一佈線電路板具有一電子零件嵌入 於其中與一用來生產一使用上述嵌入樹脂的佈線電路板之 製私。特別是,本發明適合用於多層佈線電路板,用來接 收半導體元件組件,以及諸如此類。 2li_担技藝之始沭 近年來’已經有相當多的研究是關於一種具有許多配置 於集、(佈線電路板(building-up wiring circuit b〇ard)上之半導體元件的多晶片模組(muiti - chip module ;MCM) ° —種電子零件,例如晶片電容器,晶片誘導器, 曰曰片電阻裔以及諸如此類,通常可以表面固定於一形成於 一具有一焊料(s〇lder)的佈線電路板之一表面的配置佈線 層之上。 然而’在將電子零件表面固定於一片組合佈線電路板之 表面上的時候’ 一組對應於個別的電子零件之預定的固定 區域丄可以自然的限制上述的佈線電路板之最小值。在表 面=疋的過程中,在一些佈線的排列(處理)中,就特質的 立場而言並不受歡迎的寄生電感將會提升,進而造成電子 裝置難以應付在較高頻率下使用的問題。 為了解決上述的問題,已經有相當多的研究是關於各種1245593 V. Description of the invention (1) The invention relates to a method for embedding electronic components such as chip capacitors, chip inductors and chip resistors in a wiring circuit board (wiring). The circuit board or the wiring substrate) is filled with resin (filled resin). A wiring circuit board has an electronic component embedded therein and a system for producing a wiring circuit board using the embedded resin. In particular, the present invention is suitable for a multilayer wiring circuit board for receiving a semiconductor element package, and the like. 2li_Beginning of the skill in recent years' A lot of research has been done on a multi-chip module (muiti) with many semiconductor components configured on a building-up wiring circuit board. -chip module; MCM) ° — an electronic component, such as a chip capacitor, a chip inductor, a chip resistor, and the like, which can usually be surface-mounted on a wiring circuit board formed with a solder. A surface is provided with a wiring layer. However, when the surface of an electronic component is fixed on the surface of a combined wiring circuit board, a set of predetermined fixed areas corresponding to individual electronic components can naturally limit the above-mentioned wiring. The minimum value of the circuit board. In the process of surface = 疋, in some wiring arrangements (processing), the parasitic inductance that is unpopular from the standpoint of traits will increase, which makes it difficult for electronic devices to cope with higher The problem of frequency use. In order to solve the above problems, there have been quite a lot of researches on various
C:\2D-00DE\91-04\91100717.ptd 第4頁 1245593 五、發明說明(2) 包含在上述佈線電路板中的電子零件之嵌入。日 專利第1 999M 26978字號揭露了一種方法,包含已公開 固定一電子零件於一片佈線電路板之上’上述的先接合 板具有一組由金屬箔所組成的傳送片材,並接、、二路 電子零件傳送至另n線電路板。$而,上述的;J的 可以預期的留下了-些諸如在固定過程中之定位的準確: 之類的問題。日本已公開專利第2〇〇〇 — 1 24352字號 一種多層佈線電路板,具有一層組合在一組嵌入於一路種核 心基板(core substrate)中的電子零件之上的絕緣層。乂 上述關於一種核心基板中的電子零件之嵌入的方^需要 在上述核心基板與電子零件之間的缺口中填入樹脂並2上 述電子零件的電極與形成於絕緣層之上的佈線可以藉由諸 如缺電子的金屬薄片之類的方式來彼此連接。在上^的範 例中 種一般的敢入樹脂無法充分的附著於諸如佈線之 類的沉積物(金屬薄片),在一可靠度測試上會造成一種沉 積物發泡的問題(例如,圖5中的2 9 )。 發明之概诚 本發明之目的在於提供一種嵌入樹脂,其可改善具有電 子零件裝設於其中之佈線電路板之安裝密度(m〇unting dens 1 ty )以及對於例如抗衝擊測試及抗水測試之可靠度測 試,備高可靠度,利用該嵌入樹脂之佈線電路板以及利用 該嵌入樹脂來製造佈線電路板之方法。 本發明之嵌入樹脂至少包含可溶樹脂及可溶有機填充劑C: \ 2D-00DE \ 91-04 \ 91100717.ptd Page 4 1245593 V. Description of the invention (2) Embedding of electronic parts contained in the above wiring circuit board. Japanese Patent No. 1 999M 26978 discloses a method including publicly fixing an electronic component on a piece of wiring circuit board. The above-mentioned pre-joining board has a set of transmission sheets made of metal foil, and is connected in parallel. The electronic components are transferred to the other n-wire circuit board. However, the above mentioned; J's can be expected to leave-some issues such as the accuracy of the positioning in the fixing process :. Japanese Published Patent No. 2000-1 24352 A multi-layer wiring circuit board has an insulating layer combined on a group of electronic parts embedded in a core substrate of various kinds.乂 The above-mentioned method for embedding electronic components in a core substrate ^ It is necessary to fill resin in the gap between the core substrate and the electronic components. 2 The electrodes of the electronic components and the wiring formed on the insulating layer can be obtained by Such as electron-deficient metal flakes. In the above example, a general dare resin cannot sufficiently adhere to deposits (metal flakes) such as wiring, and will cause a problem of deposit foaming on a reliability test (for example, in FIG. 5 2 of 9). SUMMARY OF THE INVENTION An object of the present invention is to provide an embedded resin that can improve the mounting density (mounting dens 1 ty) of a wiring circuit board having electronic components installed therein, and is useful for, for example, impact resistance tests and water resistance tests. Reliability test, with high reliability, a method for manufacturing a wiring circuit board using the embedded resin and a wiring circuit board using the embedded resin. The embedded resin of the present invention contains at least a soluble resin and a soluble organic filler
C:\2D-C0DE\91-04\91100717.ptd 1245593 五、發明說明(3) 氧化劑溶解之可溶成分。經由選擇地溶解及去除可溶樹脂 及^含於該嵌入樹脂並具有一氧化劑之溶解有機填充劑, 遠f入樹脂之表面會易於變粗糙,以發揮獲得一預期佈線 者之口疋作用。結果,甚至一具有一結合於其中之電容 為之佈線電路板可以最小量之佈線黏著的可靠度來設置, 亦$ S大1電流流動於形成在具有一電容器嵌入於其中之 甘入入树脂上之供電佈線(p〇wer sUppiy wiring)。 發明之詳細姑沭 關於可利用氧化劑溶解之可溶樹脂,可使用一已改性 (mojH led) 丁二烯橡膠,以獲得一良好粗糙表面之優點。 =些細節中,於含羧基之丙烯腈丁二烯橡膠中,較佳例 ::止於羧基之丙烯腈丁二烯橡膠(ctb趵、含羧基之丙 酉夂系橡膠、N B R、已改性璟惫其丁一咗 分取- Γ衣虱基丁一烯、已改性順丁烯二 = ,係為可溶於氧化劑中之液狀橡膠,其特 別具有極佳之粗糙性質。 巧於:j用氧化劑溶解之可溶有機填充劑,可使用任何已 知的可溶於氧化劑之樹脂咬 中,較佳為已交聯_填充劑有機丙真Λ劑。於丁二稀填充劑 氧樹脂填充劑料,係㈣填充劑、環 且由於該等填充劑可調整::解2化劑之有機填充劑’ 表面之非平坦大小。 以易於調整形成於該粗糙 遠可溶樹脂及/或可溶有機埴 樹脂,係為1至30重量百分=真4充劑之使用量基於該故入 更佳為1至1〇重量百分比。,較佳為1至20重量百分比,C: \ 2D-C0DE \ 91-04 \ 91100717.ptd 1245593 V. Description of the invention (3) Soluble ingredients dissolved by oxidant. By selectively dissolving and removing the soluble resin and the dissolving organic filler contained in the embedded resin and having an oxidizing agent, the surface of the resin can be easily roughened, so as to exert the effect of obtaining a desired wiring. As a result, even a wiring circuit board with a capacitor incorporated therein can be set with a minimum amount of wiring adhesion reliability, and a $ 1 large current flows on a resin formed with a capacitor embedded therein. Power supply wiring (p〇wer sUppiy wiring). Detailed description of the invention Regarding the soluble resin that can be dissolved with an oxidizing agent, a modified (mojH led) butadiene rubber can be used to obtain the advantage of a good rough surface. = In some details, in the acrylonitrile butadiene rubber containing carboxyl group, the preferred examples are: acrylonitrile butadiene rubber that stops at the carboxyl group (ctb 趵, acrylonitrile rubber containing carboxyl group, NBR, modified Weaning its butyl butadiene-Γ 虱 虱 butyrene, modified cis butylene di =, is a liquid rubber soluble in oxidants, which has particularly good rough properties. Coincidentally: j A soluble organic filler which is dissolved with an oxidizing agent may be used in any known resin soluble in an oxidizing agent, preferably a cross-linked filler, an organic propionate Λ. It is filled with a succinic diluent filler, an oxygen resin. The agent is a filler, ring and can be adjusted due to these fillers: the size of the non-flat surface of the organic filler's organic solvent. It is easy to adjust the formation of the rough far soluble resin and / or soluble The organic rhenium resin is 1 to 30 weight percent = true 4 charge. The amount of use based on the reason is more preferably 1 to 10 weight percent., Preferably 1 to 20 weight percent,
1245593 五、發明說明(4) 5〇:ΐ用:=該T溶有機填充劑的直徑較佳為不大於 入 〆肷入樹脂亦易於流經介於該電子零件之雷 極之間,缺口(gap)為必需的。此係因為當可溶有機充、 劑之^ ^超過5〇微来時,該可溶有機填充劑會易於阻爽介 於該電子零件之雷榀+卩日n , 丨基;丨 填滿,並產生且有月邱Β’ ,而造成嵌入樹脂不足以 、、士 士 w 生/、有局〇卩不同熱膨脹係數之部分。該可、玄右 杈、w之直徑較佳不超過30微米,更佳不超過2〇彳气乎, 特佳為不超過1 〇科丰。$ i & υ u ^ 矣τδ芈:典,土 π/ν :再者,s該嵌入樹脂可拋光為使其 A可避I葬* :該可溶有機填充劑,以產生極不平坦度, 其了避免精由電鍍而隨後形成微細 劑之直徑的較低範圍較佳為不小 了當合有^充 直r於該範圍以下0寺,該嵌入樹脂 :小於可//機填充劑之直徑的較低範圍係更佳 不J於未’特佳為不小於〇.5微米。 至少匕3液狀%虱樹脂及無機 之調整該熱膨脹係數的作用之外,:J卜t •。除了其 琴P叙持务 > 山外该等不可溶成分可防止 =構之ί加之=入樹脂為大於藉已硬化之環氧樹脂之立體 或做為一聚集物之無機填充劑之作用所 =樹=使用量基於該嵌入樹脂, 里百为比,較佳為5至25重量百分比。 重」5 充j之使用量基於該嵌人樹脂,係可為45至85 里刀 乂佳為50至75重量百分比,更佳為60至75重 第7頁 C:\2D-CODE\91-04\91100717.ptd 五、發明說明(5) 量百分比。 考慮到該嵌入樹脂之流動性時,一 用做為-必要的添加劑。此係 =:氧樹脂較佳使 公低黏性’以及因此允許合併例如口身; 之熱膨脹係數之無機填充劑之填充劑= = = 係較佳使用-雙-型環氧樹脂。 環氧樹脂等等相較,係且水甘油醚或脂環族 性)。就未減少工作效率而t,1半(特,是耐熱 額外地使I料Μ環氧錢之較彳;;旨係=佳 ^Cnovoia,) ,, , ^ # 0 ,, ^ …換::。=為萘樹脂具有特佳之耐熱性及耐濕性。 桝iii ^僅使用半固體環氧樹脂時,該所產生之敌入 二=升高的黏性。因此,例如需要降低嵌入樹:之 機填充劑之填充劑成分無法以高填充比例 2 3獲得與使用液狀環氧樹脂之例子所得到之 及填充比例,需要加入可揮發溶劑。然而,一可揮= =ί =會因為殘留溶劑而造成嵌入樹脂之泡泳的產生,並 使其處於不利之狀態。 貝質上不溶於氧化劑之無機填充劑並未有特別地限 但ί ί 1圭為結晶二氧化矽、熔解二氧化矽、氧化鋁、氮化 矽或等等。經由加入此種高填充比例填充劑之無機填充 第8頁 \\312\2d-code\9l-04\9l100717.ptd 1245593 五、發明說明(6) 劑,以致使該嵌入樹脂之熱膨脹係數不大於4〇 ppm/它(較 佳不大於30 ppm/t,更佳不大於25 ppm/£>c,特佳為不大 於20 pPm/t:,而最低界限為不小於1〇 ppm^c),可減少 歸因於嵌入電子零件血_ _ 差之應力的集中 裝…體-件之間的熱膨脹係數 丹之形狀較佳為球…改善流動性及嵌入 rm 二氧化石夕為主之無機填充劑為特佳 的:因為其易於獲得球形1 了進-步降低流動性及:文盖 該:欠入:脂之填充比例’較佳加入二或多種具有不同顆; 形狀之無機填充劑。 个丨』稍粒 將於:加入之無機填充劑的顆粒直徑較 :,因為嵌入樹脂需要透過介於電子零件間的缺口= 動。該無機填充劑之顆粒直徑較佳不大於3〇 ^ 大於2。微米,特佳不大於1〇微米。當無機 徑超過5〇微米時,所產生的填充劑會容易阻塞介於電子^ =電極之間的缺π,而造成嵌人樹脂無法足夠地7 :肷入樹脂產生具有局部不同熱膨脹係數之部份。再:’ 二將該f入樹脂拋光並使其表面平滑時’ Ϊ二:後生成之微細佈=不 十了度/無機填充劑之直徑的最低界限較佳 微米。當無機填充劑之直徑低於此範圍時,該爭舛二_ 難以提供預期的流動性。該無機填充劑之直徑::=會 更佳為不小於〇·3微米’特佳為不小於0.5微米。 黏度及改善嵌入樹脂之填充比例,可擴大顆粒大:心低1245593 V. Description of the invention (4) 50: Application: = The diameter of the T-soluble organic filler is preferably not larger than the resin into which the resin easily flows through the gap between the thunder electrodes of the electronic part ( gap) is required. This is because when the amount of the soluble organic filler and the agent exceeds 50 micrometers, the soluble organic filler will easily block the thunder + the next day of the electronic part; the base is filled, and There is a month Qiu B ′, which results in insufficient embedded resin. There are different thermal expansion coefficients in the taxi. The diameters of Ke, Xuan Right Wing, and W are preferably not more than 30 microns, more preferably not more than 20%, and particularly preferably not more than 10 Kefeng. $ i & υ u ^ 矣 τδ 芈: Code, soil π / ν: Moreover, the embedded resin can be polished so that A can be avoided. I: The soluble organic filler to produce extremely unevenness It is better to avoid the lower range of the diameter of the fines formed by electroplating and subsequent formation of fines. It is better not to be smaller than the range. The embedded resin: less than The lower range of the diameter is more preferably not less than 0.5 micrometers. In addition to at least 3 liquid% lice resins and inorganics, in addition to adjusting the coefficient of thermal expansion: J BU t •. In addition to its pianos, these insoluble ingredients can prevent the structure of the resin from being greater than that of the solidified epoxy resin or as an inorganic filler as an aggregate. = Tree = The amount used is based on the embedded resin, and is 100% by weight, preferably 5 to 25% by weight. The weight of "5" charge is based on the embedded resin, which can be 45 to 85 li, preferably 50 to 75 weight percent, and more preferably 60 to 75 weight. Page 7 C: \ 2D-CODE \ 91- 04 \ 91100717.ptd V. Description of the invention (5) Volume percentage. When considering the fluidity of the embedded resin, it is used as a necessary additive. This series =: Oxygen resins are preferred to have low viscosity, and therefore allow the incorporation of inorganic fillers with thermal expansion coefficients such as mouth and mouth; = = = is the preferred use of -double-type epoxy resins. Compared with epoxy resin, etc., it is water glycerol ether or alicyclic). In terms of not reducing the working efficiency, t, 1 and a half (especially, heat resistance additionally makes the material of epoxy material more expensive;; system = good ^ Cnovoia,) ,,, ^ # 0 ,, ^… change :: . = Is a naphthalene resin with excellent heat resistance and moisture resistance.桝 iii ^ When using only semi-solid epoxy resins, the resulting enemies are two = increased viscosity. Therefore, for example, it is necessary to reduce the embedding tree: the filler component of the organic filler cannot be obtained at a high filling ratio 2 3 and obtained using the example of the liquid epoxy resin and the filling ratio, and a volatile solvent needs to be added. However, a volatile = = ί = will cause the generation of blister in the resin due to the residual solvent, and put it in an unfavorable state. There is no particular limitation on the inorganic fillers that are insoluble in the oxidant. However, it is crystalline silicon dioxide, fused silicon dioxide, aluminum oxide, silicon nitride, or the like. Inorganic filling by adding such a high filling ratio filler Page 8 \\ 312 \ 2d-code \ 9l-04 \ 9l100717.ptd 1245593 V. Description of the invention (6) agent, so that the thermal expansion coefficient of the embedded resin is not greater than 40ppm / it (preferably not more than 30 ppm / t, more preferably not more than 25 ppm / £ &c; c, particularly preferably not more than 20 pPm / t :, and the minimum limit is not less than 10 ppm ^ c) Can reduce the stress due to the blood _ _ poor stress of the embedded electronic parts. Concentrated packs ... The thermal expansion coefficient of the body-parts is preferably a spherical shape ... Improve the fluidity and embed the inorganic filler mainly based on SiO2 The agent is particularly good: because it is easy to obtain a spherical shape, the liquidity is further reduced, and: the amount of filling: the ratio of underfilling: fat is preferably added to two or more kinds of inorganic fillers with different shapes; The individual particles will be: The particle diameter of the inorganic filler added is smaller than that: because the embedded resin needs to pass through the gap between the electronic parts = motion. The particle diameter of the inorganic filler is preferably not greater than 30 ^ greater than 2. Micron, particularly preferably no greater than 10 microns. When the inorganic diameter exceeds 50 micrometers, the generated filler will easily block the lack of π between the electrons ^ = electrodes, causing the embedded resin to be insufficient. 7: Inserting the resin produces parts with locally different thermal expansion coefficients Serving. Further: "2 When this f resin is polished and its surface is smoothed" Ϊ2: The fine cloth produced afterwards = not more than 10 degrees / the minimum limit of the diameter of the inorganic filler is preferably micron. When the diameter of the inorganic filler is lower than this range, it is difficult to provide the desired fluidity. The diameter of the inorganic filler :: = will be more preferably not less than 0.3 micron ', and particularly preferably not less than 0.5 micron. Viscosity and filling ratio of the embedded resin can be enlarged, the particle size is large: low heart
C:\2D-CODE\91-04\9ll007l7.ptd 第9頁 1245593 五、發明說明(7) 布。 無機填充劑之表面較佳視需要以偶合劑來進行名 理。這是因為經由樹脂成分可改善無機填充劑的月 以改善嵌入樹脂之流動性。可應用於此之偶合劑以 括以石夕烧為主之偶合劑、以鈦酸鹽為主之偶合劑、 鋁酸鹽為主之偶合劑。 該實質上不溶於氧化劑之不溶成分的其他例子包 劑,例如變硬加速劑(硬化加速劑)、聚矽氧油、及 膠、反應稀釋劑及抗泡沫劑。 該硬化加速劑在基於嵌入樹脂下,其使用量為〇. 5重量百分比。 於包含合併於其中之熱硬化樹脂的嵌入樹脂的例 於此處加入硬化劑(固化劑)為必須的。該使用於此 劑的種類並未有特別地限制。然而,實際上,#佳 咪唑為主之硬化劑、以胺為主之硬化劑、以酸^為 ,劑、以熱塑性酚醛樹脂為主之硬化劑或類似者。 疋,於使用環氧樹脂做為熱硬化樹脂之例子中,告 如咪唑、胺及酸酐之液狀硬化劑時,所產生之二 易於提供低黏度、並伸盆古4丨 入 充劑。 ! I使其有利於加入例如無機填充C: \ 2D-CODE \ 91-04 \ 9ll007l7.ptd Page 9 1245593 V. Description of the invention (7) Cloth. The surface of the inorganic filler is preferably named by a coupling agent if necessary. This is because the month of the inorganic filler can be improved by the resin component to improve the fluidity of the embedded resin. Coupling agents that can be applied to this include coupling agents based on Shiyaki, coupling agents based on titanate, and coupling agents based on aluminate. Other examples of the substantially insoluble component of the oxidizing agent include a hardening accelerator (hardening accelerator), a silicone oil, and a gum, a reaction diluent, and an antifoaming agent. 5 重量 %。 This hardening accelerator is based on the embedded resin, and its amount is 0.5 weight percent. In the case of an embedded resin containing a thermosetting resin incorporated therein, it is necessary to add a hardener (curing agent) here. The kind of the agent used is not particularly limited. However, in fact, # 佳 imidazole-based hardener, amine-based hardener, acid ^ as the agent, thermoplastic phenolic resin-based hardener or the like. Alas, in the case of using epoxy resin as the thermosetting resin, when the liquid hardener such as imidazole, amine, and acid anhydride is used, the second one is easy to provide low viscosity and extend the filling agent. !! I make it advantageous to add e.g. inorganic fillers
硬化劑基於嵌入樹脂,其使用量為5至45 較佳為5至25重量百分比。 里百X 具有介於設置在形成於其中之開口之電 口之佈線電路板及填充本發明之嵌人樹脂的開口% L面處 「濕性, J例子包 以及以 *含改性 ‘應石夕 02 至3· 子中, 之硬化 使用以 主之硬 特別 使用諸 樹脂可 劑之填 卜比, 間的缺 有效地 C:\2D-C0DE\91-04\91100717.ptd 第10頁The hardener is based on an embedded resin and is used in an amount of 5 to 45, preferably 5 to 25 weight percent. Liba X has a wiring circuit board interposed between an electrical port formed in an opening formed therein and an opening filled with the embedded resin of the present invention. The surface at "L" is "wet, J example package, and modified" In the evenings 02 to 3, the hardening is based on the hardness of the master and the resin fillers are used. The gap is effectively C: \ 2D-C0DE \ 91-04 \ 91100717.ptd page 10
1245593 五、發明說明(8) 緩和歸因於組成零件之間的熱膨脹係數差之應力集中,並 因此具有極佳的可靠度。為了填充介於設置在佈線電路板 的開口與具有本發明之嵌入樹脂的開口之電子零件之間的 缺口 ,任何習知的注入方法或塗佈方法,可使用例如利用 分散劑之注入方法、屏幕印刷(s c r e e n p r i n t i n g )法及滾 動塗佈(r o 1 1 c o a t i n g)法。 關於開口,可使用打孔於基板中之穿孔、經由多層技術 形成之凹洞或類似者。關於基板,可使用所謂的核心基 板’例如F R -、4、F R - 5及B T。可使用經由在藉由夾住例如由 具有約35微米大的厚度之銅箔的pTFE之熱塑性樹脂所形成 之核心基板形成一開口所獲得之基板。可選擇地,藉形成 由一絕緣層及一佈線層之可替換層合物在一核心基板之至 少一側上所組成之集結層,及透過該核心基板與集結層形 成一開口,以獲得一基板。於此設置中,如圖丨5所示,甚 至是合電容器之多層佈線電路板,亦有利於使所謂的玻 璃-環氧複合材料(絕緣基板)的厚度減低至約 為普通產品(刚微米)之-半,以降低其高度/ 合電容之基板具有以下的優點··佈線黏著之可 降可防止大電流流動於形成在具有嵌入於此之的爭二纷 上之供電佈線。關於其他例子,可形成具有在核二:曰 嵌入之電子零件的佈線電路板(如圖3),或嵌入於%士板 之佈線電路板(如圖1 4 )。 、果…板 於本發明之佈線電路板ψ,嵌入樹脂可在苴之一 觸佈線的表面上粗糙化。這是因為在粗糙表面之微平 C:\2D-C0DE\91-04\91100717.ptd 第頁 12455931245593 V. Description of the invention (8) Alleviates the stress concentration due to the difference in thermal expansion coefficient between the component parts, and therefore has excellent reliability. In order to fill the gap between the opening provided in the wiring circuit board and the electronic part having the opening of the embedded resin of the present invention, any conventional injection method or coating method may use, for example, an injection method using a dispersant, a screen A screen printing method and a ro 1 1 coating method. As for the opening, a perforation made in a substrate, a recess formed by a multilayer technique, or the like can be used. As the substrate, so-called core substrates such as F R-, 4, F R-5 and B T can be used. A substrate obtained by forming an opening by sandwiching a core substrate formed of, for example, a thermoplastic resin of pTFE having a copper foil having a thickness of about 35 micrometers can be used. Alternatively, an assembly layer consisting of an insulating layer and a wiring layer replaceable laminate on at least one side of a core substrate is formed, and an opening is formed through the core substrate and the assembly layer to obtain an Substrate. In this setup, as shown in Figure 丨 5, even the multilayer wiring circuit board of the capacitor is also beneficial to reduce the thickness of the so-called glass-epoxy composite material (insulating substrate) to about ordinary products (just micron) The half of the board has the following advantages to reduce its height / capacitance. The wiring adhesion can be reduced to prevent large currents from flowing in the power supply wiring that is formed by the disputes embedded in it. For other examples, it is possible to form a wiring circuit board (see Figure 3) with electronic components embedded in the core 2: or a wiring circuit board (see Figure 1 4) embedded in a PCB. In the wiring circuit board ψ of the present invention, the embedded resin can be roughened on the surface where one of the wires touches the wiring. This is because the surface is slightly flat on a rough surface C: \ 2D-C0DE \ 91-04 \ 91100717.ptd Page 1245593
坦度會發揮改善嵌入樹脂對經由 黏著力之固定作用。哕# ^: 成之佈線的 乎至1 5 «半:: 較佳調整為具有自〇· 1微 米至1 5破未之表面粗糙度,更 佔么1 η本=。 又住马U · 5彳政未至1 〇微米,特 佳為1破未至8微米,又更佳為3微米至 :Tando will play a role in improving the fixing effect of the embedded resin on the adhesive force.哕 # ^: The wiring of Cheng Zhi is about 15 «Half :: It is better to adjust it to have a surface roughness ranging from 0.1 micrometer to 15 Ω, which accounts for 1 η this =. Also live in the U.S. 5 to 10 microns, particularly preferably 1 to less than 8 microns, and more preferably 3 microns to:
米至7微米。該佑蝮Μ佳Α麻所u #丄, 竹⑴疋b U 4师線私隹為貝質上藉由粗糙表面上 不平坦度所夾持。這是因為竇皙 ' 八訂 ^疋口匈灵貝上無法耩不平扫声所十 之佈線具有微小缺口或不完全黏著邱 、 生在可靠度測試中。 ^ ,本發明之佈線電路板較佳於下列方法(圖3及圖6至13)中 ,造。圖3為說明本發明之佈線電路板應用至B(jA基板之一 貫施例。首先,一核心基板(1}經由模具壓製來打孔,以 形成有預疋形狀之開口( 2 )。如圖6所示,一背條(3 ) 應用在該核心基板之一側,以防止一嵌入樹脂之滲漏。該 核心基板接著以朝下面對之背條侧設置。如圖7所示,該 電子零件(4 )接著由另一側插入開口,並設置在使用一晶 片安裝器之開口之背條的黏著側之位置中。 如圖8所示,介於設置在開口之電子零件與開口之壁之 間的缺口填充使用分散劑之本發明的嵌入樹脂(6)。於使 用環氧樹脂之例子中,基板加熱至一 1 1 〇 °C至1 8 〇 t之溫 度’以熱硬化該嵌入樹脂。該熱硬化較佳經由兩階段來達 成,例如第一加熱步驟,係於8 〇 °C至1 2 0 °C之溫度下進 行,以及第二加熱步驟,係於1 2 0 °C至1 8 0 °C之溫度下進 行。這是因為第一加熱步驟允許介於電子零件與開口之壁 之間及介於電極間所捕捉泡沫之有效去除,以及該第二加Meters to 7 microns. The 蝮 蝮 佳 麻 麻 所 u # 丄, the bamboo ⑴ 疋 b U 4 division line is privately held by shells with unevenness on the rough surface. This is because Dou Xi's eight-dimensional ^ 疋 疋 匈 匈 匈 耩 匈 匈 匈 匈 匈 耩 on the Hun Lingbei can not beat the sound of the wiring, the wiring has a small gap or incomplete adhesion Qiu, born in the reliability test. ^ The wiring circuit board of the present invention is preferably manufactured in the following method (FIG. 3 and FIGS. 6 to 13). FIG. 3 is an example of a conventional application of the wiring circuit board of the present invention to a B (jA substrate. First, a core substrate (1) is punched through a die to form a pre-shaped opening (2). As shown in FIG. As shown in FIG. 6, a backing strip (3) is applied to one side of the core substrate to prevent leakage of an embedded resin. The core substrate is then disposed to face the backing strip side facing downward. As shown in FIG. 7, the The electronic component (4) is then inserted into the opening from the other side, and is set in the position of the adhesive side of the back strip using the opening of a chip mounter. As shown in FIG. The gap between the walls is filled with the embedding resin (6) of the present invention using a dispersant. In the case of using an epoxy resin, the substrate is heated to a temperature of 110 ° C to 180 ° t to thermally harden the embedding. Resin. This thermal hardening is preferably achieved in two stages, for example, the first heating step is performed at a temperature of 80 ° C to 120 ° C, and the second heating step is performed at 120 ° C to 18 ° C. This is because the first heating step allows between Between the wall and the opening of the sub-components between the captured between the electrodes and effective removal of the foam, and the second plus
C:\2D-CODE\91-04\91100717.ptd 第12頁 1245593 月說明⑽~ " —-— 熱步驟接著允許嵌入樹脂在無泡沫之良好狀態中硬化。 槪如圖9所示,該因此硬化之嵌入樹脂的表面接著利用一 f狀磨矽機來將粗糙拋光,以及藉由重疊拋光來完成拋 光,以f使其變平滑而形成一平滑表面(6 〇 )。如圖丨〇所 不,该嵌入樹脂之表面接著以二氧化碳氣體雷射或YAg雷 射來照射,以致使其可部分去除而形成一用於輸送之通孔 (7),如此會讓嵌入於嵌入樹脂之電子零件的電極露出。 而可從電子零件之電極獲得一佈線。 違肷入樹脂之平滑表面(6 〇 )的粗糙化係經由使用一氧化 =之粗I化步驟來完成。關於將使用於粗糖化步驟之氧化 剡,可使用任何習知的氧化劑,例如以高锰酸鹽為主之氧 化劑(諸如ΚΜη04、HMn〇4)、以鉻酸鹽為主之氧化劑(諸如 以〇3、K2Cr2〇7、K2Cr04、KCr03Cl、Cr02Cl2)、以硝酸鹽為主 之氧化劑(諸如HN〇3、N2 04、N2 03、N20、Cu(N03)2、Pb(N03)2 、AgN03、KNH4N03)、以鹵素為主之氧化劑(諸如匕、C1g、 Brs、I。、以過氧化物為主之氧化劑(諸如扎%、Na2〇2、C: \ 2D-CODE \ 91-04 \ 91100717.ptd Page 12 1245593 Description ~~ The thermal step then allows the embedded resin to harden in a good state without foam.槪 As shown in FIG. 9, the surface of the thus hardened embedded resin is then rough polished using an f-shaped silicon grinder, and polished by overlapping polishing to smooth it with f to form a smooth surface (6 〇). As shown in Figure 丨, the surface of the embedded resin is then irradiated with a carbon dioxide gas laser or YAg laser, so that it can be partially removed to form a through hole (7) for transportation, which will allow the embedded in the embedded The electrodes of resin electronic parts are exposed. A wiring can be obtained from the electrodes of the electronic component. The roughening of the smooth surface (60) of the resin is performed by using a roughening step using an oxidation step. As for the thorium oxide to be used in the crude saccharification step, any conventional oxidant may be used, such as a permanganate-based oxidant (such as KMη04, HMn〇4), a chromate-based oxidant (such as 3.K2Cr2〇7, K2Cr04, KCr03Cl, Cr02Cl2), nitrate-based oxidants (such as HN〇3, N2 04, N2 03, N20, Cu (N03) 2, Pb (N03) 2, AgN03, KNH4N03) , Halogen-based oxidants (such as dagger, C1g, Brs, I.), peroxide-based oxidants (such as Zr%, Na202,
Ba02、(C6H5C0 )202 )、以過酸(peracid)為主之氧化劑(諸如Ba02, (C6H5C0) 202), peracid-based oxidants (such as
Na2S2 08、Na2S05、K2S2 08、K2S05、HCQ3H、CH3C03H、C6H5C03H 、c6h4(cooh)co3h、cf3co3h)、以硫酸鹽為主之氧化劑(諸 如熱濃硫酸、發煙硫酸+濃硝酸)、以含氧酸(oxygen acid)為主之氧化劑(諸如、NaC1〇、KBr〇、NaBr〇、 KIO、NaIO、KC103、NaC103、KBr04、NaBr04、KI04、NaI04 、HI04、Na3N2106)、金屬氧化劑(諸如FeCl3、Cus〇4、Na2S2 08, Na2S05, K2S2 08, K2S05, HCQ3H, CH3C03H, C6H5C03H, c6h4 (cooh) co3h, cf3co3h), sulfate-based oxidants (such as hot concentrated sulfuric acid, fuming sulfuric acid + concentrated nitric acid), and oxo acids (Oxygen acid) -based oxidants (such as NaC10, KBrO, NaBr〇, KIO, NaIO, KC103, NaC103, KBr04, NaBr04, KI04, NaI04, HI04, Na3N2106), metal oxidants (such as FeCl3, Cus〇4 ,
Cu(CH3COO)2、CuCl2、Hg(CH3COO)2、Bi(CH3COO)3、Cu (CH3COO) 2, CuCl2, Hg (CH3COO) 2, Bi (CH3COO) 3,
C:\2D-C0DE\91-04\91】00717.ptd 第13頁 1245593 五、發明說明(η)C: \ 2D-C0DE \ 91-04 \ 91】 00717.ptd Page 13 1245593 V. Description of the invention (η)
Pb(CH3COO)4)、以氧為主之氧化劑(諸如 二::氧化物為主之氧化劑(諸如c二 θ 3、〇叫、副4、Se〇2、_、A4)。特別 豳-^踐A用士諸如以驗_過錳酸鹽為主之氧化劑、以鉻酸 I气Hr為 氧化劑、以鉻酸鹽—硫酸鹽-氣化納為主 羊刎及以溴氟酸鹽-二鉻酸鹽為主之氧化劑之混厶氧 ::化因為其可完全地將主要由環氧樹二,二 的自為粗糙化前及後之接近礙入樹脂之拋光表面 用1於l!面圖。該可溶樹脂或可溶有機填充劑’如可利 氧St3丨2Γ入樹脂(6)之氧化劑來溶解之成分(3〇),係以 :::而形成一洗提部分(32)。因此,由微小不平坦 "^成之粗糙表面(61 )係形成於嵌入樹脂之暴露表面 電度會發揮固定作用’使其可提供對於經由無 佈i且;箱Γ etCtr〇lytlC Plating)過程而隨後形成之 液妝二#抖4黏著力之嵌入樹脂。該嵌入樹脂較佳包含一 树脂或-無機填充劑,其係結合於此並做為實質 袓ίΓΪ乳化劑之不可溶成分’以調整其熱膨服係數或在 粗糙化後,防止其本身脫離所須之形狀。 ,糙表面(61 )以包含氯化把溶液之化學品來活化,以及 耆以銅進行無電鍍膜(未顯示)。隨後,該粗糙表面(6】) 糸以銅進行無電鍍膜,以形成如圖丨丨所示之面板堆積 = nel dep〇sit)(9)。由於在電鍍步驟利用銅來填充通孔 ),以形成如圖11所示之接觸導體(via c〇nduct〇rK8) 第14頁 C:\2D-CODE\91-04\91100717.ptd 1245593 五、發明說明(13) 類似者。除了使用粗糙化後經由面板電鍍而獲得之列舉的 核心基板之外,一預先以銅箔來鍍層之鍍銅核心基板可使 用於完成本發明之目的。該基板之厚度並未有特別地限 制,但較佳幾乎等於或稍大於電子零件之厚度。在製造多 層佈線電路板之例子中,可使用將用於習知集結方法或層 合方法之絕緣層。可使用一熱硬化樹脂、一熱塑型樹脂、 一感光樹脂或其之混合物或改性產品。該等樹脂之特殊例 子包含環氧樹脂,諸如雙酚型環氧樹脂及熱塑性酚醛型樹 · 脂環氧樹脂、環氧丙烯酸酯樹脂、鐵氟龍樹脂、液狀結晶 聚合物、PPS樹脂及PPE樹脂。 · 該電子零件之例子包含晶片電阻器(chip resist〇r)、 i 曰曰片電谷器以及晶片感應器(chip inductor)。該等電子 零件係較佳為陶製層合(ceramic-laminated)形式,因為 其甚至在小尺寸形式中亦具有足夠的容量。從嵌入於該嵌 入樹脂之電子零件的電極之陶瓷材料的表面延伸至該嵌入 樹脂之表面之該突出物d(圖5中之元件編號50)較佳至少在 設置有半導體之基板的一側為2 0微米至1 5 0微米。較佳 地,對於在電子零件之兩側上的電極,該突出物d係為2 〇 微米至1 5 0微米。這是因為該嵌入樹脂可完全地透過介於 該電子零件之兩側上之電極間的缺口而流動。當電極突出 · 物落在此範圍之下時,於該嵌入樹脂之填充劑藉由該缺口 而被捕捉’故使其難以填充該缺口。反之,當該電極突出 物超過此範圍時,該所產生之應力會造成電極本身易於脫 離而不利於可靠度。Pb (CH3COO) 4), oxygen-based oxidants (such as two :: oxide-based oxidants (such as c two θ 3, 〇 called, vice 4, Se〇2, _, A4). Special 豳-^ Practices such as oxidants based on permanganate, chromic acid I and Hr as oxidants, chromate-sulfate-vaporized sodium as main lamella, and bromofluorate-dichromate Oxide mixed with oxygenate as the main oxidant :: because it can completely use the epoxy resin two, two before and after the roughening of the access to the resin's polished surface with 1 to 1! The soluble resin or soluble organic filler, such as the component (30) dissolved in the oxidant of the resin (6) into the resin (6), is formed by using ::: to form an elution portion (32). Therefore, the rough surface (61) formed by the micro unevenness is formed on the exposed surface of the embedded resin, and the electric energy will play a fixed role, so that it can provide a process for passing through the cloth and the box. And then the formation of the liquid makeup II # shaking 4 adhesive resin embedded. The embedded resin preferably contains a resin or an inorganic filler, which is incorporated here as a substantially insoluble component of the emulsifier to adjust its thermal expansion coefficient or prevent it from leaving itself after being roughened. Beard shape. The rough surface (61) is activated with a chemical containing the solution, and the electroless plating film (not shown) is made of copper. Subsequently, the rough surface (6)) is electroless-plated with copper to form a panel stack as shown in FIG. 丨 (nel deposit) (9). Because copper is used to fill the vias in the plating step) to form a contact conductor (via c〇nduct〇rK8) as shown in Figure 11 Page 14 C: \ 2D-CODE \ 91-04 \ 91100717.ptd 1245593 V. Invention Description (13) Similar. In addition to using the enumerated core substrates obtained by panel plating after roughening, a copper-plated core substrate plated with copper foil in advance can be used to accomplish the object of the present invention. The thickness of the substrate is not particularly limited, but is preferably almost equal to or slightly larger than the thickness of the electronic component. In the example of manufacturing a multi-layer wiring circuit board, an insulating layer to be used for a conventional assembly method or a lamination method may be used. A thermosetting resin, a thermoplastic resin, a photosensitive resin, or a mixture or modified product thereof may be used. Specific examples of these resins include epoxy resins such as bisphenol-type epoxy resins and thermoplastic phenol-type resins, epoxy resins, epoxy acrylate resins, Teflon resins, liquid crystalline polymers, PPS resins, and PPE Resin. Examples of the electronic component include a chip resistor, a chip resistor, and a chip inductor. These electronic parts are preferably in ceramic-laminated form because they have sufficient capacity even in small-sized forms. The protrusion d (element number 50 in FIG. 5) extending from the surface of the ceramic material of the electrode of the electronic component embedded in the resin to the surface of the embedded resin is preferably at least on the side where the semiconductor is provided. 20 microns to 150 microns. Preferably, for the electrodes on both sides of the electronic part, the protrusion d is 20 μm to 150 μm. This is because the embedded resin can completely flow through the gap between the electrodes on both sides of the electronic part. When the electrode protrusions fall below this range, the filler embedded in the resin is captured by the gap ', making it difficult to fill the gap. On the contrary, when the protrusion of the electrode exceeds this range, the generated stress will cause the electrode itself to be easily detached, which is not conducive to reliability.
C:\2D-CODE\91-04\91100717.ptdC: \ 2D-CODE \ 91-04 \ 91100717.ptd
12455931245593
該電極突出物較佳為3〇 ::流性;並使嵌人 斗& 土興電子零件之間的缺口變為可处 以二子零件之電極的表面具有〇 · 3微米至2 〇微、米此 又,較佳為0 · 5微米至1 〇微米, ^ ;a、 這是因為嵌入樹脂可經由在電極更之佳表= = : = =間ΐ黏著力的固定作用。用於控制粗糙 又之方法並無特別地限制。可使用任何習知的 如微蝕刻及變暗(blackening)方法。 烫ί 之佈線電路板係允許設置-半導體幾乎於該電子 於此處所使用之「幾乎於…上(實質上於…上)」之意義 為顯示一不僅包含該半導體正好設置於電子零件的上方之 狀悲’亦包含該半導體正好只設置於連接至該半導體之電 子零件之電極周圍的上方之狀態的觀念。這是因為當該半 ::φ ΐ ’以及因此可減低其面#。例如,藉由再佈線電 路板中肷入一晶片電容器,以致使其結合於該佈線電路板 而形成一去偶合電容器’可減低由供電層及接地層至咳去 偶合電容器之佈線的長度,以減低額外的感應係數 (1 nductance),並使有效地減低開關噪音變為可能。 導體之電極及該電子零件之電極在適當位置時,以致使該 等電極可經由該接觸導體而幾乎彼此垂直地連接,因而可 獲得描述於前述段落之作用。 可經由例如以下方法(圖15至29)製造包含一基板之多層The electrode protrusion is preferably 30 :: fluid; and makes the gap between the embedded human & Tuxing electronic parts become usable. The surface of the electrode of the two sub-parts has 0.3 micrometers to 2 micrometers, meters. In this case, it is preferably 0.5 μm to 10 μm, ^; a. This is because the embedding resin can fix the adhesive force through the better surface of the electrode. The method for controlling the roughness is not particularly limited. Any conventional method such as micro-etching and blackening can be used. The wiring circuit board is allowed to be placed-the semiconductor is almost the same as the word "almost on" (substantially on) used by the electron here to indicate that it contains not only the semiconductor just above the electronic part The state of sadness also includes the concept that the semiconductor is disposed only just above the periphery of an electrode of an electronic component connected to the semiconductor. This is because when the half :: φ ΐ 'and thus its face # can be reduced. For example, by inserting a chip capacitor into the rewiring circuit board so that it is combined with the wiring circuit board to form a decoupling capacitor, 'the length of the wiring from the power supply layer and the ground layer to the decoupling capacitor can be reduced, so that Reduces additional inductance (1 nductance) and makes it possible to effectively reduce switching noise. When the electrodes of the conductor and the electrodes of the electronic component are in place so that the electrodes can be connected almost perpendicularly to each other via the contact conductor, the effects described in the preceding paragraph can be obtained. A multilayer including a substrate can be manufactured by, for example, the following method (FIGS. 15 to 29)
1245593 五、發明說明(15) 佈線電路板,而該基板係藉由在一核心基板之至少一側上 形成由一絕緣層及一佈線層之交替層合物’以及透過核心 基板及集結層形成一開口來獲得。該製造方法將參照圖1 5 所示之所謂的「FC-PGA」基板之具體例於下文中敘述。 如圖1 6所示,製造一鍍有厚度1 8微米之銅箔(2 0 0 )且具 有厚度0· 4微米之絕緣基板(1 〇〇)的FR-5雙側鍍銅核心基 板。關於此處所使用之核心基板之性質,藉TMA所定義之 Tg(玻璃轉換點)為175 t:,沿著基板之表面的CTE(熱膨脹 係數)為1 6 ppm/ °C,在垂直於基板之表面之方向中的 CTE(熱膨脹係數)為5〇ppm/ °c,於1兆赫下之介電常數ε為 4. 7,以及於1兆赫下之tan 6為0· 018。 該核心基板係經由一已黏著於此之抗光蝕劑薄膜來暴露 至光中,以及接著發展以形成一具有60 0微米之直徑的開 口以及具有相對於該佈線之預定形狀之形狀的開口(未顯 示)。暴露於抗光蝕劑薄膜之開口的銅箔接著利用一包含 亞硫酸鈉及硫酸之蝕刻溶液來蝕刻去除。該抗光蝕劑薄膜 然後從核心基板剝離,已獲得一具有如圖丨7所顯示之暴露 部分(3 0 0 )之核心基板,以及一具有相對於形成於其上之 佈線之預定形狀的暴露部分(未顯示)。 該核心基板然後利用 市售可獲得之蝕刻裝置(MEC公司 所製造之CZ處理荔)來進行蝕刻,以致使該鋼箔於其表面 上粗化。一具有厚度35微米且主要由環氧樹脂所組 絕緣薄膜接著黏著至該核心基板之兩側。該 之溫度下接受u小時之硬化,以於其上形成=1245593 V. Description of the invention (15) Wiring circuit board, and the substrate is formed by forming an alternating laminate of an insulating layer and a wiring layer on at least one side of a core substrate, and forming the core substrate and the build-up layer through An opening to get. This manufacturing method will be described below with reference to a specific example of the so-called "FC-PGA" substrate shown in FIG. 15. As shown in FIG. 16, a FR-5 double-sided copper-plated core substrate plated with a copper foil (200) having a thickness of 18 microns and an insulating substrate (100) having a thickness of 0.4 microns was manufactured. Regarding the properties of the core substrate used here, the Tg (glass transition point) defined by TMA is 175 t :, the CTE (coefficient of thermal expansion) along the surface of the substrate is 16 ppm / ° C, and the The CTE (coefficient of thermal expansion) in the direction of the surface was 50 ppm / ° C, the dielectric constant ε at 1 MHz was 4.7, and the tan 6 at 1 MHz was 0.018. The core substrate is exposed to light through a photoresist film that has been adhered thereto, and then developed to form an opening having a diameter of 600 micrometers and an opening having a shape corresponding to a predetermined shape of the wiring ( Not shown). The copper foil exposed to the opening of the photoresist film is then removed by etching with an etching solution containing sodium sulfite and sulfuric acid. The photoresist film is then peeled from the core substrate to obtain a core substrate having an exposed portion (300) as shown in FIG. 7 and an exposure having a predetermined shape with respect to the wiring formed thereon. Section (not shown). The core substrate was then etched using a commercially available etching device (CZ-treated Li manufactured by MEC Corporation), so that the steel foil was roughened on its surface. An insulating film having a thickness of 35 microns and mainly composed of epoxy resin is then adhered to both sides of the core substrate. Accepted for u hours of hardening at this temperature to form on it =
第18頁 1245593 五、發明說明(16) ----- $。關於因、此硬化之絕緣層的性質,藉TMA所測定之以(玻 ^轉換點)為155(:,藉1^所測定之丁2(玻璃轉換點)為2〇4 CTE( 4知服係數)為66 它,於1兆赫下之介電係 數ε為3· 7,於1兆赫之tan 5為0.0 33,於3 0 0 t下之重量 減少率為,1〇·1%,水吸收率為0.8%,吸濕率為1%,揚格模 數(Young’ s modulus)為3千兆赫,張力強度為63百萬帕以 及伸長率為4. 6%。 如圖1 8所不’該基板利用二氧化碳氣體雷射光束來照 射’以形成一於該絕緣層(4〇〇)中用來中間層連接之通孔 (5 0 0 )。該通孔於其上部為具有丨2 〇微米直徑之圓錐體形 式,以及其底部為具有6 0微米直徑之圓錐體形式。藉提昇 二氧化碳氣體雷射之輸出,經由該絕緣層及該核心基板來 开乂成具有300微米直徑之穿孔(6〇〇)。該穿孔之内壁具有雷 射處理之波盪(未顯示)特性。將該基板浸泡於包含氯化鈀 之催化活化溶液,以及接著於其整個表面上進行無電鍍銅 (未顯示)。 接下來,該基板接受銅面板電鍍(7 〇 〇 )至1 8微米之厚 度。在通孔中形成一用來電連接該等層之接觸導體 (8 0 0 )。在該通孔中亦形成一用於電連接介於該基板之表 面與另一表面之間的穿孔導體(900)。使用市售可得之雀虫 刻裝置(經由MEC公司製造之CZ處理器),該基板接著進行 姓刻,以致使銅沉積於其表面上粗糙化。於下文中,該銅 沉積利用MEC公司所製造之防銹器進行防銹處理(商品名: c Z處理),以形成一疏水性表面以及完成疏水性。相對於Page 18 1245593 V. Description of Invention (16) ----- $. With regard to the properties of this hardened insulating layer, the (glass transition point) measured by TMA is 155 (: the D2 (glass transition point) measured by 1 ^ is 20.0 CTE (4 know service Coefficient) is 66, its dielectric coefficient ε is 1 · 7 at 1 MHz, tan 5 is 0.0 33 at 1 MHz, and the weight reduction rate at 3 0 0 t is 10.1%, water absorption The rate is 0.8%, the moisture absorption rate is 1%, the Young's modulus is 3 GHz, the tensile strength is 63 million Pa and the elongation is 4.6%. The substrate is irradiated with a laser beam of carbon dioxide gas to form a through hole (500) in the insulating layer (400) for intermediate layer connection. The through hole has a thickness of 20 μm on the upper portion thereof. The diameter of the cone form, and the bottom is a cone form with a diameter of 60 microns. By increasing the output of the carbon dioxide gas laser, through the insulation layer and the core substrate to open a perforation with a diameter of 300 microns (60. 〇). The inner wall of the perforation has the characteristics of undulation (not shown) of laser treatment. The substrate is immersed in a catalytic activation containing palladium chloride And then electroless copper plating (not shown) on its entire surface. Next, the substrate is subjected to copper panel plating (700) to a thickness of 18 microns. A through hole is formed to electrically connect the substrates. Layer of the contact conductor (800). A through-hole conductor (900) for electrically connecting the surface of the substrate and the other surface is also formed in the through hole. A commercially available bird engraving is used. Device (via the CZ processor manufactured by MEC), the substrate is then engraved so that the copper deposit is roughened on its surface. In the following, the copper deposit is rust-prevented by a rust preventer manufactured by MEC. (Trade name: c Z treatment) to form a hydrophobic surface and complete hydrophobicity.
\\312\2d-code\91-04\91100717.ptd 第19頁 1245593 五、發明說明(17) 水之該導體層之疏水性表面的接觸角2 Θ係接著藉由使用 一接觸角量測計(商品名:CA-A,由Kyowa Interface Science公司所製造)之液體滴下(Hquid dropping)方法 來測量。因此,該接觸角2 Θ為1 0 1。。 一非纖維紙接著放置於裝設有真空吸引裝置之臺座上。 該鈾述基板接著置於臺座上。一在相對於其之穿孔的適當 位置中具有穿孔之不銹鋼填充孔罩係置於基板上。接下 來’用於填充穿孔且包含銅填充劑之糊狀物置放於該罩 上。該穿孔接著於軋輥橡膠滾筒之壓力下利用該糊狀物來 填充。 如圖1 9所示,用於填充穿孔且裝滿該穿孔之糊狀物 ( 1 0 0 0 )係於12 0 °C之溫度下係暫時性地硬化2〇分鐘。接下 來,如圖2 0所示,该核心基板之表面利用一帶狀磨砂機 (粗糙拋光)來抛光,以及接著進行擦亮(buf f ing)(完成拋 光)’以致使其變平滑(未顯示)。該糊狀物接著於1 5 〇 〇c之 溫度下硬化5小時’以完成該填充步驟。已完成於該填充 步驟之基板係部分使用於針對填充性質之評估測試。 如圖2 1所示,一具有8毫米見方之尺寸的穿孔(丨丨〇 )係利 用一模具(未顯示)來形成。如圖2 2所示,一護條(丨2 〇 )係 黏著至該基板之一側。接下來,如圖23所示,8層合晶片 電谷器(130)係放置於暴露在使用一晶片安裳器之穿孔 (11 0 )之濩條上。该專層合晶片電容器分別由各自具有1 · 2 毫米X 0.6毫米X 0·4毫米尺寸之層合材料(15〇)。一由層 合材料突出之電極(1 4 0 )為7 〇微米。 θ\\ 312 \ 2d-code \ 91-04 \ 91100717.ptd Page 19 1245593 5. Description of the invention (17) The contact angle 2 of the hydrophobic surface of the conductive layer of water 2 Θ is then measured by using a contact angle The meter (trade name: CA-A, manufactured by Kyowa Interface Science) was measured by a liquid dropping method. Therefore, the contact angle 2 Θ is 1 0 1. . A non-fiber paper is then placed on a pedestal equipped with a vacuum suction device. The uranium substrate is then placed on a pedestal. A stainless steel filled escutcheon with perforations in place relative to its perforations is placed on the substrate. Next, a paste containing copper filler for filling the perforations is placed on the cover. The perforations are then filled with the paste under the pressure of a roll rubber roller. As shown in FIG. 19, the paste (100 000) used to fill the perforations and filled with the perforations is temporarily hardened for 20 minutes at a temperature of 120 ° C. Next, as shown in FIG. 20, the surface of the core substrate is polished using a belt sander (rough polishing), and then buff fing (complete polishing) is performed to make it smooth (unfinished). display). The paste was then hardened at a temperature of 15 ° C for 5 hours' to complete the filling step. The part of the substrate that has been completed in the filling step is used for the evaluation test of the filling property. As shown in FIG. 21, a perforation (丨 丨 〇) having a size of 8 mm square is formed using a mold (not shown). As shown in FIG. 22, a guard strip (丨 20) is adhered to one side of the substrate. Next, as shown in FIG. 23, the 8-layer wafer electric valley device (130) is placed on a purlin exposed to a perforation (110) using a wafer device. The dedicated laminated chip capacitors are each made of a laminated material (15) having dimensions of 1.2 mm x 0.6 mm x 0.4 mm. An electrode (140) protruding from the laminated material is 70 microns. θ
1245593 五、發明說明(18) 如圖2 4所示,其中設有層合晶片電容器之穿孔係利用一 分散器(未顯示)以本發明之嵌入樹脂來填充。該嵌入樹脂 係於8 0 °C之溫度下接受第一加熱步驟歷經3小時,以及接 著在1 70 °C之溫度下接受第二次加熱歷經6小時,以進行消 泡及熱硬化。 如圖2 5所示,因此硬化之嵌入樹脂的表面係利用一帶狀 磨砂機來進行一粗糙拋光,以及接著經由重疊拋光來完成 抛光。該晶片電容器之電極的末端面係暴露於該嵌入樹脂 之拋光表面。接下來,該已暫時性硬化的嵌入樹脂係於 1 5 0 C之溫度下硬化5小時。 方;下文中’ 5亥攸入樹脂之抛光表面係以一溶服溶液及 KMn〇4溶液來進行粗糙化。該嵌入樹脂之粗糙表面係經由 一 Pd催化劑來活化,利用銅來無電鍍膜,以及接著利用銅 來電鑛。如圖2 6所示,形成於該嵌入樹脂上之沉積物係電 連接至該晶片電容器之電極的末端面。一抗光钱劑係形成 於違肷入树月曰之電錢表面上。關於此抗光钱劑,一預定的 佈線圖樣係形成於該嵌入樹脂之電鍍表面上。該不必要的 銅利用N 〇8 /濃硫酸來钱刻去除。該抗光钱劑係由該拔 入樹脂來剝離,以完成如圖2 7所示之佈線形成。利用市售 可獲得之蚀刻裝置(由MEC公司所製造之CZ處理器),該嵌 入樹脂接著接受蝕刻,以致使該鍍銅佈線於其表面上粗糙 化。 一做為絕緣溥膜之薄膜(丨9 〇 )係於該鍍銅佈線之粗糙表 面上層合,以及接著進行熱硬化。該絕緣薄膜係以二氧化1245593 V. Description of the invention (18) As shown in FIG. 24, the perforation provided with the laminated chip capacitor is filled with a disperser (not shown) with the embedded resin of the present invention. The embedded resin was subjected to a first heating step at a temperature of 80 ° C for 3 hours, and then a second heating at a temperature of 1 70 ° C for 6 hours to perform defoaming and heat curing. As shown in Fig. 25, the surface of the hardened embedded resin is thus rough-polished using a belt sander, and then polished by overlapping polishing. The end face of the electrode of the chip capacitor is exposed to the polished surface of the embedded resin. Next, the temporarily hardened insert resin was hardened at a temperature of 150 ° C for 5 hours. In the following, the polishing surface of the ‘50 helium resin is roughened with a solvent solution and a KMn0 4 solution. The rough surface of the embedded resin was activated by a Pd catalyst, electroless plating was performed using copper, and copper was then used to deposit the metal. As shown in FIG. 26, the deposit formed on the embedded resin is electrically connected to the end face of the electrode of the chip capacitor. An anti-light money agent is formed on the surface of the electric money which is invaded into the tree. Regarding the light-resistant agent, a predetermined wiring pattern is formed on the plating surface of the embedded resin. The unnecessary copper is removed by using No. 8 / concentrated sulfuric acid. The anti-light money agent is peeled off by the pulled-in resin to complete the wiring formation as shown in FIG. Using a commercially available etching device (CZ processor manufactured by MEC Corporation), the embedded resin was then subjected to etching so that the copper-plated wiring was roughened on its surface. A thin film (9o), which is an insulating film, is laminated on the rough surface of the copper-plated wiring, followed by thermal curing. The insulating film is based on dioxide
12455931245593
碳氣體雷射光束來照射,以形成一用來插入連接其中之通 孔。該絕緣層之表面係以上述所使用之相同氧化劑來粗糙 化。一預定佈線(2 〇 1)係形成於上述之相同方式中。一做 為抗焊料層之乾薄膜係接著層合於該佈線電路板之最上層 上。該乾薄膜係經由半導體元件裝設圖樣而暴露於光中, 以及接著培養以完成一抗焊料層(2丨〇)之形成。一預定佈 線( 230 )及一抗焊料層(24〇)亦形成於該佈線電路板之表面 上’於其上設有裝設引線,以獲得一未設有如圖2 8所示之 引線的多層印刷電路板。 於其上裝設有半導體之末端電極(2 〇丨)係利用N丨來電 錢’以及接著以Au來電鍍(未顯示)。一由低溶解焊料所製 成之焊料糊接著印刷於佈線電路板上。該佈線電路板接著 通過一焊料回流爐,以形成一用於裝設半導體之焊料凸塊 (220)。 換言之’一由高溶解焊料所製成之焊料糊係印刷於該佈 線電路板之表面上’該表面係於裝設有半導體之表面的對 面。該佈線電路板接著通過一焊料回流爐至一用來裝設引 線之焊料凸塊(2 6 0 )。該佈線電路板然後通過一焊料回流 爐’同時放置於裝設在固定裝置(未顯示)上之引線(25〇) 上,以於其中裝設引線(未顯示)。因此,如圖2 9所示,獲 得一FC-PGA型多層印刷電路板,其係準備安裝半導體元 件。利用一投射器(pro]· ector),從該預定位置測量該裝 設在相對於以該嵌入樹脂填充之開口之區域引線之前端的 位置之誤差。此結果係不大於〇·丨毫米。甚至當利用一大A carbon gas laser beam is irradiated to form a through-hole for insertion into the connection. The surface of the insulating layer is roughened with the same oxidant used above. A predetermined wiring (201) is formed in the same manner as described above. A dry film as a solder resist layer is then laminated on the uppermost layer of the wiring circuit board. The dry film is exposed to light via a pattern of the semiconductor device, and is then cultured to complete the formation of a solder resist layer (2o). A predetermined wiring (230) and a solder-resistant layer (24) are also formed on the surface of the wiring circuit board. There are mounting leads provided thereon to obtain a multilayer without the leads shown in FIG. 28. A printed circuit board. A terminal electrode (20 丨) on which a semiconductor is mounted is charged by N 丨 and then plated with Au (not shown). A solder paste made of a low-solubility solder is then printed on the wiring circuit board. The wiring circuit board is then passed through a solder reflow furnace to form a solder bump (220) for mounting a semiconductor. In other words, "a solder paste made of a highly soluble solder is printed on the surface of the wiring circuit board" and the surface is opposite to the surface on which the semiconductor is mounted. The wiring circuit board is then passed through a solder reflow oven to a solder bump (2 60) for mounting leads. The wiring circuit board is then simultaneously placed on a lead (25) mounted on a fixture (not shown) through a solder reflow oven 'to mount leads (not shown) therein. Therefore, as shown in FIG. 29, an FC-PGA type multilayer printed circuit board is obtained, which is ready to be mounted with a semiconductor element. An error of the position of the device relative to the front end of the lead of the area filled with the embedded resin is measured from the predetermined position using a projector. The result is no more than 0 · 丨 mm. Even when using a large
1245593 、發明說明(20) 電流進行重複供給能量, ^ 之佈線係未經歷諸如钿齙》成於該嵌入樹脂上並用於供電 割離之缺陷。 半導體元件(27〇)係於 板之裝設表面上。該佈綠违衣6又位置中設置於該佈線電路 解之溫度條件下通過一焊枓路板接者於僅有低溶解焊料熔 體元件。該裝設部分接㈣’以於其中裝設-半導 填n j滿材料然後熱硬化 = 於其中之半導體元件的代―ΡΑΓ^夕^^又行匕3”有哀叹 PAG型多層印刷電路板之丰 裝置,如圖1 5所示。 | w电峪极惑牛V體 J發::以藉ί下列的範例來做更進-步的敘述。嵌入 ,的ΐ :可以精由測量諸如在表1中所提出的各種組成 成分,混δ上述的組成成分,並接著藉由一種具有三組滾 軸的研磨機之裝置來搓揉上述的混合物。在表丨中所描述 的細節如下。 環氧樹脂 *液態ΒΡΑ :雙酚Α型環氧樹脂(YL980,由日本環氧樹 脂股份有限公司所製造) * π液態BPF1’ ··雙酚F型環氧樹脂(YL983U,由日本環氧 樹脂股份有限公司所製造) *’'半固態評’’:萘型環氧樹脂(1^-40320,由〇人01??(^ INK & CHEMICALS公司所製造) * 固態CN” :曱酚熱塑性酚醛型環氧樹脂(EOCN103,由 NIPPON KAYAKU股份有限公司所製造)+溶劑(乙二醇二甲 醚)1245593, Description of the invention (20) The current is repeatedly supplied with energy, and the wiring of ^ has not experienced defects such as that formed on the embedded resin and used for power supply separation. The semiconductor element (27) is mounted on the mounting surface of the board. The cloth green cloth 6 is placed in a position where the wiring circuit is decomposed, and is connected by a soldering circuit board to only a low-solubility solder melt component. The installation part is connected to the semiconductor device filled with nj filled material and then thermally hardened = the generation of the semiconductor element in it-"PΑΓ ^ 夕 ^^ 行行 3" There are laments of PAG type multilayer printed circuit boards Device, as shown in Figure 15. | wElectronically confused cow V body J hair :: Take the following example to make a further-step narrative. Embedding the ΐ: You can precisely measure such as in the table The various constituents proposed in 1 are mixed with the above-mentioned constituents, and then the above-mentioned mixture is kneaded by a device of a grinder having three sets of rollers. The details described in Table 丨 are as follows. Epoxy Resin * Liquid BPA: Bisphenol A epoxy resin (YL980, manufactured by Japan Epoxy Resin Co., Ltd.) * πLiquid BPF1 '· Bisphenol F epoxy resin (YL983U, manufactured by Japan Epoxy Resin Co., Ltd. (Manufactured by the company) * "Semi-solid evaluation": naphthalene-type epoxy resin (1 ^ -40320, manufactured by 〇 person 01 ?? (made by INK & CHEMICALS) * solid CN ": acetol thermoplastic phenolic type Epoxy resin (EOCN103, manufactured by NIPPON KAYAKU Co., Ltd.) + solvent (Ethylene glycol dimethyl ether)
C:\2D-0QDE\91-04\91100717.ptd 第23頁 1245593 五、發明說明(21) *上述的溶劑成分並未包含在表1中所敘述的重量百八 比濃度。 77 硬化劑 * S义酐:以酸酐為基礎的硬化劑(E p i c u r e Υ Η 3 0 7,由 曰本環氧樹脂股份有限公司所製造) 硬化加速劑 * π咪唾π ••以咪唑為基礎的硬化劑(2E4MZ-CN,由 SHIKOKU化學藥品公司所製造) 有機填充劑 * Π橡膠填充劑π ••以橡膠為基礎的填充劑(XER-91,由 JSR所製造) 液態橡膠 * π已改性環氧”:已改性環氧丁二烯橡膠(E-1〇〇〇_8. 〇 ,由N IPP0N石油化學股份有限公司所製造) 無機填充劑 * π氧化矽(直徑Φ : 24微米)π :經過矽烷偶合處理的氣 化矽(Tasumori PLV-6,在顆粒尺寸分布方面,最大的顆 粒直徑:24微米) * ”氧化矽(混合物)π ··經過矽烷偶合處理的氧化矽 (7:3(重量比),係由MS-35與SO-C5的混合物,MS-35是由 DENKI KAGAKU K0GY0 Κ·Κ·所製造且 S0-C5 是由 Tatsumori 股份有限公司所製造,在顆粒尺寸分布方面,最大的顆粒 直徑:不小於200微米)C: \ 2D-0QDE \ 91-04 \ 91100717.ptd Page 23 1245593 V. Description of the invention (21) * The above-mentioned solvent components are not included in the one-hundred-eighth specific concentration described in Table 1. 77 Hardener * S Anhydride: An acid anhydride-based hardener (E picure Υ Η 3 0 7 manufactured by Japan Epoxy Resin Co., Ltd.) Hardening accelerator * πimisal π •• Based on imidazole Hardener (2E4MZ-CN, manufactured by SHIKOKU Chemical Co., Ltd.) Organic filler * Π Rubber filler π •• Rubber-based filler (XER-91, manufactured by JSR) Liquid rubber * π has been changed Epoxy ”: Modified epoxy butadiene rubber (E-1OO00_8. 〇, manufactured by NIPPON Petrochemical Co., Ltd.) Inorganic filler * π silica (diameter Φ: 24 microns ) Π: Silane-coated fumed silicon (Tasumori PLV-6, the largest particle diameter in terms of particle size distribution: 24 microns) * "Silicon oxide (mixture) π ·· Silane-coated silicon oxide (7 : 3 (weight ratio), which is a mixture of MS-35 and SO-C5. MS-35 is manufactured by DENKI KAGAKU K0GY0 Κ · Κ · and S0-C5 is manufactured by Tatsumori Co., Ltd. in particle size distribution. In terms of the largest particle diameter: not less than 200 microns )
C:\2D-GODE\91-04\91100717.ptd 第24頁 1245593 五、發明說明(22) 表1 (ς 卜)?=LS φ)&^碱C: \ 2D-GODE \ 91-04 \ 91100717.ptd Page 24 1245593 V. Description of the invention (22) Table 1 (ς)? = LS φ) & ^ base
ElsEls
Ifi I (0Ζ.)£^<ΝΦ)^Α3> 碱 (0 卜)?^Γνιφ)/ί!§>« ss (s蘅枳®酸逖 (ΙΌ)糾鲁Ifi I (0Z.) £ ^ < ΝΦ) ^ Α3 > Base (0 卜)? ^ Γνιφ) / ί! § > «ss (s 蘅 枳 ® 酸 逖 (ΙΌ)
(s^KTHsHilJ (S 碱Kiy^il] (ΙΌ) in# (Γ0)勃# (ld)勃# (ΙΌ)鄯# (ΙΌ)釗# (%i s}®(s ^ KTHsHilJ (S base Kiy ^ il) (ΙΌ) in # (Γ0) 勃 # (ld) 博 # (ΙΌ) 鄯 # (ΙΌ) 赵 # (% i s) ®
(ςι) I (H)felg § i (s) fe 趑 (s)H-g 氍 (Η)&趑 (e)UHda 趟嫠 (e) vdas^ (edNil囤并 £dds 雲 (ool)vda 雲 観滋丨邻卸* (rvll)Kuis 画 蘅铤1仞切* (n)Kus画 C:\2D-CODE\91>04\91100717.ptd 第 25 頁 1245593 五、發明說明(23) 如同上述的核心基板所使用的一種Βτ基板具有〇 · 8毫米 的厚度。使用一種模具,一種具有預定尺寸的穿孔可以接 著形成於上述的核心基板之中。接下來,將一種背條黏合 =上述核心基板之一表面上。然後,上述的核心基板是隨 者上述月條的月條側面以正面朝下的方式來設置。接下 來,將一種晶片電容裔從上述核心基板的其他側邊來插入 至上述的開口,並使用一種晶片安裝器來設置於上述的開 口中的上述背條的黏合側之一個預定位置。接著使用一分 配器來將表達於表1中的嵌入樹脂流入在上述開口中的晶 片電谷裔與上述開口之間的缺口之間。 上述的嵌入樹脂於80 t的溫度下進行3小時的第一次加 熱步驟,並接下來在1 70 °C的溫度下進行6小時的第二·欠加 熱步驟,以經過泡沫消除與熱硬化處理。因此,使用一册 狀磨光機來對上述經過處理的嵌入樹脂之表面進行粗Z 拋光,並使用重疊拋光來完成拋光的過程。然後,以二 化碳氣體雷射光束來照射上述的嵌入樹脂以形成通孔於 入樹脂中,以便於暴露出上述晶片電容器的電極。、入 以後,上述嵌入樹脂經過拋光的表面經過使用 與KMn〇4溶液來進行粗链化的步驟。上述故入樹=液 糙化的表面可以藉由—Pd催化劑來進行活化,藉由 行無電鍍膜/並接著藉由銅來進行電鍍。在上述嵌二 經過電鍍之後的表面上形成一層抗光蝕劑。隨 二曰 光敍劑,在上述嵌入樹脂經過電鍍之後的表面上^j抗 預定的佈線圖樣。使用NaAW/濃硫酸來蝕刻移除ς成需一要層 第26頁 C: \2D-C0DE\91-04\91100717.ptd 1245593 五、發明說明(24) — 的銅。將上述抗光蝕劑從上述嵌入樹脂剝除, 線的形成步驟。 心成一佈 將一種用來作為絕緣層的薄膜層合於上述鋼 3粗糙化的表面之上’接下來,對上述的銅電鍍u;; …硬化的處理。使用雷射光束來照射上述的絕 形成一通孔,使得中間層可以藉以連結。接下來用=, 文中相同的氧化劑來對上述絕緣層的表面進 /、 用如上所述的方式來形成一預定的佈線。然;=化播: ί作乾燥薄膜層合於佈線電路板的最上層之 於光線下,接著,發展上述乾燥薄膜 y路 形成步驟。 70风抗焊料層的 裝设一半導體元件於末端電極之上,其中, 電極先以Ni電鍍,再以Au電鑛。上述的 端 過-焊料回流爐以形成-種用來裝設一 G體u t經 的裝設部份:m器來使用未充滿材料來填充上述 得到一評估樣品填充材料接著經過熱硬化處理,以 。。ί:來C讓=t所得到的評估樣品經過熱循環測試(-55 cf 2 c· m次循環)與pcT(麼力 55 cooker)測試(i2KCx?女 $ 厭·“。 P essure 之評估樣品的表面狀能及· 小時)。觀察經過測試 ; = 以將不低·_果判定為良上好述 結果可以表達於表2之中。 〇民野。上述的 第27頁 C:\2D-OODE\91-O4\91100717.ptd 1245593 五、發明說明(25) 為了測量上述嵌入樹脂的熱膨脹係數,可以將上述的嵌 入樹脂製作成具有厚度為1 0 0微米的片材。上述片材在1 2 0 °C的溫度下進行第一加熱步驟歷經1小時並接著在1 7 0 °C的 溫度下進行第二加熱步驟歷經5小時以經過熱硬化的過程 ,接下來將上述的片材切成具有4毫米X 2 0毫米的尺寸之 樣本。在上文中所製備的樣品接著可以藉由使用一種熱膨 脹係數測量器來測量。在某些細節中,上述的樣品曾經一 度冷卻至-60 °C的溫度,並接著在以每分鐘2 °C的加熱速率 之下對上述的樣品進行測量。上文中所測量的熱膨脹係數 落於- 5 0 °C至+ 1 3 0 °C。上述的結果表示於表2之中。(ς) I (H) felg § i (s) fe 趑 (s) Hg 氍 (Η) & 趑 (e) UHda 嫠 (e) vdas ^ (edNil store and £ dds cloud (ool) vda cloud 観Neighbor unloading * (rvll) Kuis picture 1 cut * (n) Kus picture C: \ 2D-CODE \ 91 > 04 \ 91100717.ptd Page 25 1245593 V. Description of the invention (23) As the core of the above A Bτ substrate used in the substrate has a thickness of 0.8 mm. Using a mold, a perforation with a predetermined size can be subsequently formed in the above-mentioned core substrate. Next, a back strip is bonded = one of the above-mentioned core substrates On the surface. Then, the above-mentioned core substrate is provided with the side of the moon bar of the above-mentioned moon bar facing down. Next, a chip capacitor is inserted into the opening from the other side of the core substrate. A chip mounter is used to set a predetermined position on the adhesive side of the back strip in the above-mentioned opening. Then, a dispenser is used to flow the embedded resin expressed in Table 1 into the wafer valley in the above-mentioned opening. And the gap between the seed and the opening. The first heating step was performed for 3 hours at a temperature of 80 t, and then the second and under heating step was performed at a temperature of 1 70 ° C for 6 hours to undergo foam removal and heat hardening treatment. Therefore, use A booklet polisher was used to perform rough Z polishing on the surface of the treated embedded resin, and the polishing process was completed using overlapping polishing. Then, the above embedded resin was irradiated with a laser beam of carbon dioxide gas to form a through hole. Holes are inserted into the resin so that the electrodes of the chip capacitors are exposed. After the insertion, the polished surface of the embedded resin is subjected to a rough chaining step with KMnO4 solution. The above tree entry = liquid roughening The surface can be activated by a -Pd catalyst, by electroless plating and / or by electroplating with copper. A layer of photoresist is formed on the surface of the above-mentioned embedded layer after electroplating. On the surface of the above-mentioned embedded resin after plating, anti-predetermined wiring patterns. Use NaAW / conc. 0717.ptd 1245593 V. Description of the invention (24) — Copper. The photoresist is stripped from the embedded resin, and the wire is formed. A cloth is laminated to the steel as a layer of insulation. 3 on the roughened surface 'Next, the above-mentioned copper plating u ;; ... hardening treatment. Use a laser beam to irradiate the above-mentioned insulation to form a through hole so that the intermediate layer can be connected. Next, use =, in the text The same oxidant is used to enter the surface of the insulating layer, and a predetermined wiring is formed in the manner described above. However, = chemical broadcasting: a dry film is laminated on the uppermost layer of the wiring circuit board under light, and then, the above-mentioned dry film y-path forming step is developed. A 70-degree anti-solder layer is provided with a semiconductor element on the terminal electrode, wherein the electrode is first plated with Ni, and then Au power ore. The above-mentioned end-pass solder reflow furnace is used to form a kind of installation part for installing a G body ut warp: a device to fill the above with an unfilled material to obtain an evaluation sample filling material and then heat curing treatment to . . ί: Let C let the evaluation sample obtained by t go through thermal cycle test (-55 cf 2 c · m cycles) and pcT (Meili 55 cooker) test (i2KCx? Female $ tired · ". P essure evaluation sample Surface energy and · hours). Observed and tested; = The result is judged to be good. The results can be expressed in Table 2. Mino. The above page 27 C: \ 2D- OODE \ 91-O4 \ 91100717.ptd 1245593 V. Description of the invention (25) In order to measure the thermal expansion coefficient of the above-mentioned embedded resin, the above-mentioned embedded resin can be made into a sheet having a thickness of 100 microns. The above sheet is in 1 The first heating step was performed at a temperature of 20 ° C for 1 hour and then the second heating step was performed at a temperature of 170 ° C for 5 hours to undergo a thermal curing process. Then, the above sheet was cut into A sample with a size of 4 mm x 20 mm. The sample prepared above can then be measured by using a coefficient of thermal expansion. In some details, the above sample was once cooled to -60 ° C. Temperature and then at a heating rate of 2 ° C per minute The above samples were measured in the thermal expansion coefficient falls within the above measured -. 5 0 ° C to + 1 3 0 ° C the above-described results are shown in Table 2.
\\312\2d-code\91-04\91100717.ptd 第28頁 1245593 五、發明說明(26) 2表 _^_ (% «S爵 HSBS 鄉N^lslud 抝 (SS州侧) S9 001 001 55Ί 02 (®®,刦侧) 09 (親皆琍㈣) IOOZ. 001 OS I551 02 _^_ (% "觸®) 001 ~^Γ 001 02 is® s (鏡创胡«) 000 GO^E&wisI^\\ 312 \ 2d-code \ 91-04 \ 91100717.ptd Page 28 1245593 V. Description of the invention (26) 2 Table _ ^ _ (% «SJ HSBS Township N ^ lslud 拗 (SS State side) S9 001 001 55Ί 02 (®®, side) 09 (Kinjiri) IOOZ. 001 OS I551 02 _ ^ _ (% " Touch®) 001 ~ ^ Γ 001 02 is® s (Mirror Chuanghu «) 000 GO ^ E & wisI ^
lCN eeNNΤΓlCN eeNNΤΓ
otNotN
Hi 画___1 C:\2D-OODE\91-04\91100717.ptd 第 29 頁 1245593 五、發明說明(27) 樣品編號1至4與6,包含一種可溶有機填充劑或是可溶 解於一種氧化劑之中的可溶樹脂,在pCT測試之後不會2 為剝離而形成銅金屬層的起泡並從而呈現出一種良好θ的黏 合性。在樣品編號3中,更包含了一種半固體萘型環氧樹 脂,可以顯示出良好的結果。 〈 ^ 相反地,樣品編號5與7,不包含可溶有機填充劑或是可 溶解於一種氧化劑之中的可溶樹脂,在PCT測試(例如,參 考在圖5之中的編號29)之後會產生銅金屬層的起泡或是在 上述嵌入樹脂中破裂(例如,參考在圖4中的編號28)<。&在 上述結果中可以發現的是,可溶有機填充劑或是可溶解於 一種氧化劑之中的可溶樹脂的添加使得嵌入樹脂黏合至上 述銅金屬層的黏合性之改善變成可能。同樣可以發^的 是,可以發揮一種效果以放鬆上述的壓力濃度並^此可以 防止破裂的發生。 樣品編號6,包含一種固體環氧樹脂’可以顯示出歸因 於揮發性溶劑而發生的空隙,上述揮發性溶劑的添加是用 來處理上述嵌入樹脂的黏度之昇高。可以發現的是,上述 的環氧樹脂,如果使用的話,最好是—種^狀環氧樹脂二 根據本發明,可獲得一種與由銅或是類似材料所製成的 佈線具有良好的黏著性之嵌入樹脂及一包含該嵌入樹脂之 嵌入電子零件之佈線電路板。藉由促進該嵌入樹脂之表面 的粗糙化,會發揮一固定作用,以改良其與該佈線之黏著 性。再者,可獲得一於電連接中具有改良可靠度之佈線電 路板,其係於從嵌入於其中之電子零件至裝設在幾乎設於Hi drawing ___1 C: \ 2D-OODE \ 91-04 \ 91100717.ptd Page 29 1245593 V. Description of the invention (27) Samples Nos. 1 to 4 and 6 contain a soluble organic filler or can be dissolved in a kind The soluble resin among the oxidants does not form a blistered copper metal layer for peeling after the pCT test and thus exhibits a good θ adhesion. In Sample No. 3, a semi-solid naphthalene-type epoxy resin was further included, which showed good results. <^ Conversely, samples Nos. 5 and 7 that do not contain soluble organic fillers or soluble resins that are soluble in an oxidant will be tested after the PCT (for example, refer to No. 29 in Figure 5). Foaming of the copper metal layer is generated or cracked in the above-mentioned embedded resin (for example, refer to No. 28 in Fig. 4) <. & In the above results, it can be found that the addition of a soluble organic filler or a soluble resin soluble in an oxidizing agent makes it possible to improve the adhesion of the embedded resin to the copper metal layer. It can also be said that an effect can be exerted to relax the above-mentioned pressure concentration and prevent the occurrence of cracking. Sample No. 6, which contains a solid epoxy resin ', can show voids due to a volatile solvent, which is added to deal with the increase in viscosity of the embedded resin. It can be found that the above-mentioned epoxy resin, if used, is preferably a kind of ^ -shaped epoxy resin. According to the present invention, it is possible to obtain a kind of good adhesion with a wiring made of copper or a similar material. An embedded resin and a wiring circuit board of the embedded electronic part including the embedded resin. By promoting the roughening of the surface of the embedded resin, a fixing effect is exerted to improve its adhesion to the wiring. Furthermore, a wiring circuit board with improved reliability in electrical connection can be obtained, ranging from the electronic parts embedded therein to being installed in almost
C:\2D-CODE\91-04\911007l7.ptdC: \ 2D-CODE \ 91-04 \ 911007l7.ptd
第30頁 1245593 五、發明說明(29) 29 透明發泡 30 以氧化劑溶解之可溶成分 31 實質上不溶於氧化劑之不可溶成分 3 2 洗提部分 50 電子零件之電極之突出物 60 平滑表面 61 粗链表面 90 預定佈線 100 絕緣基板 110 穿孔 120 護條 130 層合晶片電容器 14 0 電極 150 層合材料 190 薄膜 20 0 銅箔 201 預定佈線/末端電極 210 抗焊料層 230 預定佈線 240 抗焊料層 25 0 引線 260 焊料凸塊 270 半導體元件 3 0 0 暴露部分P.30 1245593 V. Description of the invention (29) 29 Transparent foam 30 Soluble component dissolved with oxidant 31 Insoluble component substantially insoluble in oxidant 3 2 Elution part 50 Projection of electrode of electronic part 60 Smooth surface 61 Thick chain surface 90 Scheduled wiring 100 Insulating substrate 110 Perforation 120 Guard strip 130 Laminated wafer capacitor 14 0 Electrode 150 Laminated material 190 Thin film 20 0 Copper foil 201 Scheduled wiring / terminal electrode 210 Anti-solder layer 230 Scheduled wiring 240 Anti-solder layer 25 0 Lead 260 Solder bump 270 Semiconductor element 3 0 0 Exposed part
C:\2D-CODE\91-04\91100717.ptd 第32頁 1245593 五、發明說明(30) 4 0 0 絕緣層 5 0 0 通孔 60 0 穿孔 7 0 0 銅面板電鍵 80 0 接觸導體 90 0 穿孔導體 1 0 0 0 穿孔之糊狀物C: \ 2D-CODE \ 91-04 \ 91100717.ptd Page 32 1245593 V. Description of the invention (30) 4 0 0 Insulating layer 5 0 0 Through hole 60 0 Perforation 7 0 0 Copper panel key 80 0 Contact conductor 90 0 Perforated conductor 1 0 0 0 Perforated paste
IlHilil 第33頁 C:\2D-C0DE\91-04\91100717.ptd 1245593 圖式簡單說明 圖1為說明本發明之嵌入樹脂的一具體例之圖,其係參 考其平滑表面的鄰近部份; 圖2為說明本發明之嵌入樹脂的另一具體例之圖,其係 參考其粗糙表面的鄰近部份; 圖3為說明將本發明之佈線電路板應用至一BGA基板之一 實施例之圖; 圖4為說明產生於該嵌入樹脂之裂縫(crack)之狀態之實 施例的圖; 圖5為說明產生於具有該嵌入樹脂之界面之佈線透明發 泡(b 1 i s t e r)之實施例之圖; 圖6為說明本發明之製造佈線電路板之方法之具體例之 圖; 圖7為說明本發明之製造佈線電路板之方法之另一具體 例之圖; 圖8為說明本發明之製造佈線電路板之方法之其他具體 例之圖; 圖9為說明本發明之製造佈線電路板之方法之再一具體 例之圖; 圖1 0為說明本發明之製造佈線電路板之方法之又一具體 例之圖; 圖1 1為說明本發明之製造佈線電路板之方法之又一具體 例之圖; 圖1 2為說明本發明之製造佈線電路板之方法之又一具體 例之圖;IlHilil Page 33 C: \ 2D-C0DE \ 91-04 \ 91100717.ptd 1245593 Brief description of the drawing Figure 1 is a diagram illustrating a specific example of the embedded resin of the present invention, which refers to the adjacent portion of its smooth surface; FIG. 2 is a diagram illustrating another specific example of the embedded resin of the present invention, which refers to the adjacent portion of the rough surface thereof. FIG. 3 is a diagram illustrating an embodiment of applying the wiring circuit board of the present invention to a BGA substrate Figure 4 is a diagram illustrating an example of a state of a crack generated in the embedded resin; Figure 5 is a diagram illustrating an example of a transparent foam (b 1 ister) of a wiring generated in an interface having the embedded resin Figure 6 is a diagram illustrating a specific example of a method for manufacturing a wiring circuit board of the present invention; Figure 7 is a diagram illustrating another specific example of a method for manufacturing a wiring circuit board of the present invention; Figure 8 is a diagram illustrating manufacturing a wiring of the present invention FIG. 9 is a diagram illustrating another specific example of a method for manufacturing a wiring circuit board of the present invention; FIG. 9 is a diagram illustrating another specific example of a method for manufacturing a wiring circuit board of the present invention; Example map 11 is an explanatory view of still another specific embodiment of the method of the present invention for producing a wiring circuit board; FIG. 12 is a diagram of a further method of the present invention for producing a wiring circuit board of the embodiment specifically described;
C:\2D-CODE\91-04\91100717.ptd 第34頁 1245593 圖式簡單說明 -- 圖1 3為說明本發明之製造佈線電路板之方法之又一具體 例之圖; 圖14為說明將本發明之佈線電路板應用至一BGA基板之 實施例之圖; 圖15為說明一包含一 FC-PGA型多層印刷電路板之半導體 裝置做為本發明所涉及之具體例之圖; 圖1 6為說明具有4 0 0微米厚度之鍍銅核心基板之略圖; 圖17為說明具有40 0微米厚度之圖樣(patterned)鍍銅核 心基板之狀態之圖; 018 為說明一通孔(via hole)及一穿孔(throughhole) 如何形成於一具有形成於其兩側之絕緣層之核心基板之 圖; 圖1 9為說明具有形成於其兩側之絕緣層之核心基板之狀 悲之圖’該核心基板已進行面板電鑛(p a n e 1 一 p 1 a t e d ); 圖20為說明具有其已填充穿孔之基板之圖; 圖21為說明具有打孔(punched)於其中之穿孔之基板之 圖, 圖2 2為說明一護條(m a s k i n g t a p e )如何黏合於具有打孔 於其中之穿孔之基板之一側之圖; 圖23為說明層合晶片電容器(laminated chip c a p a c i t o r )如何設置於暴露在穿孔之護條上之圖; 圖24為說明以嵌入樹脂填充之穿孔之圖; 圖2 5為說明已拋光為使其表面平滑之基板之圖; 圖2 6為說明基板如何製成一面板於其已拋光表面之圖;C: \ 2D-CODE \ 91-04 \ 91100717.ptd Page 34 1245593 Brief description of the diagram-Figure 13 is a diagram illustrating another specific example of the method for manufacturing a wiring circuit board of the present invention; FIG. 14 is an illustration FIG. 15 is a diagram illustrating an embodiment in which a wiring circuit board of the present invention is applied to a BGA substrate; FIG. 15 is a diagram illustrating a semiconductor device including an FC-PGA type multilayer printed circuit board as a specific example involved in the present invention; FIG. 1 6 is a schematic diagram illustrating a copper-plated core substrate having a thickness of 400 micrometers; FIG. 17 is a diagram illustrating a state of a patterned copper-plated core substrate having a thickness of 400 micrometers; 018 illustrates a via hole and A through hole is formed on a core substrate having an insulating layer formed on both sides thereof; FIG. 19 is a diagram illustrating the shape of a core substrate having an insulating layer formed on both sides of the core substrate Panel ore has been performed (pane 1-p 1 ated); Figure 20 is a diagram illustrating a substrate having a perforation filled therein; Figure 21 is a diagram illustrating a substrate having a perforation punched therein, Figure 2 2 To illustrate a masking tape) how to adhere to one side of a substrate with perforations in which it is punched; FIG. 23 is a diagram illustrating how a laminated chip capacitor is placed on a protective strip exposed to perforations; FIG. 24 is an illustration Figures of perforations filled with embedded resin; Figure 25 is a diagram illustrating a substrate that has been polished to smooth its surface; Figure 26 is a diagram illustrating how the substrate is made into a panel on its polished surface;
\\312\2d-code\91-04\91100717.ptd 第35頁 1245593 圖式簡單說明 圖27為說明如何製成一佈線圖樣(wiring patterning) 之圖; 圖28為說明一集結層(build-up layer)及一抗焊料層 (solder resist layer)如何形成於基板上之圖;以及 圖29為說明一FC-PGA型多層印刷電路板做為本發明所涉 及之具體例之圖。\\ 312 \ 2d-code \ 91-04 \ 91100717.ptd Page 35 1245593 Brief Description of Drawings Figure 27 is a diagram illustrating how to make a wiring patterning; Figure 28 is a diagram illustrating a build-up layer (build- up layer and a solder resist layer are formed on the substrate; and FIG. 29 is a diagram illustrating a FC-PGA type multilayer printed circuit board as a specific example of the present invention.
C:\2D-C0DE\91-04\91100717.ptd 第36頁C: \ 2D-C0DE \ 91-04 \ 91100717.ptd Page 36
Claims (1)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2000212075 | 2000-07-13 | ||
JP2001044795A JP4326710B2 (en) | 2000-07-13 | 2001-02-21 | Wiring board using embedded resin |
Publications (1)
Publication Number | Publication Date |
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TWI245593B true TWI245593B (en) | 2005-12-11 |
Family
ID=26595922
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TW91100717A TWI245593B (en) | 2000-07-13 | 2002-01-11 | Embedding resin, wiring substrate using same and process for producing wiring substrate using same |
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TW (1) | TWI245593B (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4365641B2 (en) * | 2002-07-10 | 2009-11-18 | 日本特殊陶業株式会社 | Multilayer wiring board and method for manufacturing multilayer wiring board |
JP4500091B2 (en) * | 2004-04-23 | 2010-07-14 | 三井化学株式会社 | Circuit board |
TW200707468A (en) * | 2005-04-06 | 2007-02-16 | Toagosei Co Ltd | Conductive paste, circuit board, circuit article and method for manufacturing such circuit article |
JP4900910B2 (en) * | 2006-03-17 | 2012-03-21 | 日本特殊陶業株式会社 | Filler and substrate using the same |
WO2015064642A1 (en) * | 2013-10-30 | 2015-05-07 | 京セラ株式会社 | Wiring board and mounting structure using same |
JP6398096B2 (en) * | 2014-03-05 | 2018-10-03 | 三菱瓦斯化学株式会社 | Resin structure, and prepreg, resin sheet, metal foil-clad laminate, and printed wiring board using the same |
-
2001
- 2001-02-21 JP JP2001044795A patent/JP4326710B2/en not_active Expired - Lifetime
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2002
- 2002-01-11 TW TW91100717A patent/TWI245593B/en not_active IP Right Cessation
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JP2002094211A (en) | 2002-03-29 |
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