JP2002348441A - Embedding resin and wiring board using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an embedding resin capable of increasing packaging density of a wiring board for mounting electronic components and obtaining high reliability in the reliability test for heat resistance, water resistance and the like, and to provide a wiring board using the same. SOLUTION: The wiring board is obtained by embedding the electronic components disposed in an opening (a recess such as a through-hole or a cavity) provided on an insulating board using an embedding resin having a peel strength of a cupper layer after a pressure cooker test (121 deg.C × humidity 100 mass% ×2.1 atoms × 168 hours) of 588 N/m (0.6 kg/cm) or above, and by forming a buildup layer thereon.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an embedding resin for embedding electronic components such as a chip capacitor, a chip inductor, and a chip resistor in a substrate, and a wiring board in which electronic components are embedded in the substrate. In particular, it is suitable for a multilayer wiring board in which a fine wiring layer having a width of 150 μm or less is formed on an embedded resin, a package for housing a semiconductor element, and the like.

[0002]

2. Description of the Related Art Recently, a multi-chip module (MCM) in which a large number of semiconductor elements are mounted on a build-up wiring board.
Is being considered. When electronic components such as a chip capacitor, a chip inductor, and a chip resistor are mounted, they are generally surface-mounted using solder on a mounting wiring layer formed on the surface of a wiring board.

However, when electronic components are surface-mounted on the surface of the build-up wiring board, a predetermined mounting area corresponding to each electronic component is required, so that there is naturally a limit to miniaturization. In addition, there is a problem in that the routing of the wiring at the time of surface mounting increases the parasitic inductance, which is unfavorable in characteristics, and makes it difficult to cope with a higher frequency of the electronic device.

In order to solve these problems, various methods for embedding electronic components in a substrate have been studied. Japanese Patent Application Laid-Open No. H11-126978 discloses a method of transferring an electronic component by soldering it to a wiring board with a transfer sheet made of a metal foil in advance and then transferring the electronic component. Japanese Patent Application Laid-Open No. 2000-124352 discloses a multilayer wiring board in which an insulating layer is built up on an electronic component embedded in a core substrate.

[0005]

In order to embed an electronic component arranged in a wiring board into a substrate, a gap between the core substrate and the electronic component is filled with a resin, and an electrode of the electronic component and a wiring formed on an insulating layer are formed. Must be electrically connected by electroless plating or the like. In this case, with the usual filling resin, it is not possible to sufficiently secure the adhesion to the plating layer to be a wiring, and there is a problem that plating blisters and the like occur in a reliability test.
For example, even in the initial state, even if it has a peel strength exceeding 588 N / m, it is deteriorated by the influence of heat or moisture in the use environment, and the peel strength becomes 588 N / m or less, which is a problem. In particular, 150 μm width on embedded resin
This becomes a significant problem when the following fine wiring layer is formed, or when a wiring layer that flows a large current such as a power supply layer is formed.

In order to improve the adhesion between the embedded resin and the plating layer, first, the embedded resin is embedded, and then the surface of the embedded resin is roughened with an oxidizing agent such as permanganic acid or chromic acid, and then plated. In this case, a method of forming a wiring layer and performing build-up (multi-layering) can be considered. This is because the adhesion to the plating wiring layer is increased by the anchor effect of the irregularities on the roughened surface. This is known as a method for improving the adhesion between a wiring layer and an insulating layer of a build-up wiring board. However, the embedding resin usually does not consider the easiness of roughening at all, and it is difficult to expect a dramatic improvement in adhesion by the above method.

SUMMARY OF THE INVENTION The present invention provides an embedded resin capable of increasing the mounting density of a wiring board on which electronic components are mounted and obtaining high reliability in reliability tests such as heat resistance and water resistance, and a wiring board using the same. The task is to

[0008]

An embedding resin according to the present invention is an embedding resin for embedding an electronic component disposed in an opening (a recess such as a through hole or a cavity) provided in a substrate. The peel strength of the copper layer of the substrate having the copper layer formed on the cured product after the pressure cooker test (121 ° C. × 100% by humidity × 2.1 atm × 168 hours) was 588 N / m (0.6 kg / c
m) or more. This peel strength
70 at peel strength after pressure cooker test (121 ° C x 100% by humidity x 2.1 atm x 168 hours)
More preferably, it is 0 N / m (0.71 kg / cm) or more. Under these conditions, the peel strength is still 58%.
By securing 8 N / m (0.6 kg / cm) or more, even when a fine wiring layer having a width of 150 μm or less is formed on the embedded resin, or when a wiring layer that flows a large current such as a power supply layer is formed. , High adhesion reliability can be ensured. In particular, even when a wiring layer for a power supply layer connected to an electronic component such as a capacitor having a power supply function is formed, high adhesion reliability can be ensured.
The electronic components include passive electronic components such as a chip capacitor, a chip inductor, a chip resistor, and a filter, a transistor, a semiconductor element, a FET, a low noise amplifier (L
NA) and other active electronic components, or SAW filters, L
Electronic components such as a C filter, an antenna switch module, a coupler, and a diplexer are included.

Further, the embedding resin of the present invention is a pressure cooker test (121 ° C. × 100% by mass of humidity × 2.10%) of a substrate having a copper layer formed on a cured product of the embedding resin.
The peel strength of the copper layer after 1 atm x 336 hours)
It is good to be more than 600N / m (0.61kg / cm). Even after passing through such more severe conditions, by securing the peel strength of 600 N / m (0.61 kg / cm) or more, the wiring layer for the power supply layer connected to the electronic component such as the capacitor having the power supply function can be formed. Even if formed,
Even higher adhesion reliability can be ensured.

The method for measuring the peel strength is JIS C50.
12, but the width of the copper layer is 10 mm. The peel strength at the time of peeling the copper layer at 90 degrees (vertical direction) from the embedded resin surface at a tensile speed of 50 mm / min is measured. The embedding resin of the present invention was subjected to a pressure cooker test (121 ° C. × 100% by humidity × 2.1 atm × 16).
8 hours), the peel strength of the copper layer was 588 N / m.
(0.6 kg / cm) or more, carbon black may be added in an amount of 0.5% by mass or less, preferably 0.3% by mass or less, in order to maintain a color of black. This is because the wiring layer can be colored black without deteriorating the adhesion reliability of the wiring layer under high temperature and high humidity and the volume resistance which is an index of insulating property.

The embedding resin of the present invention is subjected to a pressure cooker test (121 ° C. × 100% by mass of humidity × 2.
(1 atm x 336 hours)
0.4% by mass of carbon black in order to color black while maintaining the value at 00 N / m (0.61 kg / cm) or more.
Below, preferably 0.3% by mass or less, particularly preferably 0.2% by mass. This is because, by increasing the adhesion of the wiring layer under high temperature and high humidity, the cause of defects such as blisters in the wiring board manufacturing process can be prevented beforehand, and the yield and the insulation reliability can be improved.

The resin to be embedded is preferably colored black so as to suppress irregular reflection during exposure when the wiring pattern is cut or to prevent the occurrence of color unevenness during curing. However, when carbon black is blended in a certain amount or more for coloring black, the heat resistance and moisture resistance of the resin are reduced, and the adhesion to copper is reduced.

The embedding resin of the present invention comprises a resin component and at least one kind of inorganic filler. In addition to adjusting the coefficient of thermal expansion, the inorganic filler requires the three-dimensional structure of the epoxy resin after curing and the shape of the embedded resin after roughening due to the effect of the inorganic filler as an aggregate. This is because there is no further collapse.

The inorganic filler used is not particularly limited,
Crystalline silica, fused silica, alumina, silicon nitride and the like are preferred. Since the thermal expansion coefficient of the embedded resin can be effectively reduced, the resin can be prevented from peeling off due to thermal stress, and the reliability can be improved.

Regarding the filler diameter of the inorganic filler, it is preferable to use a filler having a particle diameter of 50 μm or less because the embedded resin must easily flow into the gap between the electrodes of the electronic component. If it exceeds 50 μm, the gap between the electrodes of the electronic component is liable to be clogged with the filler, and a portion having an extremely different coefficient of thermal expansion locally occurs due to insufficient filling of the embedded resin. The lower limit of the filler diameter is preferably 0.1 μm or more. If it is smaller than this, it becomes difficult to secure the fluidity of the embedded resin. It is preferably at least 0.3 μm, more preferably at least 0.5 μm. To achieve low viscosity and high filling of the embedded resin, the particle size distribution should be widened.

The shape of the inorganic filler is preferably substantially spherical in order to increase the fluidity and the filling rate of the filling resin. In particular, a silica-based inorganic filler is preferable because a spherical one can be easily obtained.

The surface of the inorganic filler may be subjected to a surface treatment with a coupling agent, if necessary. This is because the wettability of the inorganic filler with the resin component is improved, and the fluidity of the embedded resin can be improved. As the type of the coupling agent, a silane type, a titanate type, an aluminate type or the like is used.

The embedding resin of the present invention contains at least one component of a liquid epoxy resin, bisphenol epoxy resin or naphthalene type epoxy resin, phenol novolak type epoxy resin or cresol novolak type epoxy resin, in consideration of its fluidity. It is good to use as a resin component. If the fluidity of the embedded resin is poor, poor filling is likely to occur in the gap between the electrodes of the electronic component, and a portion having an extremely different coefficient of thermal expansion locally occurs. in particular,
In consideration of heat resistance and moisture resistance, naphthalene type epoxy resin is superior.

A wiring board in which an electronic component is embedded using the embedded resin of the present invention has an advantage that the peel strength of a wiring layer formed on the embedded resin is unlikely to be deteriorated by the influence of heat or moisture in a use environment. In particular, a width of 150
It is suitable when a fine wiring layer of μm or less is formed, or when a wiring layer that flows a large current such as a power supply layer is formed. In particular, by improving the adhesion of the wiring layer, which is the power supply layer, to the embedded resin, it is possible to effectively prevent the wiring layer from bulging and degrading the peel strength even when a large current flows from the power supply capacitor. Can be prevented. The term “embed an electronic component” as used herein refers to an opening (such as a through hole (for example, FIG. 1) or a concave portion (for example, FIG. 10) such as a cavity) provided in a substrate such as a core substrate or a built-up insulating layer. After the electronic component is placed in the opening, filling the gap created between the electronic component and the opening with an embedding resin. In particular, when a thin core substrate having a thickness of 400 μm or less is used, it is preferable to dispose the electronic component in a cavity provided in the build-up layer. As the opening, a through hole formed by punching a substrate, a cavity formed by a multilayer technique, or the like may be used. Substrates used in the present invention include FR-4, FR-5, BT
It is preferable to use a so-called core substrate such as PTFE. Alternatively, a core substrate in which a thick copper foil having a thickness of about 35 μm is sandwiched between thermoplastic resin sheets such as PTFE and an opening may be formed. In addition, a structure may be used in which a build-up layer in which insulating layers and wiring layers are alternately laminated is formed on at least one surface of the core substrate, and an opening is formed to penetrate the core substrate and the build-up layer. In this case, even with a multilayer wiring board with a built-in capacitor as shown in FIG. 11, the thickness of the so-called glass-epoxy composite material (insulating board) is reduced to about 400 μm, which is half of 800 μm of a normal product. There is an advantage that the height can be reduced. As another example, a wiring board (for example, FIG. 1) in which an electronic component is embedded inside a core substrate or a wiring board (for example, FIG.
0) can be formed.

The thickness of the substrate on which the electronic component is embedded is preferably as close as possible to the thickness of the electronic component to be embedded. In particular, the distance from the surface of the terminal electrode of the electronic component to the wiring layer of the build-up layer laminated on the substrate is 100 μm or less (preferably 5 μm).
The relationship between the height of the electronic component and the thickness of the substrate is preferably set so as to be 0 μm or less, more preferably 30 μm or less. By making the distance between the electronic component and the build-up layer laminated on the substrate as close as possible, generation of unnecessary parasitic capacitance (inductance or the like) can be prevented.

On at least one surface of the core substrate, a build-up layer in which insulating layers and wiring layers are alternately laminated is formed, and a substrate having an opening formed to penetrate at least one of the core substrate and the build-up layer is used. The multilayer wiring board that has been manufactured may be manufactured, for example, as follows (FIGS. 11 to 11).
(FIG. 25).

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Here, an embodiment of a so-called "FC-PGA" structure shown in FIG. 11 will be described below. As shown in FIG. 12, an FR-5 double-sided copper-clad core substrate in which an 18 μm-thick copper foil (200) is attached to a 0.4-mm-thick insulating substrate (100) is prepared. The characteristics of the core substrate used here are as follows: Tg (glass transition point) by TMA is 175 ° C., CTE (thermal expansion coefficient) in the substrate surface direction is 16 ppm / ° C., CTE (thermal expansion coefficient) in the direction perpendicular to the substrate surface is 50 ppm / The dielectric constant ε at 1 ° C. and 1 MHz is 4.7, and the tan δ at 1 MHz is 0.018.

A photoresist film is attached to the core substrate and exposed and developed to provide an opening having a diameter of 600 μm and an opening (not shown) corresponding to a predetermined wiring shape. The copper foil exposed at the opening of the photoresist film is removed by etching using an etching solution containing sodium sulfite and sulfuric acid. The photoresist film is peeled off to obtain a core substrate having an exposed portion (300) as shown in FIG. 13 and an exposed portion (not shown) corresponding to a predetermined wiring shape.

A commercially available etching apparatus (manufactured by MEC)
After the surface of the copper foil is roughened by performing an etching process using a CZ processing device), a thickness of 35 mainly composed of epoxy resin is obtained.
A μm insulating film is attached to both sides of the core substrate. Then, curing is performed under the condition of 170 ° C. × 1.5 hours to form an insulating layer (400). The properties of the insulating layer after this curing are as follows: Tg (glass transition point) by TMA is 155 ° C .;
Tg (glass transition point) by MA is 204 ° C, CTE
(Thermal expansion coefficient) is 66 ppm / ° C., dielectric constant ε at 1 MHz is 3.7, and tan δ at 1 MHz is 0.03.
3. Weight loss at -300 ° C is -0.1%, water absorption is 0.8
%, The moisture absorption rate is 1%, the Young's modulus is 3 GHz, the tensile strength is 63 MPa, and the elongation rate is 4.6%.

As shown in FIG. 14, via holes (50) for interlayer connection are formed in the insulating layer (400) using a carbon dioxide laser.
0) is formed. The form of the via hole is in the shape of a horn having a surface layer portion diameter of 120 μm and a bottom portion diameter of 60 μm. Further, the output of the carbon dioxide laser was increased, and the insulating layer (40
0) and a through hole (600) having a diameter of 300 μm is formed so as to penetrate the core substrate. The inner wall surface of the through hole has undulations (not shown) peculiar to laser processing. Then, after immersing the substrate in a catalyst activating solution containing palladium chloride, electroless copper plating is performed on the entire surface (not shown).

Next, an 18 μm thick copper panel plating (700) is applied to the entire surface of the substrate. Here, a via hole conductor (800) for electrically connecting the layers is formed in the via hole (500). In addition, through holes (60
In 0), a through-hole conductor (900) for electrically connecting the front and back surfaces of the substrate is formed. An etching treatment is performed by a commercially available etching treatment device (CZ treatment device manufactured by MEC) to roughen the surface of the copper plating. Thereafter, a rust preventive treatment (trade name: CZ treatment) is performed with a rust preventive agent of the company to form a hydrophobic surface, and the hydrophobic treatment is completed. The contact angle 2θ of water on the surface of the conductor layer subjected to the hydrophobization treatment was measured with a contact angle measuring device (trade name: CA-A, manufactured by Kyowa Kagaku) by a liquid method, and the contact angle 2θ was 101 °. .

The nonwoven paper is placed on a pedestal equipped with a vacuum suction device, and the substrate is placed on the pedestal. A stainless steel filling mask having a through-hole is set thereon so as to correspond to the position of the through-hole (600). Next, a paste for filling through holes containing a copper filler is placed, and filling and filling are performed while pressing a roller squeegee.

As shown in FIG. 15, through holes (60
0), the paste for filling through holes (100
0) is temporarily cured at 120 ° C. for 20 minutes.
Next, as shown in FIG. 16, the surface of the substrate was polished (coarse polished) using a belt sander, and then flattened by buff polishing (final polishing), and cured at 150 ° C. × 5 hours. Complete the filling process. A part of the substrate which has completed the filling process is used for an evaluation test for filling properties.

As shown in FIG. 17, a through hole (opening: 110) of 8 mm square is formed using a mold (not shown). As shown in FIG. 18, a masking tape (120) is attached to one surface of the substrate. Then, as shown in FIG. 19, eight laminated chip capacitors (130) are arranged on the masking tape exposed in the through holes (110) by using a chip mounter. This multilayer chip capacitor has 1.2
It consists of a laminate (150) of mm × 0.6 mm × 0.4 mm, and the electrode (140) protrudes 70 μm from the laminate.

As shown in FIG. 20, a filling resin (160) of the present invention is filled into a through hole (110) in which a multilayer chip capacitor (130) is arranged, using a dispenser (not shown). The embedded resin is defoamed and thermally cured under the conditions of a primary heating step of 80 ° C. × 3 hours and a secondary heating step of 170 ° C. × 6 hours.

As shown in FIG. 21, the surface of the hardened embedded resin (160) is roughly polished by using a belt sander, and then finish polished by lap polishing. On the polished surface,
The end surface of the electrode (140) of the chip capacitor (130) is exposed. Then, the temporarily cured embedded resin (1
60) is cured at 150 ° C. for 5 hours.

Thereafter, the polished surface of the embedding resin (160) is roughened using a swelling solution and a KMnO ₄ solution. After activating the roughened surface with a Pd catalyst, copper plating is performed in the order of electroless plating and electrolytic plating. As shown in FIG. 22, a plating layer (170) formed on the embedding resin (160)
Is electrically connected to the end face of the electrode (140) of the chip capacitor (130). A resist (not shown) is formed on the plating surface, and a predetermined wiring pattern is patterned. Unnecessary copper is removed by etching using Na ₂ S ₂ O ₈ / concentrated sulfuric acid. The resist is peeled off to complete the formation of the wiring as shown in FIG. An etching treatment is performed by a commercially available etching treatment device (CZ treatment device manufactured by MEC Corporation) to roughen the surface of the copper plating of the wiring.

A film (190) to be an insulating layer thereon
Is laminated and thermally cured, and then irradiated with a carbon dioxide laser to form via holes for interlayer connection. The surface of the insulating layer is roughened using the same oxidizing agent as described above, and a predetermined wiring (201) is formed in the same manner. A dry film to be a solder resist layer is laminated on the outermost surface of the wiring board, and a mounting pattern of the semiconductor element is formed by exposing and developing, thereby completing the formation of the solder resist layer (210).
The same method is applied to the back side on which the mounting pins are attached, and the predetermined wiring (230) and the solder resist layer (2) are formed.
40) to form a multilayer printed wiring board before pinning as shown in FIG.

Terminal electrode (201) for mounting a semiconductor element
Is plated in the order of Ni plating and Au plating (not shown). After printing a solder paste made of low melting point solder thereon, a solder bump (220) for mounting a semiconductor element is formed through a solder reflow furnace.

On the other hand, a solder bump (260) for pinning through a solder reflow furnace is formed after printing a solder paste made of high melting point solder on the side opposite to the semiconductor element mounting surface. A pin (25) is attached to a jig (not shown).
In the state where the substrate is placed on top of (0), pinning is performed through a solder reflow furnace (not shown), and FIG.
As shown in the figure, FC-PGA before mounting the semiconductor element
Mold multilayer printed wiring board is obtained. Using a projector, the positional deviation of the tip of the pin (250) from the predetermined position, which was attached to the area corresponding to the opening (110) embedded with the embedded resin (160), was measured to be 0.1 mm or less. Good results were obtained.

The semiconductor element (27) is mounted on the semiconductor element mounting surface.
0) is placed at a position where it can be mounted, and the low melting point solder (22)
The semiconductor element (270) is mounted through a solder reflow furnace under a temperature condition in which only 0) melts. After filling the mounting portion with an underfill material (300) with a dispenser, it is thermally cured to obtain a semiconductor device using an FC-PGA type multilayer printed wiring board having a semiconductor element mounted on the surface as shown in FIG. .

A different wiring board of the present invention will be described in detail with reference to FIG. This can be manufactured by the following steps. As shown in FIG. 2, through holes (openings: 2) of a predetermined size are provided in the core substrate (1) using a mold,
After attaching the back tape (3) to one surface of the core substrate, the core substrate is placed with the surface to which the back tape is attached facing downward.

As shown in FIG. 3, a chip capacitor (4) is arranged at a predetermined position on the adhesive surface of the pack tape (3) in the opening (2) from the other surface using a chip mounter. As the chip capacitor used here, it is preferable to use a chip capacitor having an electrode (5) protruding from the capacitor body so that the embedded resin can easily move around.
As shown in FIG. 4, the embedded resin (6) of the present invention is poured into the gap in the opening with the chip capacitor (4) arranged in the opening (2) using a dispenser.

The embedded resin (6) is defoamed and thermally cured under the conditions of 100 ° C. × 80 minutes → 120 ° C. × 60 minutes → 160 ° C. × 10 minutes. The surface of the cured embedded resin (6) is roughly polished by using a belt sander, and then is polished by lap polishing. FIG. 5 shows the surface (60) of the embedded resin (6) after polishing. Next, as shown in FIG. 6, a via hole (7) is formed using a carbon dioxide laser.
Is drilled to expose the electrode (5) of the chip capacitor (4).

Thereafter, the exposed surface (61) of the embedding resin (6) is roughened using a swelling solution and a KMnO ₄ solution.
After activating the roughened surface with a Pd catalyst, copper plating (9) is performed in the order of electroless plating and electrolytic plating. FIG. 7 shows the state after copper plating. A resist (not shown) is formed on the plating surface, and a predetermined wiring pattern is patterned. Unnecessary copper is removed by etching using Na ₂ S ₂ O ₈ / concentrated sulfuric acid. The resist is stripped to complete the formation of the wiring (90) to be the power supply layer. FIG. 8 shows the state after forming the wiring to be the power supply layer.
Shown in By improving the adhesion of the wiring layer (90) serving as the power supply layer to the embedded resin (6), even if a large current flows from the power supply capacitor (4), the wiring layer (9
0) can be effectively prevented from bulging and the peel strength from deteriorating.

A film (14, 1) serving as an insulating layer is formed thereon.
After laminating 5) and thermally curing, laser irradiation is performed to form via holes for interlayer connection. The surface of the insulating layer is roughened using the same oxidizing agent, and a predetermined wiring pattern is formed by the same method. A dry film to be a solder resist layer is laminated on the outermost surface of the wiring board, and the mounting pattern of the semiconductor element is formed by exposing and developing to form a solder resist layer (12). FIG. 9 shows this state. The terminal electrode (13) for mounting the semiconductor element has Ni
Plating is performed in the order of plating and Au plating. Thereafter, the semiconductor element (18) is mounted through a solder reflow furnace. Solder balls (17) are formed on the electrodes to be mounted on the substrate by using low melting point solder. After the mounting portion is filled with an underfill material (21) with a dispenser, it is thermally cured to complete the production of the target wiring substrate as shown in FIG.

[0042]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The effects of the wiring board of the present invention will be described below with reference to an embodiment using a board. Table 1 for embedded resin
Each component is weighed and mixed so as to have the composition shown in Table 2, and kneaded with a three-roll mill. Here, the details of the items described in Table 1 are as follows.

[0043]

[Table 1]

Epoxy resin "HP-4032D": high-purity naphthalene type epoxy resin (manufactured by Dainippon Ink) "E-807": bisphenol F type epoxy resin (manufactured by Yuka Shell) "YL-980": bisphenol A type epoxy resin (made by Yuka Shell) "N-740": phenol novolak type epoxy resin (made by Dainippon Ink)

Curing agent "QH-200": acid anhydride curing agent (manufactured by Zeon Corporation) "B-570": acid anhydride curing agent (manufactured by DIC) "B-650": acid anhydride -Based curing agent (manufactured by DIC)-"YH-306": acid anhydride-based curing agent (manufactured by oil-based shell epoxy)-"YH-300": acid anhydride-based curing agent (manufactured by oil-based shell epoxy)

Accelerator (curing accelerator) "2P4MHZ": imidazole-based curing agent (manufactured by Shikoku Chemicals)

Inorganic filler "FB-5SDX": spherical silica filler (manufactured by Denki Kagaku Kogyo) Silane-coupling treated

Carbon black "# 4400": manufactured by Tokai Carbon Co., Ltd.

The “filler content” and “carbon content” are defined as the total of epoxy resin, curing agent and filler being 10
It is a value showing each content rate when it is set to 0% by mass. "Accelerator" means epoxy + curing agent + filler
When it is 0% by mass, it is 0.1% by mass. The ratio between the epoxy resin and the curing agent is 100/95 in terms of the functional group ratio. The following reliability evaluation is performed on these compositions.

(Evaluation of Reliability) The core substrate has a thickness of 0.8 m.
m BT substrate is used. The core substrate is formed by punching a through hole having a predetermined size using a mold. As shown in FIG. 2, after the back tape (3) is attached to one surface of the core substrate (1), the back tape (3) is placed on the lower side. Next, as shown in FIG. 3, a chip capacitor (4) is arranged at a predetermined position on the adhesive surface of the pack tape (3) in the opening (2) from the other surface using a chip mounter. As shown in FIG. 4, an embedded resin (6) shown in Table 1 is poured into a gap between the chip capacitor (4) disposed in the opening (2) and the opening (2) using a dispenser.

The embedded resin (6) is defoamed and thermally cured under the conditions of 100 ° C. × 80 minutes → 120 ° C. × 60 minutes → 160 ° C. × 10 minutes. As shown in FIG. 5, the surface (60) of the cured embedded resin (6) is roughly polished by using a belt sander, and then finish-polished by lap polishing. Next, as shown in FIG. 6, a via hole (7) is drilled in the flattened surface (60) using a carbon dioxide laser to expose the electrode (5) of the chip capacitor (4).

Thereafter, the exposed surface of the embedded resin (6) is roughened using a swelling solution and a KMnO ₄ solution. After the obtained roughened surface (61) is activated with a Pd catalyst, as shown in FIG. 7, copper plating (9) is applied in the order of electroless plating and electrolytic plating. This sample was subjected to a moisture resistance test at a time shown in Table 2 using a pressure cooker test under predetermined conditions (conditions: 121 ° C., humidity 100% by mass, 2.1 atm). A 10 mm wide cut is made in the copper plating (9) on the embedded resin of the sample after each time. The copper plating layer (9) is peeled off while being pulled in a direction perpendicular to the substrate according to JIS C 5012. The strength required for the peeling at this time is defined as the peel strength. Peel strength is 588 N / m (0.6 kg /
cm) or more. Table 2 shows the measurement results.

[0053]

[Table 2]

The results show that the embedded resins of Sample Nos. 1 to 5 and the wiring boards using the same, which are examples of the present invention, can maintain good peel strength even after the pressure cooker test under predetermined conditions. In particular, it can be seen that by adjusting the amount of carbon black added to a predetermined range, the insulating property can be improved satisfactorily. vice versa,
When the addition amount of carbon black is too large as in Comparative Examples Sample Nos. 6 to 9, not only is the insulation resistance lowered,
It can be seen that the reliability of the peel strength also decreases.

[0055]

According to the present invention, when an electronic component arranged in an opening (recess such as a through hole or a cavity) provided in a substrate is embedded using an embedding resin, a pressure cooker under a predetermined condition is used. Even after the test, high adhesion reliability with high peel strength can be ensured. A remarkable effect can be obtained when a fine wiring layer having a width of 150 μm or less is formed on the embedded resin, or when a wiring layer that flows a large current such as a power supply layer is formed. In particular, when a wiring layer for a power supply layer connected to an electronic component such as a capacitor having a power supply function is formed, high adhesion reliability can be ensured.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing an example in which a wiring board of the present invention is applied to a BGA board.

FIG. 2 is an explanatory view showing one embodiment of a method of manufacturing a wiring board according to the present invention.

FIG. 3 is an explanatory view showing one embodiment of a method for manufacturing a wiring board of the present invention.

FIG. 4 is an explanatory view showing one embodiment of a method for manufacturing a wiring board of the present invention.

FIG. 5 is an explanatory view showing one embodiment of a method for manufacturing a wiring board of the present invention.

FIG. 6 is an explanatory view illustrating one embodiment of a method for manufacturing a wiring board of the present invention.

FIG. 7 is an explanatory view illustrating one embodiment of a method for manufacturing a wiring board of the present invention.

FIG. 8 is an explanatory view showing one embodiment of a method for manufacturing a wiring board of the present invention.

FIG. 9 is an explanatory view illustrating one embodiment of a method for manufacturing a wiring board of the present invention.

FIG. 10 is an explanatory diagram showing an example in which the wiring board of the present invention is applied to a BGA board.

FIG. 11 is an explanatory diagram of a semiconductor device using an FC-PGA type multilayer printed wiring board which is one embodiment of the present invention.

FIG. 12 is a schematic view of a copper-clad core substrate having a thickness of 400 μm.

FIG. 13 is an explanatory view showing a state after patterning of a copper-clad core substrate having a thickness of 400 μm.

FIG. 14 is an explanatory diagram showing a state in which via holes and through holes are formed in a substrate in which insulating layers are formed on both surfaces of a core substrate.

FIG. 15 is an explanatory diagram showing a state after panel plating is applied to a substrate having an insulating layer formed on both surfaces of a core substrate.

FIG. 16 is an explanatory view of a substrate in which through holes are filled and filled.

FIG. 17 is an explanatory view showing a substrate formed by punching through holes.

FIG. 18 is an explanatory view showing a state in which a masking tape is attached to one surface of a substrate on which a through hole is punched and formed.

FIG. 19 is an explanatory view showing a state in which a multilayer chip capacitor is arranged on a masking tape exposed in a through hole.

FIG. 20 is an explanatory view showing a state in which a filling resin is filled in a through hole.

FIG. 21 is an explanatory view showing a state where a substrate surface is polished and flattened.

FIG. 22 is an explanatory view showing a state where a polished surface of a substrate is subjected to panel plating.

FIG. 23 is an explanatory view showing a state in which wiring is patterned.

FIG. 24 is an explanatory view showing a state in which a build-up layer and a solder resist layer are formed on a substrate.

FIG. 25 is an explanatory diagram of an FC-PGA type multilayer printed wiring board which is one embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Core board 2 Through-hole (opening) 3 Back tape 4 Electronic component 5 Electrode of electronic component 6 Embedded resin 60 Flat surface 61 Rough surface

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H05K 1/18 H05K 3/28 C 3/28 3/46 B 3/46 Q T H01L 23/12 B ( 72) Inventor Kazushige Obayashi 14-18, Takatsuji-cho, Mizuho-ku, Nagoya-shi, Aichi Japan Inside (72) Inventor Hisato Kashima 14-18 Takatsuji-cho, Mizuho-ku, Nagoya-shi, Aichi Japan In-house F term (reference) 4F100 AA37A AB17B AK01A AK53A BA02 CA23A GB43 JB12A JB13A JK06 YY00A 4J002 AA021 CD001 CD041 CD051 CD061 DA036 DE147 DJ007 DJ027 FD017 FD096 GF00 GQ00 GQ01A03A03A03A03DD GG08 GG12 5E336 AA08 BB03 BB15 BC26 BC31 CC31 CC51 GG01 GG12 GG14 5E346 AA04 AA06 AA12 AA15 AA42 AA43 AA60 BB01 CC02 CC08 CC31 DD02 DD22 EE31 FF04 GG15 GG27 GG28 GG40 HH08 H H11 HH18

Claims (8)

[Claims] An embedded resin for embedding an electronic component, wherein a peel strength of the copper layer after a pressure cooker test of a substrate having a copper layer formed on a cured product of the embedded resin is 588 N / m ( 0.6 kg / cm) or more. However, the conditions of the pressure cooker test were 121 ° C. × 100% by mass of humidity ×
2. Atmospheric pressure x 168 hours. The peel strength is measured according to JIS C 5012, and the width of the copper layer is 10 mm. 2. An embedding resin for embedding an electronic component, wherein the substrate having a copper layer formed on a cured product of the embedding resin has a peel strength of 600 N / m after a pressure cooker test. 0.61 kg / cm) or more. However, the conditions of the pressure cooker test were 121 ° C. × 100% by mass of humidity ×
2. Atmospheric pressure x 336 hours. The peel strength is measured according to JIS C 5012, and the width of the copper layer is 10 mm. 3. The embedding resin according to claim 1, wherein the content of carbon black is 0.5% by mass or less. 4. The embedding resin according to claim 2, wherein the content of carbon black is 0.4% by mass or less. 5. The embedding resin according to claim 1, wherein the resin component of the embedding resin includes at least a thermosetting resin and at least one or more inorganic fillers. . 6. The embedding according to claim 5, wherein the thermosetting resin is at least one selected from a bisphenol epoxy resin, a naphthalene type epoxy resin, a phenol novolak type epoxy resin and a cresol novolak type epoxy resin. resin. 7. A wiring board, wherein an electronic component is embedded using the embedding resin according to any one of claims 1 to 6. 8. A build-up layer in which insulating layers and wiring layers are alternately laminated on at least one surface of a core substrate, and an opening is formed to penetrate at least one of the core substrate and the build-up layer. 7. An electronic component using a substrate and disposed in the opening, the electronic component being disposed in the opening.
A wiring board, wherein the wiring board is embedded using the embedding resin according to any one of the above.