JP2007288179A - Wiring board, and ceramic chip to be buried - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board having excellent connection reliability between a semiconductor element and a mother board. <P>SOLUTION: A core material 11 of a wiring board 10 with a built-in ceramic chip has an accommodation hole 91 opening at a first main surface 12 of core and a second main surface 13 of core. A ceramic capacitor 101 is accommodated in the accommodation hole 91 while a first main surface 102 of chip is directed to the same side of the first main surface 12 of core, and a second main surface 103 of chip is directed to the same side of the second main surface 13 of core. A first core side insulating layer 33 is formed on the first main surface 12 of core and the first main surface 102 of chip, and a second core side insulating layer 34 is formed on the second main surface 13 of core and the second main surface 103 of chip. In the second core side insulating layer 34, a via hole 54 and a via conductor 50 are not formed in a region corresponding to the second main surface 103 of chip. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a wiring board having a built-in ceramic chip and a ceramic chip for embedding.

  In recent years, semiconductor integrated circuit elements (IC chips) used for a CPU of a computer have been increased in speed and function, and accordingly, the number of terminals is increased and the pitch between terminals tends to be narrowed. In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, generally, a technique is adopted in which an IC chip is mounted on an IC chip mounting wiring board, and the IC chip mounting wiring board is mounted on a motherboard. As this type of IC chip mounting wiring board, for example, a core part is formed by embedding a ceramic chip in a core material made of a polymer material, and build-up layers are formed on the front and back surfaces of the core part. Conventionally proposed (see, for example, Patent Documents 1 and 2).

The conventional IC chip mounting wiring board is manufactured, for example, by the following procedure. First, a core material made of a polymer material having an accommodation hole portion that opens on both the core surface and the core back surface is prepared. At the same time, a ceramic chip for embedding in which a plurality of terminal electrodes are provided so as to protrude from the chip front surface and the chip back surface is prepared. Next, the taping process which affixes an adhesive tape on the core material back surface side is performed, and the core material back surface side opening of an accommodation hole part is sealed beforehand. And the ceramic chip for embedding is accommodated in an accommodation hole part, and the chip | tip back surface is affixed on the adhesive surface of an adhesive tape, and is temporarily fixed. Next, after the gap between the inner surface of the accommodation hole and the side surface of the embedding ceramic chip is filled with a resin filler, a fixing process is performed in which the gap is cured to fix the embedding ceramic chip to the core material. Thereafter, the build-up layer is formed by alternately forming an interlayer insulating layer mainly composed of a polymer material and a conductor layer on the front surface and the back surface of the core portion made of the core material and the embedded ceramic chip. Form. As a result, a desired IC chip mounting wiring board is obtained.
JP 2002-100870 A JP-A-2005-39243

  Incidentally, in the conventional manufacturing method, as shown in FIG. 17, in order to fix the embedding ceramic chip 204 to the core material 201, a gap between the inner surface 203 of the accommodating hole 202 and the side surface 205 of the embedding ceramic chip 204 is used. 206 is filled with a resin filler 207. However, since the ceramic chip 204 has thickness variation and warpage, and further, there is an error in the filling amount of the resin filler 207, so that it is flush with the surface of the ceramic chip 204 (so that the height coincides). ) It is difficult to embed the resin filler 207. Further, if the resin filler 207 covers the chip surface due to too much filling amount, problems such as build-up layer floating and delamination occur, and therefore the resin filler 207 is usually filled in a small amount. . Therefore, the height of the resin filler 207 in the gap 206 between the core material 201 (accommodating hole 202) and the ceramic chip 204 is lower than that of the core material 201 and the chip 204, and a recess 209 is formed in that portion. It will be. The influence of the concave portion 209 spreads to the surface of the buildup layer, resulting in a problem that the flatness is lowered and it is difficult to mount the IC chip.

  Specifically, as shown in FIG. 18, since there are recesses 209 on the upper surface side of the core material 201, the ceramic chip 204, and the resin filler 207, the resin has unevenness on the upper surface side and thickness variation. The insulating layer 210 is formed. In addition, via holes 211 and via conductors 212 are formed in the resin insulating layer 210 for connection to the conductor layer of the buildup layer. When via processing is performed using a laser processing apparatus in order to form the via hole 211, since the resin insulating layer 210 has irregularities, the workability varies depending on its thickness, and the shape of the via hole 211 is determined. Will be different. Further, when the via hole 211 is formed in a thin portion of the resin insulating layer 210, there is a problem that chipping occurs at the location of the via hole 211 in the desmear process after laser processing, causing a short circuit. Further, when the via hole 211 is formed in the thick portion of the resin insulating layer 210, there is a concern that the via hole 211 is not formed by laser processing.

  The present invention has been made in view of the above problems, and a first object of the invention is to provide a wiring board excellent in connection reliability with a semiconductor element and a mother board. The second object is to provide a ceramic chip for embedding suitable for realizing such a wiring board.

  And as a means (means 1) for solving the said subject, it has a core 1st main surface and a core 2nd main surface, and the accommodation hole opened in the said core 1st main surface and the said core 2nd main surface A core material having a portion, a chip first main surface and a chip second main surface, an internal conductor is formed therein, the chip first main surface is directed to the same side as the core first main surface, and A ceramic chip for embedding accommodated in the accommodation hole with the chip second main surface facing the same side as the core second main surface, and on the core first main surface and the chip first main surface A first core-side insulating layer having a via hole and a via conductor formed in a region corresponding to the chip first main surface, the core second main surface, and the chip second main surface; A second core in which holes and via conductors are not formed in a region corresponding to the chip second main surface An element mounting formed on an insulating layer and the first core side insulating layer, having a structure in which an interlayer insulating layer and a conductor layer are alternately stacked, and having a plurality of connection terminals on which a semiconductor element can be surface-mounted on a surface layer portion There is a wiring board comprising: a side buildup layer, wherein the flatness of the second core side insulating layer is lower than the flatness of the first core side insulating layer. In addition, as another means (means 2) for solving the above-described problem, the housing has a core first main surface and a core second main surface, and is opened at the core first main surface and the core second main surface. A core material having a hole, a chip first main surface and a chip second main surface, and an internal conductor is formed inside, the chip first main surface facing the same side as the core first main surface; and A ceramic chip for embedding accommodated in the accommodation hole with the second main surface of the chip facing the same side as the second main surface of the core, and the first main surface of the core and the upper surface of the first chip main surface Arranged on the first core side insulating layer in which via holes and via conductors are formed in a region corresponding to the chip first main surface, the core second main surface and the chip second main surface, The second core side in which the via hole and the via conductor are not formed in the region corresponding to the chip second main surface An element mounting formed on an edge layer and the first core-side insulating layer, having a structure in which an interlayer insulating layer and a conductor layer are alternately stacked, and having a plurality of connection terminals on which a semiconductor element can be surface-mounted on a surface layer portion And a side buildup layer, wherein the thickness variation of the first core side insulating layer is smaller than the thickness variation of the second core side insulating layer.

  Therefore, according to the wiring boards of the means 1 and 2, the first core side insulating layer is formed on the core first main surface and the chip first main surface, and on the core second main surface and the chip second main surface. A second core side insulating layer is formed. In the first core-side insulating layer, a plurality of via holes and a plurality of via conductors are formed in a region corresponding to the chip first main surface. Since the first core side insulating layer has higher flatness and less thickness variation than the second core side insulating layer, it is possible to form via holes and via conductors having a uniform shape without processing variations. Therefore, the via conductor can be reliably connected to the terminals of the semiconductor element having a narrow inter-terminal pitch via the element mounting side buildup layer formed on the first core side insulating layer. On the other hand, since the via hole and the via conductor are not formed in the region corresponding to the chip second main surface of the second core side insulating layer with low flatness, the via conductor in the second core side insulating layer is not connected. Problems such as short circuits are prevented. From the above, it is possible to provide a wiring board excellent in connection reliability with a semiconductor element and a mother board.

  The core material forms part of the core portion of the wiring board, and is formed in a flat plate shape having, for example, a core first main surface and a core second main surface located on the back side thereof. Such a core material has one or more housing holes for housing the embedding ceramic chip. The accommodation hole is a through hole that opens at the core first main surface and the core second main surface.

  The wiring board preferably includes a resin filling portion that fixes the embedding ceramic chip to the core material by filling a gap between the inner surface of the accommodation hole and the side surface of the embedding ceramic chip. By providing this resin filling portion, it becomes possible to fix the ceramic chip to the core material so that the core first main surface and the chip first main surface are flush with each other. The flatness of the first core-side insulating layer disposed on the surface side can be made higher than the flatness of the second core-side insulating layer. Further, the thickness variation of the first core side insulating layer can be made smaller than the thickness variation of the second core side insulating layer.

In the wiring board, the core first main surface, the chip first main surface, and the core first main surface exposed surface of the resin filling portion are at the same level, and the flatness of the core side insulating layer is 0 μm or more and 30 μm. The following is preferable. As a result, the flatness of the first core-side insulating layer is increased, and as a result, the unevenness on the surface of the element mounting side build-up layer formed thereon can be suppressed, so that the semiconductor element can be mounted reliably. Can do. Here, the measuring method of flatness is not particularly limited, and for example, the following method may be adopted. (1) When a ceramic chip for embedding is embedded in the central portion of the wiring board, it is cut at a plane passing through the central portion of the wiring board. (2) At this time, a linear reference line is assumed corresponding to a position of the first core main surface of the core substrate, and the distance between the reference line and the surface of the first core-side insulating layer is nine locations. taking measurement. Specifically, three arbitrarily spaced points on the embedding ceramic chip, three arbitrarily spaced points on the core substrate without the embedding ceramic chip (the region on the left side of the chip as a reference), Measurements are made at three arbitrarily spaced points on a non-core substrate (the region on the right side of the chip as a reference) (total of 9 points). (3) Then, the difference between the maximum value and the minimum value of the nine measured values obtained is calculated, and this value is defined as “flatness”. The method for measuring the flatness of the second core-side insulating layer is basically the same.
Further, the thickness variation of the first core-side insulating layer is preferably 15 μm or less, and more preferably 10 μm or less. In this case, since the flatness of the first core-side insulating layer is increased, unevenness on the surface of the element mounting side build-up layer formed thereon can be suppressed, so that the semiconductor element can be reliably mounted. . Here, the thickness variation measurement method is not particularly limited, and for example, the following method may be employed. (1) When a ceramic chip for embedding is embedded in the central portion of the wiring board, the first core-side insulating layer appearing on the cut surface is cut at a plane passing through the central portion of the wiring board and the thickness of the first core side insulating layer is nine Measure with Specifically, three arbitrarily spaced points on the embedding ceramic chip, three arbitrarily spaced points on the core substrate without the embedding ceramic chip (the region on the left side of the chip as a reference), Measurements are made at three arbitrarily spaced points on a non-core substrate (the region on the right side of the chip as a reference) (total of 9 points). When the measurement is performed on the embedding ceramic chip, the distance from the surface of the terminal electrode to the surface of the first core side insulating layer is defined as “the thickness of the first core side insulating layer”. When measurement is performed on a core substrate without a ceramic chip for embedding, the distance from the core substrate wiring surface to the surface of the first core side insulating layer is defined as the “thickness of the first core side insulating layer”. (2) Then, the average of the nine measured values obtained is calculated, and this value is defined as “thickness variation”. The method for measuring the thickness variation of the second core-side insulating layer is basically the same.

  The thickness of the embedding ceramic chip is preferably equal to or less than the thickness of the core material. In this case, the thickness variation of the second core-side insulating layer formed on the core second main surface and the chip second main surface can be suppressed.

  Although the material which forms the said core material is not specifically limited, A preferable core material is mainly formed of a polymer material. Specific examples of the polymer material for forming the core material include, for example, EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleimide / triazine resin), PPE resin (polyphenylene ether resin), etc. There is. In addition, composite materials of these resins and glass fibers (glass woven fabric or glass nonwoven fabric) or organic fibers such as polyamide fibers may be used.

  The ceramic chip for embedding is preferably a ceramic sintered body having a chip first main surface and a chip second main surface. As this ceramic sintered body, a sintered body of a high-temperature fired ceramic such as alumina, aluminum nitride, boron nitride, silicon carbide, silicon nitride, etc. is preferably used, and also for borosilicate glass or lead borosilicate glass. A sintered body of low-temperature fired ceramic such as glass ceramic to which an inorganic ceramic filler such as alumina is added is preferably used. In this case, it is also preferable to use a sintered body of a dielectric ceramic such as barium titanate, lead titanate, or strontium titanate depending on the application. When a dielectric ceramic sintered body is used, a ceramic capacitor having a large capacitance can be easily realized.

  An internal conductor is formed inside the ceramic chip. The material for forming such an internal conductor is not particularly limited, but it is preferable to use a metal that can be sintered simultaneously with the ceramic, for example, nickel, molybdenum, tungsten, titanium, or the like. When a low-temperature fired ceramic sintered body is selected, copper, silver, or the like can be further used as a material for forming the internal conductor. The internal conductor may be a via conductor extending in the thickness direction of the ceramic sintered body or may be an inner conductor layer extending in the surface direction of the ceramic sintered body.

  The embedded ceramic chip is an embedded ceramic capacitor having a plurality of connection terminals connected to the inner conductor on the first chip main surface side and the second chip main surface side, and on the second chip main surface side. The plurality of connection terminals are preferably non-connection terminals covered with the second core-side insulating layer. When the non-connected terminal is provided on the chip second main surface side in this way, the adhesion strength between the chip second main surface and the second core side insulating layer is improved, so that the buildup layer is not lifted or delaminated. be able to.

  The embedded ceramic chip is a embedded ceramic capacitor having a plurality of connection terminals connected to the internal conductor on the first main surface side of the chip and an adhesive conductor layer on the second main surface side of the chip. Preferably, the contact conductor layer on the chip second main surface side is covered with the second core-side insulating layer. Thus, even if the adhesion conductor layer is provided on the second main surface side of the chip, the adhesion strength between the second main surface of the chip and the second core side insulating layer is improved, so that the build-up layer is not lifted or delaminated. can do. The area ratio of the adhesion conductor layer on the chip second main surface side is not particularly limited, but it is preferably as large as possible from the viewpoint of improving adhesion, for example, 30% or more, further 50% or more, particularly 70. % Or more is preferable. The contact conductor layer may or may not be connected to the inner conductor of the embedding ceramic capacitor, but it is preferable that it is not connected.

  A plurality of connection terminals formed on the chip first main surface side and the chip second main surface of the ceramic chip can be sintered simultaneously with the ceramic, so that the metal material suitable for metallization, for example, nickel, molybdenum, tungsten, titanium Etc. are used.

  As the metal constituting the adhesion conductor layer, for example, nickel, molybdenum, tungsten, titanium, copper, silver or the like can be used, and in particular, the same kind of metal material as that of the connection terminal made of the metallized layer is used. It is preferable to do. With such a configuration, it is possible to form the contact conductor layer in the same process as the connection terminal, and thus it is easy to achieve cost reduction.

  The surfaces of the plurality of connection terminals and the contact conductor layer are preferably rougher than the ceramic sintered body. That is, when the configuration of the present invention is adopted, the adhesion strength with the core-side insulating layer can be improved by increasing the ratio of the rough surface on the ceramic chip side at the bonding interface with the core-side insulating layer.

  It is desirable that a metal layer made of a metal softer than the metal constituting the plurality of connection terminals and the contact conductor layer is formed on the surfaces of the plurality of connection terminals and the contact conductor layer. The reason is as follows. That is, since the plurality of connection terminals and the contact conductor layer made of the metallized layer are both sintered metal layers and relatively hard, it is extremely difficult to directly roughen the surface using an etchant or the like. It is. Therefore, if a soft metal layer is formed and the layer is roughened, a desired rough surface can be obtained relatively easily and reliably. Here, the surface roughness Ra of the metal layer is preferably 0.2 μm or more, and particularly preferably 0.2 μm or more and 1.0 μm or less. If the surface roughness Ra of the metal layer is not more than this level, the surface will not be much different from the surface roughness of the ceramic sintered body, and even if an adhesion conductor layer is provided, the adhesion strength cannot be sufficiently improved. It is.

  In this case, the metal layer is appropriately selected according to the types of the plurality of connection terminals and the contact conductor layer. For example, when the plurality of connection terminals and the contact conductor layer are made of nickel, the metal layer is a copper layer. It is preferable to select (especially a copper plating layer). This is because such a combination makes it possible to form a rough surface more easily and reliably than when directly roughening the surface of nickel. In this case, the copper plating layer is preferably formed to have a thickness of 5 μm or more for safety in consideration of the amount removed by the roughening treatment. As a method for forming a soft metal layer, the above plating method is preferable because it is simple and low in cost. However, in addition to the plating method, it is also possible to employ a technique such as sputtering, CVD, or vacuum deposition.

  Here, the ceramic chip for embedding may be a ceramic capacitor having a structure in which the first internal electrode layers and the second internal electrode layers are alternately stacked via ceramic dielectric layers. When the embedded ceramic chip having a function as a capacitor is used as described above, for example, the stray inductance can be reliably reduced by being disposed in the vicinity of the semiconductor element, so that the semiconductor element is stably operated. It becomes possible.

  The build-up layer constituting the wiring board has a structure in which interlayer insulating layers mainly composed of a polymer material and conductor layers are connected alternately. The build-up layer may be formed only on one side of the core part (that is, only on the core first main surface and the chip first main surface), and on both sides of the core part (that is, the core first main surface and the chip main surface). The first main surface of the chip, the second main surface of the core, and the second main surface of the chip) may be formed. For the build-up layer formed on the core first main surface and the chip first main surface, the semiconductor element mounting portion is set in a region corresponding to the ceramic chip on the surface. Since the semiconductor element can be mounted on such a semiconductor element mounting portion, the difference in thermal expansion coefficient from the semiconductor element can be reduced as compared with the case where the semiconductor element mounting portion is provided in the core material. Therefore, the structure can easily reduce the influence of thermal stress acting on the semiconductor element.

  Hereinafter, a method for manufacturing a wiring board will be described.

  In the core material preparation step, a plate-shaped core material having a core first main surface and a core second main surface and having a receiving hole portion opened in the core first main surface and the core second main surface is conventionally used. Prepared in advance using a known technique.

  Further, in the embedding ceramic chip preparation step, an embedding ceramic chip made of a ceramic sintered body having a chip first main surface and a chip second main surface and having an internal conductor formed in the ceramic sintered body is conventionally obtained. Prepared in advance using a known technique.

  In the subsequent masking step, the masking material is disposed so as to be in close contact with the core first main surface side to close the opening of the accommodation hole. It is preferable to use a peelable adhesive tape as the masking material. However, a masking material that does not have an adhesive layer can also be used if it can be brought into close contact with the core first main surface side.

  Thereafter, in the fixing step, the chip first main surface of the ceramic chip for embedding is directed to the same side as the core first main surface, and the chip second main surface is directed to the same side as the core second main surface to enter the receiving hole. Contains a ceramic chip for embedding. Here, when an adhesive tape is used as the masking material, an embedding ceramic chip is attached to the adhesive surface of the adhesive tape and temporarily fixed. In this state, a resin filling portion is formed by filling the gap between the inner surface of the accommodation hole portion and the side surface of the embedding ceramic chip with a resin filler made of a polymer material. As the resin filler, a thermosetting resin is suitable, and when this is used, heat treatment is performed after filling. As a result, the embedded ceramic chip is fixed in the accommodation hole by the cured resin filling portion. Instead of filling with the resin filler, the gap may be filled with a part of the second core-side insulating layer and fixed.

  Thereafter, in the masking material removal step, the masking material arranged on the core first main surface side so as to close the opening of the accommodation hole is removed.

  In the cleaning and polishing step, the core first main surface and the chip first main surface are cleaned with a solvent by acid degreasing and then polished. Polishing is performed using a conventionally known polishing apparatus (for example, a buff polishing apparatus, a lapping apparatus, etc.), and at that time, the core first main surface side is scraped off by about 1 μm to 5 μm, for example. In this step, it is preferable to perform solvent cleaning first and then perform polishing. This is because the removal of the adhesive and the flattening of the surface can be reliably performed in this order.

  In the first insulating layer forming step, the first core-side insulating layer is formed on the core first main surface exposed through the masking material removing step, the chip first main surface, and the core first main surface-side exposed surface of the resin filling portion. Form.

  In the second core side insulating layer forming step, the second core side insulating layer is formed on the core second main surface, the chip second main surface, and the core second main surface side exposed surface of the resin filling portion.

  After the cleaning and polishing step and before the insulating layer forming step, a roughening step is performed to roughen the surface of the metal layer on the plurality of connection terminals and the contact conductor layer formed on the embedding ceramic chip. Is preferred. By roughening the metal layer, the adhesion of the core-side insulating layer can be enhanced. Further, when conductor layers are formed on the core first main surface and second main surface of the core material, the conductor layers are roughened simultaneously with the roughening of the metal layers of the connection terminals and the contact conductor layer. It is preferable to carry out. The reason is that man-hours are reduced and productivity is improved as compared with the case of performing roughening separately.

In the via formation step, a plurality of via holes and a plurality of via conductors are formed in the first core side insulating layer, while the second core side of the chip and the core second main surface side of the resin filler in the second core side insulating layer A plurality of via holes and a plurality of via conductors are formed avoiding a region corresponding to the exposed surface. In this via formation process, a plurality of via holes are formed by laser processing, and then desmear processing for removing smear in the plurality of via holes is performed, and then plating is performed to form filled via conductors in the plurality of via holes. preferable. If it does in this way, a favorable via conductor can be formed for connection with the conductor pattern formed in the element mounting side buildup layer. Here, the via conductor may be a conformal via or a filled via, but is preferably a filled via from the viewpoint of reducing resistance. Conformal via means that a plating layer with a uniform thickness is formed along the shape of the via hole. Therefore, the via hole is not completely filled with the plating layer, and a via having a depression is used. pointing. On the other hand, a filled via refers to a type of via that has a plating layer with a non-uniform thickness, the via hole is completely filled with the plating layer, and has no depression.
In the subsequent buildup layer forming step, after the via forming step, a buildup layer is formed on the core first main surface and the chip first main surface based on a conventionally known technique.

As another means (means 3) for solving the above problems, the chip first main surface, the chip second main surface, the internal conductor formed inside, the chip first main surface side, There is a ceramic chip for embedding characterized by comprising a plurality of connection terminals connected to the internal conductor, and a contact conductor layer disposed on the second main surface side of the chip. Therefore, according to the means 3, when the ceramic chip is embedded in the wiring board, the adhesion strength between the second main surface of the chip and the insulating layer facing it is improved, and the build-up layer is prevented from floating and delamination. be able to.
In this case, the area ratio of the adhesion conductor layer occupying the chip second main surface side is not particularly limited, but it is preferably as large as possible from the viewpoint of improving adhesion, for example, 30% or more, further 50% or more, In particular, it is preferably 70% or more. The contact conductor layer may or may not be connected to the inner conductor of the embedding ceramic capacitor, but it is preferable that it is not connected.

[First Embodiment]

  Hereinafter, a first embodiment in which a ceramic chip built-in wiring board of the present invention is embodied will be described in detail with reference to the drawings.

  As shown in FIG. 1, a ceramic chip built-in wiring board 10 of this embodiment is a wiring board for mounting an IC chip, and includes a flat core material 11 made of glass epoxy, a ceramic capacitor 101, and resin insulation. Layers (core-side insulating layers) 33, 34, a buildup layer 31 formed on the resin insulating layer 33, and a buildup layer 32 formed on the resin insulating layer 34. Through-hole conductors 16 are formed at a plurality of locations in the core material 11. The through-hole conductor 16 connects and connects the upper surface 12 side and the lower surface 13 side of the core material 11. The inside of the through-hole conductor 16 is filled with a closing body 17 such as an epoxy resin. A conductor layer 41 made of copper is patterned on the upper surface 12 and the lower surface 13 of the core material 11, and each conductor layer 41 is electrically connected to the through-hole conductor 16. Furthermore, resin insulating layers (core-side insulating layers) 33 and 34 are formed on the upper surface 12 and the lower surface 13 of the core material 11 so as to cover the conductor layer 41.

  The buildup layer 31 formed on the upper surface 12 side of the core material 11 is formed by alternately laminating core first main surface side conductor layers 242 made of copper and resin insulating layers 35 (so-called interlayer insulating layers) made of epoxy resin. It has a structure. Terminal pads 44 are formed in an array at a plurality of locations on the surface of the resin insulation layer 35. The surface of the resin insulating layer 35 is almost entirely covered with a solder resist 37. An opening 46 for exposing the terminal pad 44 (connection terminal) is formed at a predetermined location of the solder resist 37. A plurality of solder bumps 45 are provided on the surface of the terminal pad 44. Each solder bump 45 is electrically connected to the surface connection terminal 22 of the IC chip 21 (semiconductor integrated circuit element). Each terminal pad 44 and each solder bump 45 are located in a region immediately above the ceramic capacitor 101 in the buildup layer 31, and this region becomes the semiconductor element mounting portion 23. A via conductor 43 is provided in the resin insulating layer 33, and a via conductor 47 is provided in the resin insulating layer 35. Most of these via conductors 43 and 47 are arranged coaxially, and the conductor layers 41 and 42 and the terminal pads 44 are electrically connected to each other through them.

  The buildup layer 32 formed on the lower surface 13 side of the core material 11 has substantially the same structure as the buildup layer 31 described above. That is, the buildup layer 32 has a structure in which the core second main surface side conductor layer 342 made of copper and the resin insulating layer 36 made of epoxy resin are alternately laminated. BGA pads 48 are formed in a lattice pattern at a plurality of locations on the lower surface of the resin insulating layer 36. The lower surface of the resin insulating layer 36 is almost entirely covered with a solder resist 38. An opening 40 for exposing the BGA pad 48 is formed at a predetermined portion of the solder resist 38. On the surface of the BGA pad 48, a plurality of solder bumps 49 are provided for electrical connection with a mother board (not shown). The wiring board 10 shown in FIG. 1 is mounted on a mother board (not shown) by each solder bump 49. A via conductor 50 is provided in the resin insulating layer 34, and a via conductor 51 is provided in the resin insulating layer 36. In the present embodiment, the via conductor 50 of the resin insulating layer 34 is disposed coaxially with the through-hole conductor 16 and the via conductor 51 at a position corresponding to the through-hole conductor 16. The conductor layers 41 and 42 and the BGA pad 48 are electrically connected to each other through the via conductors 50 and 51.

  The core material 11 has a rectangular accommodation hole 91 in a plan view that opens at the center of the upper surface 12 and the center of the lower surface 13. That is, the accommodation hole 91 is a through hole. A ceramic capacitor 101 (embedded ceramic chip) shown in FIGS. 2, 3 and the like is housed in the housing hole 91 in an embedded state. The ceramic capacitor 101 has the chip first main surface 102 (the upper surface in FIGS. 1 and 2) facing the same side as the core first main surface 12 of the core material 11 and the chip second main surface 103 (FIGS. Then, the lower surface is accommodated with the core material 11 facing the same side as the core second main surface 13. The ceramic capacitor 101 of this embodiment has a rectangular flat plate shape of 12.0 mm long × 12.0 mm wide × 0.75 mm thick. The thickness of the ceramic capacitor 101 is equal to or less than the thickness of the core material 11.

  Further, a gap 93 between the inner surface 92 of the accommodation hole 91 and the side surface 106 of the ceramic capacitor 101 is filled with a resin filler 95 made of a polymer material (thermosetting resin in the present embodiment), and the resin filling portion 97. Is formed. The resin filling portion 97 has a function of fixing the ceramic capacitor 101 to the core material 11 and absorbing the deformation of the ceramic capacitor 101 and the core material 11 in the surface direction and the thickness direction by its own elastic deformation. . In the present embodiment, the upper end surface (exposed surface on the core first main surface 12 side) of the resin filler 97 (resin filler 95) is the core first main surface 12 of the core material 11 and the chip first of the ceramic capacitor 101. The lower end surface (exposed surface on the core second main surface 13 side) of the resin filling portion 97 substantially coincides with the main surface 102, and is higher than the core second main surface 13 of the core material 11 and the chip second main surface 103 of the ceramic capacitor 101. It is depressed on the upper side.

  As shown in FIGS. 1 to 3, the ceramic capacitor 101 of this embodiment is a so-called via array type ceramic capacitor. The ceramic sintered body 104 constituting the ceramic capacitor 101 is a plate-like object having a chip first main surface 102 (upper surface) and a chip second main surface 103 (lower surface). The ceramic sintered body 104 has a structure in which first internal electrode layers 141 (internal conductors) and second internal electrode layers 142 (internal conductors) are alternately stacked via ceramic dielectric layers 105. The ceramic dielectric layer 105 is made of a sintered body of barium titanate, which is a kind of high dielectric constant ceramic, and functions as a dielectric (insulator) between the first internal electrode layer 141 and the second internal electrode layer 142. Each of the first internal electrode layer 141 and the second internal electrode layer 142 is a layer formed mainly of nickel, and is disposed every other layer inside the ceramic sintered body 104.

  A number of via holes 130 are formed in the ceramic sintered body 104. These via holes 130 penetrate the ceramic sintered body 104 in the thickness direction and are arranged in a lattice shape (array shape) over the entire surface. In each via hole 130, a plurality of via conductors 131 and 132 (internal conductors) penetrating between the upper surface 102 and the lower surface 103 of the ceramic sintered body 104 are formed using nickel as a main material. Each first via conductor 131 passes through each first internal electrode layer 141 and electrically connects them to each other. Each second via conductor 132 penetrates each second internal electrode layer 142 and electrically connects them to each other.

  On the upper surface 102 of the ceramic sintered body 104, a plurality of first external terminal electrodes 111 and 112 (terminal electrodes) are provided so as to project. A plurality of second external terminal electrodes 121 and 122 protrude from the lower surface 103 of the ceramic sintered body 104. The first external terminal electrodes 111 and 112 on the upper surface 102 side are electrically connected to the via conductor 43. On the other hand, the second external terminal electrodes 121 and 122 on the lower surface 103 side are non-connected terminals that are not connected to the outside. In addition, the substantially central portions of the bottom surfaces of the first external terminal electrodes 111 and 112 are directly connected to the end surfaces of the via conductors 131 and 132 on the top surface 102 side, and the substantially central portions of the bottom surfaces of the second external terminal electrodes 121 and 122. Are directly connected to the end surfaces of the via conductors 131 and 132 on the lower surface 103 side. Therefore, the external terminal electrodes 111 and 121 are electrically connected to the via conductor 131 and the first internal electrode layer 141, and the external terminal electrodes 112 and 122 are electrically connected to the via conductor 132 and the second internal electrode layer 142.

  As shown in FIG. 4, the first external terminal electrodes 111 and 112 are made of a metallized layer 116 made of nickel as a main material. The surface of the metallized layer 116 is entirely covered with a copper plating layer 117 (metal layer). Similarly, the second external terminal electrodes 121 and 122 are also made of the metallized layer 116, and the surface of the metallized layer 116 is covered with the copper plating layer 117. That is, the copper plating layer 117 is made of a metal that is softer than the metal constituting the metallized layer 116. Since the surface of the copper plating layer 117 is roughened, the surfaces of the first external terminal electrodes 111 and 112 are rougher than the upper surface 102 of the ceramic sintered body 104. Similarly, the surfaces of the second external terminal electrodes 121 and 122 are also rougher than the lower surface 103 of the ceramic sintered body 104. In this embodiment, the surface roughness Ra of the copper plating layer 117 is set to about 0.5 μm. Further, the external terminal electrodes 111, 112, 121, 122 when viewed from the direction perpendicular to the upper surface 102 (part thickness direction) are substantially circular (see FIG. 3).

  A resin insulating layer 33 (first core side insulating layer) is formed on the chip first main surface 102 of the ceramic sintered body 104 so as to cover the first external terminal electrodes 111 and 112. A resin insulating layer 34 (second core-side insulating layer) is formed on 103 so as to cover the second external terminal electrodes 121 and 122. A plurality of via holes 53 are formed in a region corresponding to the chip first main surface 102 in the resin insulating layer 33 on the upper surface side. By plating the via hole 53, a via conductor 43 is formed therein. Note that the via conductor 43 in this embodiment is a so-called filled via.

  On the other hand, a via hole and a via conductor are not formed in a region corresponding to the chip second main surface 103 in the resin insulating layer 34 on the lower surface side, and a region (through-hole conductor) around the chip second main surface 103 is formed. A plurality of via holes 54 are formed at a position directly below 16. By plating the via hole 54, the via conductor 50 is formed inside. Thus, in this embodiment, since the via hole and the via conductor are not formed in the region corresponding to the chip second main surface 103, problems caused by variations in the via processing, that is, the unconnected via conductor or Problems such as shorts are avoided.

  In the ceramic capacitor 101 of the present embodiment, only the external terminal electrodes 111 and 112 provided on the chip first main surface 102 function as connection terminals, and the external terminal electrodes 111 and 112 provided on the chip second main surface 103 are It is an unconnected terminal that is not connected to the outside. The ceramic capacitor 101 is connected to the motherboard side by using the via conductor 43 of the resin insulation layer 33, the conductor layer 42 of the buildup layer 31, the through-hole conductor 16 of the core material 11, the via conductor 50 of the resin insulation layer 34, and the like. To be done through.

  When the first external terminal electrodes 111 and 112 are energized from the motherboard side via the via conductors 50 and 51, the through-hole conductor 16 and the like, and a voltage is applied between the first internal electrode layer 141 and the second internal electrode layer 142, For example, positive charges are accumulated in the first internal electrode layer 141, and negative charges are accumulated in the second internal electrode layer 142, for example. As a result, the ceramic capacitor 101 functions as a capacitor. In the ceramic capacitor 101, the first via conductors 131 and the second via conductors 132 are alternately arranged adjacent to each other, and the directions of the currents flowing through the first via conductors 131 and the second via conductors 132 are opposite to each other. It is set to face. Thereby, the inductance component is reduced.

  Next, a method for manufacturing the ceramic chip built-in wiring board 10 of the present embodiment will be described.

  In the core material preparation step, the core material 11 is manufactured by a conventionally known method. In the embedding ceramic chip preparation step, the ceramic capacitor 101 is manufactured by a conventionally known method, and the core material 11 and the ceramic capacitor 101 are prepared in advance. deep.

  In the core material preparation step, the core material 11 is produced as follows. First, a copper clad laminate is prepared in which a copper foil having a thickness of 35 μm is attached to both surfaces of a base having a length of 400 mm × width of 400 mm × thickness of 0.80 mm. Next, drilling is performed on the copper-clad laminate using a drill, and a through hole for forming the through-hole conductor 16 is formed in advance at a predetermined position. Moreover, a copper-clad laminated board is drilled using a router, and the through-hole used as the accommodation hole part 91 is previously formed in the predetermined position (refer FIG. 5). In addition, the through-hole used as the accommodation hole part 91 is a hole with a substantially square cross section which has a side of 14.0 mm and a radius of 3 mm at four corners. And the through-hole conductor 16 is formed by performing electroless copper plating and electrolytic copper plating according to a conventionally well-known method. Next, after the paste which has an epoxy resin as a main component is printed in the cavity part of the through-hole conductor 16, the obstruction | occlusion body 17 is formed by hardening. Further, the copper foil on both sides of the copper clad laminate is etched to pattern the conductor layer 41 by, for example, a subtractive method. Specifically, after the electroless copper plating, electrolytic copper plating is performed using the electroless copper plating layer as a common electrode. Further, the dry film is laminated, and the dry film is exposed and developed to form a dry film in a predetermined pattern. In this state, unnecessary electrolytic copper plating layer, electroless copper plating layer and copper foil are removed by etching. Thereafter, the core material 11 is obtained by peeling the dry film.

  In the embedding ceramic chip preparation step, the ceramic capacitor 101 is manufactured as follows. That is, a ceramic green sheet is formed, and nickel paste for internal electrode layers is screen printed on the green sheet and dried. As a result, a first internal electrode portion that later becomes the first internal electrode layer 141 and a second internal electrode portion that becomes the second internal electrode layer 142 are formed. Next, the green sheets on which the first internal electrode portions are formed and the green sheets on which the second internal electrode portions are formed are alternately stacked, and each green sheet is integrated by applying a pressing force in the sheet stacking direction. To form a green sheet laminate.

  Further, a number of via holes 130 are formed through the green sheet laminate using a laser processing machine, and a via conductor nickel paste is filled into each via hole 130 using a paste press-fitting and filling device (not shown). Next, a paste is printed on the upper surface of the green sheet laminate, and the metallized layers 116 of the first external terminal electrodes 111 and 112 are formed so as to cover the upper end surfaces of the respective conductor portions on the upper surface side of the green sheet laminate. . Further, a paste is printed on the lower surface of the green sheet laminate, and the metallized layers 116 of the second external terminal electrodes 121 and 122 are formed so as to cover the lower end surfaces of the respective conductor portions on the lower surface side of the green sheet laminate.

  Thereafter, the green sheet laminate is dried to solidify the surface terminal part to some extent. Next, the green sheet laminate is degreased and fired at a predetermined temperature for a predetermined time. As a result, barium titanate and nickel in the paste are simultaneously sintered to form a ceramic sintered body 104.

  Next, electrolytic copper plating (thickness of about 10 μm) is performed on each external terminal electrode 111, 112, 121, 122 included in the obtained ceramic sintered body 104. As a result, a copper plating layer 117 is formed on each external terminal electrode 111, 112, 121, 122, and the ceramic capacitor 101 is completed. In addition, since electroless copper plating is a little thick about 10 micrometers, the thickness of copper is securable even after passing through a later roughening process.

  As shown in FIG. 6, in the masking step, a peelable adhesive tape 152 as a masking material is disposed in close contact with the opening 96 on the core first main surface 12 side of the housing hole 91, and the housing hole portion The lower surface 13 side opening 96 of 91 is closed. The adhesive tape 152 is supported by a support base 151. In addition, the thickness of the base material of the adhesive tape 152 is 55 μm, and the thickness of the adhesive surface 153 is 25 μm. Further, the adhesive surface 153 is formed of a rubber adhesive.

  In the subsequent fixing step, the ceramic capacitor 101 is accommodated in the accommodation hole 91 using a mounting device (manufactured by Yamaha Motor Co., Ltd.). At this time, the ceramic capacitor 101 is affixed and temporarily fixed to the adhesive surface 153 of the adhesive tape 152. Here, when the chip is mounted (the state shown in FIG. 1), the chip first main surface 102 that is the upper surface is in close contact with the adhesive surface 153 in a state where the upper surface and the lower surface are reversed. . Similarly, the core material 11 is also in a state where the core first main surface 12 that is the upper surface when the chip is mounted faces downward.

  In this state, a filler 95 (NAMICS Co., Ltd.) made of a thermosetting resin is used in the gap 93 between the inner surface 92 of the accommodation hole 91 and the side surface 106 of the ceramic capacitor 101 using a dispenser device (manufactured by Asymtek). (See FIG. 7). Thereafter, when heat treatment is performed, the resin filler 95 is cured to form the resin filling portion 97, and the ceramic capacitor 101 is fixed in the accommodation hole portion 91. At this time, the positions of the surfaces of the core first main surface 12, the chip first main surface 102, and the resin filling portion 97 on the side in contact with the adhesive tape 152 are aligned and formed flat.

  Then, after the ceramic capacitor 101 is fixed, a masking material removing step is performed to peel off the adhesive tape 152 (see FIG. 8).

  Thereafter, in the cleaning and polishing step, the core first main surface 12 of the core material 11 and the chip first main surface 102 of the ceramic capacitor 101 are subjected to solvent cleaning by acidic degreasing and then polished, whereby the core first main surface 12 and The adhesive material (part of the adhesive surface 153) remaining after sticking to the chip first main surface 102 is removed.

  In the subsequent roughening step, the surface of the copper plating layer on the external terminal electrodes 111, 112, 121, 122 is roughened (CZ treatment). At the same time, the surface of the conductor layer 41 formed on the core first main surface 12 and the core second main surface 13 is also roughened. And if a roughening process is complete | finished, a washing process will be implemented. Moreover, you may perform a coupling process with respect to the core 1st main surface 12 and the core 2nd main surface 13 using a silane coupling agent (made by Shin-Etsu Chemical Co., Ltd.) as needed.

  Thereafter, in the core-side insulating layer forming step, the upper surface and the lower surface of the core material 11 and the ceramic capacitor 101 (core first main surface 12 and core second main surface 13, chip first main surface 102, and chip second main surface 103). The film-like insulating resin materials mainly composed of epoxy resin are arranged so as to overlap each other. Here, an insulating resin material having a thickness of about 45 μm is disposed on the core first main surface 12 and the chip first main surface 102 side. An insulating resin material having a thickness of about 60 μm is disposed on the core second main surface 13 and the chip second main surface 103 side in consideration of the presence of irregularities.

  Then, such a laminate is pressurized and heated under vacuum with a vacuum press hot press (not shown) to cure the film-like insulating resin material and to insulate the upper surface 12, 102 and the lower surface 13, 103 with resin insulation. Layers 33 and 34 are formed (see FIG. 9). Here, since the upper surface side (the core first main surface 12 and the chip first main surface 102 side) is a flat surface, the resin insulating layer 33 having a surface flatness of 0 μm to 30 μm is formed. On the other hand, since the lower surface side (the core second main surface 13 and the chip second main surface 103 side) has a recess, the flatness of the resin insulating layer 34 is worse than that of the resin insulating layer 33. Specifically, the thickness of the ceramic capacitor 101 is thinner than the core material 11, the chip second main surface 103 is recessed from the core second main surface 13, and the surface of the resin filling portion 97 is also the core second main surface. It is recessed from the surface 13. Since the resin insulating layer 34 is formed by press-fitting the insulating resin material into the recessed portion, the flatness of the surface is lowered. In FIG. 9, the upper and lower surfaces of the core material 11 and the ceramic capacitor 101 in FIG. 8 are reversed (in a state where the chip is mounted).

  In the subsequent via formation step, a plurality of via holes 53 and a plurality of via conductors 43 are formed in the resin insulating layer 33 on the upper surface side, and the chip second main surface 103 and the resin filling portion 97 are formed in the resin insulating layer 34 on the lower surface side. A plurality of via holes 54 and a plurality of via conductors 50 are formed avoiding a region corresponding to the surface (core second main surface exposed surface) (see FIG. 10). Specifically, a plurality of via holes 53 and 54 are formed in the resin insulating layers 33 and 34 by laser processing, and then a desmear process for removing smears in the via holes 53 and 54 is performed. Thereafter, plating is performed to form filled via conductors 43 and 50 in the via holes 53 and 54. Thereafter, patterning is performed according to a conventionally known method (for example, a subtractive method) to form the core first main surface side conductor layer 242 and the core second main surface side conductor layer 342. Here, since the surface of the chip second main surface 103 and the resin filling portion 97 is recessed from the core second main surface 13, the resin insulating layer 34 maintains good flatness like the resin insulating layer 33 side. Can not. Therefore, in the present embodiment, in the resin insulating layer 34, the via hole 54 and the via conductor 50 are not formed in the region corresponding to the surface of the chip second main surface 103 and the resin filling portion 97, but only the peripheral region thereof. A via hole 54 and a via conductor 50 are formed.

  Next, a buildup layer forming step is performed. In the buildup layer forming step, the buildup layer 31 is formed on the resin insulating layer 33 and the buildup layer 32 is formed on the resin insulating layer 34 based on a conventionally known method. Specifically, a photosensitive epoxy resin is deposited on the resin insulation layers 33 and 34, and exposure and development are performed, whereby a second layer of resin insulation having a blind hole at a position where the via conductor 47 is to be formed. Layers 35 and 36 are formed. Next, electrolytic copper plating is performed according to a conventionally known method (for example, a semi-additive method) to form a via conductor 47 in the blind hole, and a terminal pad 44 is formed on the second resin insulating layer 35. Then, a BGA pad 48 is formed on the second resin insulating layer 36. Next, solder resists 37 and 38 are formed by applying and curing a photosensitive epoxy resin on the second resin insulation layers 35 and 36. Next, exposure and development are performed with a predetermined mask placed, and the openings 40 and 46 are patterned in the solder resists 37 and 38. Further, solder bumps 45 are formed on the terminal pads 44 and solder bumps 49 are formed on the BGA pads 48. As a result, the wiring board 10 is completed.

  Then, ten wiring boards 10 are manufactured by the above manufacturing method, and thickness variations of the resin insulating layer 33 (first core side insulating layer) and the resin insulating layer 34 (second core side insulating layer) are targeted for them ( μm) were measured by the method described above, and the average value was obtained. As a result, the average value of the thickness variation of the resin insulating layer 33 was 6 μm (MAX-MIN, 3 μm-15 μm), whereas the average value of the thickness variation of the resin insulating layer 34 was 55 μm (MAX-MIN, 20 μm-120 μm). Accordingly, in these wiring boards 10, the variation in the thickness of the first core-side insulating layer is considerably smaller than the thickness variation in the second core-side insulating layer.

Therefore, according to the present embodiment, the following effects can be obtained.
(1) According to the ceramic chip built-in wiring substrate 10 of the present embodiment, the resin insulating layer 33 on the upper surface side has higher flatness and less thickness variation than the resin insulating layer 34 on the lower surface side, so there is no processing variation. Uniformly shaped via holes 53 and via conductors 43 can be formed. Therefore, the first via conductor 43 is reliably connected to the connection terminal 22 of the IC chip 21 having a narrow inter-terminal pitch via the core first main surface side conductor layer 242 and the via conductor 47 of the buildup layer 31. Can do. On the other hand, since the via hole 54 and the via conductor 50 are not formed in the region corresponding to the chip second main surface 103 of the resin insulating layer 34 with low flatness, the via conductor 50 in the resin insulating layer 34 is not connected. Problems such as short circuits are prevented. From the above, it is possible to provide the ceramic chip built-in wiring board 10 having excellent connection reliability with the IC chip 21 and the mother board.

  (2) In the ceramic chip built-in wiring substrate 10 of the present embodiment, external terminal electrodes 121 and 122 which are non-connected terminals are provided on the chip second main surface 103 of the ceramic capacitor 101, and the surface thereof is further roughened. Therefore, the adhesion strength between the chip second main surface 103 and the resin insulating layer 34 is improved, and the build-up layer 32 can be prevented from being lifted or delaminated.

  (3) In this embodiment, since the cleaning and polishing step is performed after the masking material removing step, the adhesive material remaining on the core first main surface 12 and the chip first main surface 102 can be removed, and the external terminal The surface roughening process (CZ process) of the electrodes 111 and 112 can be reliably performed.

  (4) In this embodiment, in the roughening step, the surface of each conductor layer 41 is roughened simultaneously with the roughening of the surfaces of the external terminal electrodes 111, 112, 121, 122. As a result, since the area of the rough surface on the upper surface 12 and the lower surface 13 is increased, higher adhesion strength can be obtained between the resin insulating layers 33 and 34. In addition, the metallized layers of the external terminal electrodes 111, 112, 121, 122 made of hard metal are not directly roughened, but a copper plating layer 117 that is softer than that is formed to roughen the surface. Therefore, a desired rough surface can be obtained relatively easily and reliably.

  (5) In the present embodiment, since the semiconductor element mounting portion 23 of the buildup layer 31 is located in the region directly above the ceramic capacitor 101, the semiconductor element mounting portion 23 is a ceramic having high rigidity and a low coefficient of thermal expansion. Supported by the capacitor 101. Therefore, in the semiconductor element mounting portion 23, the build-up layer 31 is not easily deformed, so that the IC chip 21 mounted on the semiconductor element mounting portion 23 can be supported more stably. Therefore, as the IC chip 21, a large IC chip of 10 mm square or more, which has a large influence of thermal stress due to a large amount of heat generation, or a low-k (low dielectric constant) IC chip can be used.

(6) Since the ceramic chip built-in wiring substrate 10 of the present embodiment has the ceramic capacitor 101, good power can be supplied to the IC chip 21 by removing noise by the ceramic capacitor 101. In addition, since the IC chip 21 is mounted on the semiconductor element mounting portion 23, the IC chip 21 is disposed immediately above the ceramic capacitor 101. Thereby, the wiring (capacitor connection wiring) connecting the IC chip 21 and the ceramic capacitor 101 is shortened. Therefore, noise entering between the IC chip 21 and the ceramic capacitor 101 can be suppressed to be extremely small, and high reliability can be obtained without causing malfunctions such as malfunctions.
[Second Embodiment]

  Hereinafter, a second embodiment of the ceramic chip built-in wiring board according to the present invention will be described in detail with reference to the drawings.

  As shown in FIG. 11, in the ceramic chip built-in wiring board 10 </ b> A of this embodiment, a gap 93 between the inner surface 92 of the accommodation hole 91 and the side surface 106 of the ceramic capacitor 101 </ b> A is filled with a part of the resin insulating layer 34. This is different from the first embodiment in that the contact conductor layer 125 is provided on the chip second main surface 103 of the ceramic capacitor 101A. The contact conductor layer 125 has a square plate shape in plan view, and is formed so as to cover almost the entire chip second main surface 103. The adhesion conductor layer 125 is a conductor layer formed to ensure adhesion with the resin insulating layer 34 and is not connected to the via conductors 131 and 132 inside the ceramic sintered body 104. The shape of the contact conductor layer 125 is not limited to a square shape, and may be other polygonal shapes or circular shapes. Further, the number of the contact conductor layers 125 may be one or plural.

  Hereinafter, a method for manufacturing the ceramic chip built-in wiring substrate 10A will be described.

  In this embodiment, in the embedding ceramic chip preparation step, the ceramic capacitor 101A having the contact conductor layer 125 on the chip second main surface 103 is prepared. In the same manner as the second external terminal electrodes 121 and 122 of the first embodiment, the adhesion conductor layer 125 is obtained by printing a paste on the lower surface of the green sheet laminate and then firing the green sheet laminate. It is formed. Similarly to the first external terminal electrodes 111 and 112, the adhesion conductor layer 125 of the ceramic capacitor 101A is subjected to electroless copper plating (thickness of about 10 μm), so that the surface of the metallized layer 126 has a copper plating layer 127. Is formed (see FIG. 12). Since the surface of the copper plating layer 127 is roughened, it is rougher than the lower surface 103 of the ceramic sintered body 104. Note that the contact conductor layer 125 does not need to be formed in consideration of connection with other conductors, and may be a relatively simple solid pattern because it may be a simple solid pattern.

  The core material preparation step and the masking step are performed in the same manner as in the first embodiment. Thereafter, in the second core-side insulating layer forming step, the ceramic capacitor 101A is accommodated in the accommodation hole 91, and the ceramic capacitor 101A is temporarily fixed on the adhesive surface 153 of the adhesive tape 152 (see FIG. 6). Here, when the chip is mounted (the state shown in FIG. 11), the chip first main surface 102 that is the upper surface is in close contact with the adhesive surface 153 with the upper surface and the lower surface reversed. .

  In this state, a film-like insulating resin material mainly composed of an epoxy resin is arranged on the core second main surface 13 of the core material 11 and the chip second main surface 103 of the ceramic capacitor 101A so as to overlap each other. And pressurizing and heating under vacuum with a vacuum press hot press (not shown). Thereby, the film-like insulating resin material is cured to form the resin insulating layer 34 (second core side insulating layer), and the gap 93 between the inner surface 92 of the accommodation hole 91 and the side surface 106 of the ceramic capacitor 101A is resin-insulated. The ceramic capacitor 101A is fixed to the core material 11 by being filled with a part (resin filling part) 97 of the layer 34 (see FIG. 13). At this time, the positions of the surfaces of the core first main surface 12, the chip first main surface 102, and a part of the resin insulating layer 34 (resin filling portion) 97 on the side in contact with the adhesive tape 152 are aligned and flat (equal). Formed.

  Then, a masking material removing process for peeling the adhesive tape 152 is performed (see FIG. 14), and a cleaning and polishing process for removing the adhesive material as in the first embodiment, and the external terminal electrodes 111 and 112 and the conductor layer 41 are removed. And a roughening step for roughening the surface.

  Thereafter, in the first core-side insulating layer forming step, a film-like insulating resin material containing epoxy resin as a main component is superimposed on the core first main surface 12 of the core material 11 and the chip first main surface 102 of the ceramic capacitor 101A. Arrange like this. Then, the film-like insulating resin material is cured by pressurizing and heating under vacuum with a vacuum press and heat press machine (not shown) to form the resin insulating layer 33 (first core side insulating layer) (FIG. 15). reference).

  In the subsequent via formation step, a plurality of via holes 53 and a plurality of via conductors 43 are formed in the resin insulating layer 33, and regions corresponding to the chip second main surface 103 and the surface of the resin filling portion 97 in the resin insulating layer 34 are formed. Avoiding this, a plurality of via holes 54 and a plurality of via conductors 50 are formed.

  Thereafter, the build-up layer forming step is performed in the same manner as in the first embodiment, thereby completing the ceramic chip built-in wiring substrate 10A shown in FIG.

  According to the ceramic chip built-in wiring substrate 10A of the present embodiment manufactured as described above, the same operational effects as those of the first embodiment can be obtained. Further, in this embodiment, since the adhesion conductor layer 125 is provided, the adhesion strength between the chip second main surface 103 and the resin insulating layer 34 is improved, so that the buildup layer 32 is prevented from being lifted or delaminated. be able to. Furthermore, in the ceramic chip built-in wiring board 10A of the present embodiment, since the resin filler 95 does not have to be used as in the first embodiment, the manufacturing cost can be reduced. Furthermore, since the filling process of the resin filler 95 using a dispenser can be omitted, the manufacturing process can be simplified.

  In addition, you may change each embodiment of this invention as follows.

  In the first embodiment, the resin filler 95 is filled with the resin filler 95 in the gap 93 between the inner surface 92 of the housing hole 91 and the side surface 106 of the ceramic capacitor 101 in the core material 11 by using a dispenser device. Although formed, it is not limited to this. For example, the resin filler 95 may be formed in the gap 93 between the inner surface 92 of the accommodation hole 91 and the side surface 106 of the ceramic capacitor 101 by printing the resin filler 95 using a printing apparatus.

  In each of the above embodiments, the ceramic capacitors 101 and 101A are used as the embedded ceramic chip. However, instead of this, a ceramic chip having no capacitor function may be used.

  In each of the above embodiments, the package form of the ceramic chip built-in wiring boards 10 and 10A is BGA (ball grid array), but is not limited to BGA, for example, PGA (pin grid array) or LGA (land grid array) Etc.

  The present invention may be embodied as a ceramic chip built-in wiring board 10B according to another embodiment shown in FIG. The wiring board 10B has a structure substantially similar to that of the wiring board 10 of FIG. 11, but the structure of the ceramic capacitor 101B is only different. That is, in the second embodiment, neither of the via conductors 131 and 132 inside the ceramic sintered body 104 is connected to the contact conductor layer 125, whereas in the present embodiment, only the via conductor 131 is connected. The difference is that the via conductor 132 is not connected. The contact conductor layer 125 in the second embodiment is a so-called dummy conductor layer that is not connected to other conductors. However, the contact conductor layer 125 in this embodiment is a conductor that functions as a part of the power supply layer or the ground layer. Become a layer. According to such a structure, the adhesion between the ceramic capacitor 101B and the resin insulating layer 34 can be ensured. In addition, since both ends of the via conductor 131 are so-called “pinned”, the adhesion between the ceramic sintered body 104 and the external terminal electrode 111, the ceramic sintered body 104 and the conductor layer for adhesion 125. The wiring board 10B having improved reliability and excellent reliability can be obtained.

  Next, the technical ideas grasped by the embodiment described above are listed below.

  (1) A flat core material having a core first main surface and a core second main surface, and having a receiving hole portion opened at the core first main surface and the core second main surface; It consists of a ceramic sintered body having a main surface and a chip second main surface, an internal conductor is formed inside the ceramic sintered body, and the chip first main surface faces the same side as the core first main surface, And the ceramic chip for embedding accommodated in the said accommodation hole part in the state which orient | assigned the said chip 2nd main surface to the said core 2nd main surface, The said core 1st main surface and the said chip 1st main surface A first core-side insulating layer disposed above and having via holes and via conductors formed in a region corresponding to the first chip main surface; and on the second core main surface and the second chip main surface. The via hole and the via conductor are not formed in a region corresponding to the second main surface of the chip. The semiconductor integrated circuit has a structure in which a second core side insulating layer formed in a peripheral region of the semiconductor layer and a first core side insulating layer are formed on the first core side insulating layer, and an interlayer insulating layer and a conductor layer are alternately stacked. An element mounting side build-up layer having a plurality of connection terminals on which the element can be surface mounted, and the flatness of the second core side insulating layer is lower than the flatness of the first core side insulating layer, A ceramic chip built-in wiring board.

  (2) The ceramic chip built-in wiring according to the above 1, wherein the core first main surface and the chip first main surface are at the same level, and the flatness of the core-side insulating layer is not less than 0 μm and not more than 30 μm. substrate.

  (3) The wiring board with a built-in ceramic chip according to 1 or 2, wherein a thickness of the embedding ceramic chip is equal to or less than a thickness of the core material.

  (4) A core material that has a core first main surface and a core second main surface, and prepares a flat core material having an accommodation hole portion that opens at the core first main surface and the core second main surface. A preparatory step, a preparatory ceramic chip preparatory step for preparing a ceramic chip for embedding having a chip first main surface and a chip second main surface and having an internal conductor formed therein, and masking on the core second main surface side A masking step that closes the material, closes the opening of the accommodation hole, and after the masking step, the chip first main surface faces the same side as the core first main surface, and the chip second The ceramic chip for embedding is accommodated in the accommodation hole with the main surface facing the same side as the second main surface of the core, and the gap between the inner surface of the accommodation hole and the side surface of the ceramic chip for embedding in this state Fill with resin filler A fixing step of fixing the embedding ceramic chip to the core material; a masking material removal step of removing the masking material after the fixing step; and the core first main surface exposed through the masking material removal step, A first core side insulating layer forming step of forming a first core side insulating layer on the chip first main surface and the core first main surface exposed surface of the resin filler, the core second main surface, A second core side insulating layer forming step of forming a second core side insulating layer on the chip second main surface and the core second main surface side exposed surface of the resin filler; and While forming a plurality of via holes and a plurality of via conductors, avoid regions corresponding to the chip second main surface and the core second main surface side exposed surface of the resin filler in the second core side insulating layer. Form multiple via holes and multiple via conductors And a plurality of layers on which the semiconductor integrated circuit element can be surface-mounted on the surface layer portion on the first core-side insulating layer after the via forming step and the via forming step. And a buildup layer forming step of forming an element mounting side buildup layer having the connection terminals.

  (5) A flat core material having a core first main surface and a core second main surface, and having a receiving hole portion opened in the core first main surface and the core second main surface, and the chip first It consists of a ceramic sintered body having a main surface and a chip second main surface, an internal conductor is formed inside the ceramic sintered body, and the chip first main surface faces the same side as the core first main surface, And the ceramic chip for embedding accommodated in the said accommodation hole part in the state which orient | assigned the said chip 2nd main surface to the said core 2nd main surface, The said core 1st main surface and the said chip 1st main surface A first core-side insulating layer disposed above and having via holes and via conductors formed in a region corresponding to the first chip main surface; and on the second core main surface and the second chip main surface. The via hole and the via conductor are not formed in a region corresponding to the second main surface of the chip. The semiconductor integrated circuit has a structure in which a second core side insulating layer formed in a peripheral region of the semiconductor layer and a first core side insulating layer are formed on the first core side insulating layer, and an interlayer insulating layer and a conductor layer are alternately stacked. An element mounting side build-up layer having a plurality of connection terminals on which the element can be surface-mounted, and the thickness variation of the first core side insulating layer is smaller than the thickness variation of the second core side insulating layer A circuit board with a built-in ceramic chip.

  (6) In the above item 5, the thickness variation of the first core-side insulating layer is 10 μm or less.

  (7) a core material having a core first main surface and a core second main surface, and having an accommodation hole opening in the core first main surface and the core second main surface; a chip first main surface; A chip second main surface having an inner conductor formed therein, having a thickness different from that of the core substrate, the chip first main surface facing the same side as the core first main surface, and the chip second main surface; A ceramic chip for embedding accommodated in the accommodation hole with the surface facing the same side as the second core main surface, and disposed on the first core main surface and the first chip main surface; The chip having a step between a first core-side insulating layer in which a via hole and a via conductor are formed in a region corresponding to the chip first main surface, and the core second main surface and the core second main surface. The via hole and the via conductor are arranged in a region corresponding to the second main surface of the chip. A plurality of connections formed on the first core side insulating layer and having a structure in which an interlayer insulating layer and a conductor layer are alternately stacked, and a semiconductor element can be surface-mounted on the surface layer portion A wiring board comprising an element mounting side build-up layer having terminals.

1 is a schematic sectional view showing a wiring board according to a first embodiment embodying the present invention. 1 is a schematic cross-sectional view showing a ceramic capacitor according to a first embodiment. 1 is a schematic top view showing a ceramic capacitor according to a first embodiment. Sectional drawing of the principal part of the wiring board of 1st Embodiment. Explanatory drawing of the manufacturing method of the wiring board of 1st Embodiment. Explanatory drawing of the manufacturing method of the wiring board of 1st Embodiment. Explanatory drawing of the manufacturing method of the wiring board of 1st Embodiment. Explanatory drawing of the manufacturing method of the wiring board of 1st Embodiment. Explanatory drawing of the manufacturing method of the wiring board of 1st Embodiment. Explanatory drawing of the manufacturing method of the wiring board of 1st Embodiment. The schematic sectional drawing which shows the wiring board of 2nd Embodiment. Sectional drawing of the principal part of the wiring board of 2nd Embodiment. Explanatory drawing of the manufacturing method of the wiring board of 2nd Embodiment. Explanatory drawing of the manufacturing method of the wiring board of 2nd Embodiment. Explanatory drawing of the manufacturing method of the wiring board of 2nd Embodiment. The schematic sectional drawing which shows the wiring board of another embodiment. Explanatory drawing which shows the fixing method of the conventional ceramic chip. Explanatory drawing which shows the resin insulating layer formed in the upper surface of a ceramic chip.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 10A, 10B ... Ceramic chip built-in wiring board 11 as a wiring board ... Core material 12 ... Core 1st main surface 13 ... Core 2nd main surface 21 ... IC chip 31 as a semiconductor element ... As an element mounting side buildup layer The first core side insulating layer 34 ... the second core side insulating layer 35 ... the resin insulating layer 42 as the interlayer insulating layer ... the conductor layers 43, 50 ... the via conductors 44 ... the terminal pads 53 as connection terminals, 54 ... Via hole 91 ... Accommodating hole 92 ... Inner surface 93 of accommodating hole part ... Gap 95 ... Resin filler 96 ... Opening of accommodating hole part 97 ... Resin filling part 101, 101A, 101B ... Ceramic capacitor as embedded ceramic chip DESCRIPTION OF SYMBOLS 102 ... Chip 1st main surface 103 ... Chip 2nd main surface 106 ... Side surface 111, 112 ... of the ceramic chip for embedding ... The 1st external terminal as a connection terminal Electrodes 121, 122 ... second external terminal electrodes 125 as unconnected terminals ... contact conductor layers 131, 132 ... via conductors 141 as internal conductors ... first internal electrode layers 142 as internal conductors ... second as internal conductors 2 Internal electrode layer 152 ... Adhesive tape as masking material

Claims (6)

A core material having a core first main surface and a core second main surface, and having an accommodation hole opening in the core first main surface and the core second main surface;
A chip first main surface and a chip second main surface, and an internal conductor is formed therein; the chip first main surface is directed to the same side as the core first main surface; and the chip second main surface is A ceramic chip for embedding accommodated in the accommodation hole in a state facing the same side as the second core main surface;
A first core-side insulating layer disposed on the core first main surface and the chip first main surface and having a via hole and a via conductor formed in a region corresponding to the chip first main surface;
A second core-side insulating layer that is disposed on the core second main surface and the chip second main surface, and a via hole and a via conductor are not formed in a region corresponding to the chip second main surface;
An element mounting side build-up layer formed on the first core side insulating layer, having a structure in which interlayer insulating layers and conductor layers are alternately stacked, and having a plurality of connection terminals on which a semiconductor element can be surface mounted on a surface layer portion And the flatness of the second core side insulating layer is lower than the flatness of the first core side insulating layer. A core material having a core first main surface and a core second main surface, and having an accommodation hole opening in the core first main surface and the core second main surface;
A chip first main surface and a chip second main surface, and an internal conductor is formed therein; the chip first main surface is directed to the same side as the core first main surface; and the chip second main surface is A ceramic chip for embedding accommodated in the accommodation hole in a state facing the same side as the second core main surface;
A first core-side insulating layer disposed on the core first main surface and the chip first main surface and having a via hole and a via conductor formed in a region corresponding to the chip first main surface;
A second core-side insulating layer that is disposed on the core second main surface and the chip second main surface, and a via hole and a via conductor are not formed in a region corresponding to the chip second main surface;
An element mounting side build-up layer formed on the first core side insulating layer, having a structure in which interlayer insulating layers and conductor layers are alternately stacked, and having a plurality of connection terminals on which a semiconductor element can be surface mounted on a surface layer portion And the variation in thickness of the first core side insulating layer is smaller than the thickness variation of the second core side insulating layer.   The resin filling part which fixes the said ceramic chip for embedding to the said core material by filling the clearance gap between the inner surface of the said accommodation hole part and the side surface of the said ceramic chip for embedding | flushing is provided. Wiring board as described in.   The embedded ceramic chip is an embedded ceramic capacitor having a plurality of connection terminals connected to the inner conductor on the first chip main surface side and the second chip main surface side, and on the second chip main surface side. 4. The wiring board according to claim 1, wherein the plurality of connection terminals are non-connection terminals covered with the second core-side insulating layer. 5.   The embedded ceramic chip is a embedded ceramic capacitor having a plurality of connection terminals connected to the internal conductor on the chip first main surface side, and an adhesive conductor layer on the chip second main surface side, 4. The wiring board according to claim 1, wherein the contact conductor layer on the chip second main surface side is covered with the second core-side insulating layer. 5.   A chip first main surface, a chip second main surface, an internal conductor formed inside, a plurality of connection terminals disposed on the chip first main surface side and connected to the internal conductor; and the chip second main surface A ceramic chip for embedding comprising an adhesive conductor layer disposed on the surface side.

Images