TWI244181B - Semiconductor chip packaging structure and manufacturing method of the same - Google Patents

Semiconductor chip packaging structure and manufacturing method of the same Download PDF

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TWI244181B
TWI244181B TW090125727A TW90125727A TWI244181B TW I244181 B TWI244181 B TW I244181B TW 090125727 A TW090125727 A TW 090125727A TW 90125727 A TW90125727 A TW 90125727A TW I244181 B TWI244181 B TW I244181B
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semiconductor wafer
package structure
substrate
metal layer
patent application
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TW090125727A
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Hsueh-Te Wang
Meng-Jen Wang
Chun-Jen Tseng
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Advanced Semiconductor Eng
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Priority to TW090125727A priority Critical patent/TWI244181B/zh
Priority to US10/143,042 priority patent/US20030071347A1/en
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Publication of TWI244181B publication Critical patent/TWI244181B/zh

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    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Description

1244181
五、發明說明（1) 【發明領域】 本發明係有關於一種半 種具有散熱片之半導體晶片 導體晶片封裝構造 封裝構造。 尤關於一 【習知技術】 5技術 為訊號 ，利用 片上之 接合引 體積小 導體晶 裝構造 有效地 有多種 覆晶接 bonding)作 面翻覆朝下 使半導體晶 合技術具有 制、及封裝 由於半 小，導致封 著提高。為 裝構造係具 於傳統I C封 方式，其係 凸塊（m e t a 1 基板之接點 傳輸延遲低 ’故近年來 地集積化， 密度（heat 装構造的散 如圖1所示 performance Flip Chip Ball Grid Array)，該半導體晶 片封裝構造1主要包括一基板1 1、一半導體晶片1 2、及一 係有別 連接的 如金屬 接點與 線短’ 等優點 片南度 之熱流 提高封 型態， 裝以打線接合（wi re 將半導體晶片的接合 bumping)之導體， 電連接。由於覆晶接 、高頻雜訊易於控 係已被廣泛地應用。 且封裝構造尺寸的縮 flux densi ty )亦隨 熱速率，覆晶式的封 係HFC-BGA(High 散熱片15(heat spreader)。半導體晶片12之接合面係翻 覆朝下，且藉由錫球（solder ball)13電連接於基板11 上。此外’於基板11上女裝加勁環18(stiffener ring)， 以增加基板Π的勁度。另外，於幾何不連續處，亦即錫球 13與半導體晶片12，或錫球13與基板11的連接處，填充底 膠（underfill)14，進而免除封裝構造受力時，產生應力 集中之現象。
1244181 五、發明說明（2) '一"' - '一" ' .再者，錫球1 9係植於連接半導體晶片丨2之基板丨丨面的 相對面上，據以電連接電路板或其他之電子元件；散熱片 15係以導熱膠17黏著於半導體晶片12上，藉著散熱片15可 使半導體晶片12所產生之熱量，傳導至半導體晶片封 造1外。
圖2所示之半導體晶片封裝構造2，為圖丨所示之半導 體曰^片封裝構造1之變化態樣。當半導體晶片22尺寸足夠 大時’則可該省去圖1中之加勁環，亦即藉由此半導體晶 片22來提高基板21勁度。需說明的是，圖2中各元件之參 考符號係與圖1中之各元件之參考符號相對應。 然而，如圖1所示，散熱片丨5係以導熱膠丨7黏著於半 ‘體日日片12上’亦即採用j)LA(direct lid attach)技術來 貼附散熱片1 5，其中，散熱片！ 5與半導體晶片i 2之間的間 距稱作BLT(b〇nd line thickness) °BLT係越小越佳，因 為若BLT太大，則填充於BLT間之導熱膠17太厚，將導致導 熱性不佳的問題，亦即無法達到良好之散熱效果；但若 BLT太小’則導熱膠17太薄，容易造成散熱片15與半導體 晶片1 2間黏著強度不足之問題。
此外’導熱膠1 7必須具高黏著強度，亦導致成本之提 高0 再者，如圖2所示，散熱片25係以導熱膠27直接黏著 於半導體晶片22上，散熱片25容易產生傾斜Γ導致導熱膠 27產生孔洞（void)或脫層（deiamina*ti〇n)現象，以致於降 低半導體晶片封裝構造2之散熱效果。
第5頁 1244181 五、發明說明（3) 因此，如何改進半導體晶片封裝構造散熱片之接合， 以避免前述以導熱膠黏著散熱片於半導體晶片上之缺點， 據以達成半導體晶片封裝構造良好之散熱效果實為一重要 的課題。 【發明概要】 鑑於上述的課題，本發明之目的係在於提供一種散熱 片與半導體晶片能夠緊密接合之半導體晶片封裝構造及其 製造方法。 又，本發明之另一目的係在於提供一種不需導熱膠便 能使散熱片緊密貼附於半導體晶片之半導體晶片封裝構造 及其製造方法。 又，本發明之再一目的係在於提供一種散熱片與半導 體晶片之間的間距為零之半導體晶片封裝構造及其製造方 法。 而，本發明之特徵係藉由散熱片上鍍上一金屬層，在 特定溫度下，半導體晶片會與該金屬層產生金屬鍵結之接 合，以使兩者能緊密地接合，並使其間距為零，據以提昇 散熱片之散熱效率。 為達上述目的’本發明係提供一種半導體晶片封裝構 造，其主要包括一基板、一半導體晶片、及一散熱片。半 導體晶片係電連接於基板上，散熱片係設於該半導體晶片 上，其中，該散熱片的一面係鍍有一金屬層，其係可由金 (Au)所構成，當溫度升高到一定高溫時，該金屬層與該半
第6頁 1244181 之半導體 之金屬層 與半導體 本發明之 散熱片之 之成本。 本發明之 散熱片之 距為零， 生接合。 亦提供一種半導體晶 步驟：提 將散熱片 五、發明說明（4) 導體晶片產 本發明 其包括下列 基板上，及 熱片之金 屬層接合。 本發明 鍍於散熱片 可使散熱片 此外， 係利用鍍於 採用導熱膠 再者， 係利用鍍於 者之間的間 效果。 供一基板 之一面錢 晶片封裝構 與半導體晶 晶片緊密接 半導體晶片 金屬層與半 半導體晶片 金屬層與半 進而提昇半 片封裝構造之製造方法， 將半導體晶片電連接於該 一金屬層’並使其與該散 造及其製造方法，係利用 片間產生之金屬鍵結，故 合。 封裝構造及其製造方法， 導體晶片接合，故可省去 封裝構造及其製造方法， 導體晶片接合，故可使兩 導體晶片封裝構造之散熱 【較佳實施例之詳細說明】 以下請參考相關圖式，以說 導體晶片封裝構造。 + U罕又佳貝施例之丰 如圖3所示，本發明之半導體封裝構造3主要包括 板31、-半導體晶片32、一散熱片35、一金屬㈣ ς 體晶片32係將接合面翻覆朝下，以錫糾使半^體導 上之接點與基板31的接點電連接’其中，半導體晶曰片曰32係
η
第7頁 1244181 五、發明說明（5) $矽所構成。此外，為避免封裝構造受力時，應力集中於 歲何不連續處，即錫球33與半導體晶片32及基板31連接 處，係將底膠34或其他具有相同功效之填充體填充於半導 脰晶片32與基板3 1之間，以使受力能夠均勻分布。 、於本貫施例中，金屬層3 6係由金（A u )或鋁（A 1 )所構 成，係以濺鍍法或其他表面沉積之方法鍍於散熱片3 5上。 當溫度加熱至3 70 °C時，構成金屬層之金與構成半導體晶 片32之矽產生金-矽共晶接合（eutectic b〇nd)之現象，或 是構成金屬層之紹與構成半導體晶片32之矽產生鋁—石夕共 晶接合（eutecUc bond)之現象，使得散熱片35能盥^ 體晶片32緊密地接合。 守 此外，以錫球38或其他之具等效之凸塊置於基板31的
另-面’以使半導體封裝構造3與電路板或其他電 訊號連接。 T 在本發明之半導體封裝構造的每 屬声梦於半導辦曰Η μ u 貝細-¾樣可為將金 fίϊΐ : 屬層係與散熱片為同種金 =片為⑽n所構成，則金屬層亦為铭 所構成，s k度加熱到一定高溫時（約6 6 0。〇， 與金屬層產生融合接合，亦可達到利 、^ 片與半導體晶片產生緊密地接合⑼用金屬鍵結以使散熱 方法如圖4所示’說明本發明半導體晶片封裝構造之製造 其f步驟41中’提供一基板’該基板可為塑膠美 板或陶£基板’接著，在步驟42中，將半導體晶片電^
第8頁 1244181 五、發明說明（6) 於該基板上 體晶片之接 球與基板電 充體填充於 時產生應力 接著， 積之方法錢^ 將溫度加熱 屬層產生金-以使散熱片 地接合。 人其中该半導體晶片係採用覆晶型態，即半導 、口面翻覆朝下，且利用植於該半導體晶片的錫 連接，在步驟4 3中，將底膠或其他具等效之填 半‘體晶片與基板之間，以避免封裝構造受力 集中之問題。 在步驟44中，將金（Au)以濺鍍法或其他表面沉 於散熱片上，以形成一由金所構成之金屬層； 至3 7 0 C以上，使得構成半導體晶片之矽與金 —矽共晶接合（eutectic bond)之化學反應，據 與半導體晶片藉由共晶接合形成之金屬鍵緊密 取後，在步驟45中，將複數個錫球置於基板與該半導 =曰曰片電連接面的相對面上，以使半導體晶片之封裝構造 月匕與電路板之或其他電子元件訊號連接。 杏a ί外，本發明半導體晶片封裝構造之製造方法的另一 a鈀悲樣亦可為將金屬層如鋁鍍於半導體晶片上，以於 6^0 C之高溫下，將一由鋁所構成之散熱片置於該半導體 日日片之至屬層上’以產生融合接合（^以^⑽b〇nd) 〇 由於金屬鍵結接合的強度佳，因此利用以金—石夕共晶 接合形成之金屬鍵結，取代習知利用導電膠或其他黏.著劑 接口政熱片與半導體晶片。藉此，不但避免散熱片傾斜、 脫層、及BLT控制困難等問題，更縮短熱傳導路徑，故可 提昇散熱片之散熱效果。此外，由於省去導電膠或黏著劑 之費用，亦可使半導體封裝構造之成本降低。 θ
第9頁 1244181
第ίο頁 1244181 圖式簡單說明 【圖式之簡單說明】 圖1為一不意圖’顯不習知HFC-BGA型之半導體晶片封 裝構造。 圖2為一不意圖’顯不習知具散熱片之半導體晶片封 裝構造。 圖3為一示意圖，顯示本發明較佳實施例之半導體晶 片封裝構造。 圖4為一流程圖，顯示本發明較佳實施例半導體晶片 封裝構造之製造方法的流程。 【圖式符號說明】 1 半 導 體 晶 片 封 裝 構 造 11 基 板 12 半 導 體 晶 片 13 錫 球 14 底 膠 15 散 熱 片 17 導 敎 膠 18 加 勁 環 19 錫 球 2 半 導 體 晶 片 封 裝 構 造 21 基 板 22 半 導 體 晶 片 25 散 熱 片
第11頁 1244181 圖式簡單說明 27 導熱膠 3 半導體封裝構造 31 基板 3 2 半導體晶片 33 錫球 34 底膠 3 5 散熱片 3 6 金屬層
3 8 錫球 41 提供一基板 42 將半導體晶片電連接於基板上 43 將底膠填充於半導體晶片與基板之間 44 將散熱片之一面鍍上一金屬層，且使半導體晶片與 散熱片之金屬層共晶接合 45 將錫球置於基板的另一面
第12頁

Claims (1)

1244181 六、申請專利範圍 l 一種半導體晶片封裝構造，包含： 一基板； 一半導體晶片，係電連接於該基板上；及 一散熱片，係設於該半導體晶片上，其一面係鍍有一 金屬層，該金屬層係與該半導體晶片接合。 2. 如申請專利範圍第1項之半導體晶片封裝構造，其中該 金屬層係與該半導體晶片共晶接合。
3. 如申請專利範圍第1項之半導體晶片封裝構造，其中該 半導體晶片係以覆晶型態與該基板電連接。 4. 如申請專利範圍第1項之半導體晶片封裝構造，更包 含： 一填充體，其係填充於該基板與該半導體晶片之間。 5. 如申請專利範圍第1項之半導體晶片封裝構造，更包 含：
複數個凸塊，其係置於該基板與該半導體晶片電連接 之一面的相對面上。 6. 如申請專利範圍第1項之半導體晶片封裝構造，其中該 金屬層係由金所構成。
第13頁 1244181 六、申請專利範圍 7. 如申請專利範圍第1項之半導體晶片封裝構造，其中該 金屬層係由銘所構成。 8. —種半導體晶片封裝構造，包含： 一基板； 一半導體晶片，係電連接於該基板上，且其與基板相 接合之一面的相對面上係形成有一金屬層；及 一散熱片，係設於該半導體晶片上，其一面與該半導 體晶片之金屬層接合。 9. 如申請專利範圍第8項之半導體晶片封裝構造，其中該 散熱片係與該半導體晶片之金屬層融合接合。 1 0.如申請專利範圍第8項之半導體晶片封裝構造，其中該 半導體晶片係以覆晶型態與該基板電連接。 11.如申請專利範圍第8項之半導體晶片封裝構造，更包 含： 一填充體，其係填充於該基板與該半導體晶片之間。 1 2.如申請專利範圍第8項之半導體晶片封裝構造，更包 含： 複數個凸塊，其係置於該基板與該半導體晶片電連接 之一面的相對面上。
第14頁 1244181 六、申請專利範圍 1 3 ·如申請專利範圍第8項之半導體晶片封裝構造，其中該 金屬層係由金所構成。 1 4.如申請專利範圍第8項之半導體晶片封裝構造，其中該 金屬層係由紹所構成。 1 5. —種半導體晶片封裝構造之製造方法，包含： 提供一基板； 將一半導體晶片電連接於該基板上；及 將一散熱片之一面鍍上一金屬層，並使其與該散熱片 之金屬層接合。 1 6.如申請專利範圍第1 5項之半導體晶片封裝構造之製造 方法，其中該金屬層係與該半導體晶片共晶接合。 1 7.如申請專利範圍第1 5項之半導體晶片封裝構造之製造 方法，其中該半導體晶片係以覆晶型態與該基板電連接。 1 8.如申請專利範圍第1 5項之半導體晶片封裝構造之製造 方法，更包含： 將一填充體填充於該半導體晶片與該基板之間。 1 9.如申請專利範圍第1 5項之半導體晶片封裝構造之製造
第15頁 1244181 六、申請專利範圍 方法，更包含： 將複數個凸塊置於該基板與該半導體晶片電連接之一 面的相對面上。 2 0 ·如申請專利範圍第1 5項之半導體晶片封裝構造之製造 方法，其中該金屬層係由金所構成。
2 1.如申請專利範圍第1 5項之半導體晶片封裝構造之製造 方法，其中該金屬層係由紹所構成。 2 2.如申請專利範圍第1 5項之半導體晶片封裝構造之製造 方法，其中該金屬層係以濺鍍法所形成。 2 3.如申請專利範圍第1 5項之半導體晶片封裝構造之製造 方法，其中該金屬層係以表面沉積法所形成。 2 4. —種半導體晶片封裝構造之製造方法，包含： 提供一基板；
提供一形成有一金屬層之半導體晶片，並將該半導體 晶片電連接於該基板上，以使其金屬層位於其上方；及 將一散熱片置於該半導體晶片之金屬層上，並使其與 該金屬層接合。 2 5.如申請專利範圍第24項之半導體晶片封裝構造之製造
第16頁 1244181 六、申請專利範圍 方法，其中該散熱片係與該半導體晶片之金屬層融合接 合。 2 6.如申請專利範圍第24項之半導體晶片封裝構造之製造 方法，其中該半導體晶片係以覆晶型態與該基板電連接。 2 7.如申請專利範圍第24項之半導體晶片封裝構造之製造 方法，更包含： 將一填充體填充於該半導體晶片與該基板之間。 28.如申請專利範圍第24項之半導體晶片封裝構造之製造 方法，更包含： 將複數個凸塊置於該基板與該半導體晶片電連接之一 面的相對面上。 2 9.如申請專利範圍第24項之半導體晶片封裝構造之製造 方法，其中該金屬層係由金所構成。 3 0.如申請專利範圍第24項之半導體晶片封裝構造之製造 方法，其中該金屬層係由鋁所構成。 3 1.如申請專利範圍第24項之半導體晶片封裝構造之製造 方法，其中該金屬層係以濺鍍法所形成。
第17頁 1244181
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