TWI240362B - Method of fabricating shallow isolation structures and trenches thereof - Google Patents

Abstract

A method facilitates generally simultaneously fabricating a number of shallow trench isolation structures such that some selected ones of the shallow trench isolation structures have rounded comers and other selected ones of the shallow trench isolation structures do not have rounded comers. The method includes forming patterned photoresist over a hard mask so that portions of the hard mask are exposed over a portion of a cell region and over a portion of a periphery region, and then removing the exposed hard mask layer in the periphery region while removing a portion of the exposed hard mask layer in the cell region. A trench having rounded comers is then partially formed in the periphery region and more of the hard mask layer is removed in the cell region, before the trench in the periphery region is deepened while a trench in the cell region is formed.

Description

1240362 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a semiconductor. In particular, there is a method for manufacturing multiple shallow trench isolation structures at the same time, so that some shallow trench isolation structures have rounded corners, and other shallow trench isolation structures do not have rounded corners. [Prior art] Integrated circuits are well known. Integrated circuits are commonly used in a variety of electronic components, such as memory chips. At present, there is a strong demand for reducing the size of integrated circuit components in order to increase the density of individual components, which can improve the function of integrated circuits. For example: when it is required to reduce the size of the memory crystal volume circuit. By reducing the size of the φ small integrated circuit, each memory chip can have more capacity and thus become more practical. However, miniaturization results in a higher density of semiconductor elements, which leads to an increased possibility of unnecessary electron interference between adjacent elements. For example, as the density of semiconductor devices increases, the inter-device current increases. When an electron or hole carrier drifts between adjacent active devices on a semiconductor substrate, parasitic internal device currents are generated. When the distance between the active elements decreases, this carrier drift becomes more significant. Therefore, in the manufacture of integrated circuits, semiconductor elements must be isolated to reduce the voltage to avoid unnecessary electronic interference. · The area oxidation (LOC0S) method is widely used to isolate adjacent metal-oxide semiconductor (MOS) circuits. In the area oxidation method, unmask is inactive

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Areas (non-active) or silicon substrate field areas are exposed to heated oxidizing air, 'recessed or semi-recessed' silicon dioxide (eg, field oxide) areas are grown . Dioxide on the unmasked area; May is usually thick enough to reduce parasitie capacitance that may occur across adjacent active components on the semiconductor substrate, but not thick enough to produce step coverage coverage) issues. The base area is different from the non-active area in that the base area is made into an active area and protected by a mask to facilitate the subsequent development of active devices in the active area.

However, the area oxidation (LOC0S) method is not without its application. For example, the commonly known limitation is that when the corners of the mask are incompletely oxidized, the dioxide will gradually grow into the bottom edge of the mask and erode to the base of the active area. This is the so-called bird ’s beak effect. The bird's beak will reduce the efficiency of the component, reduce the area of the active area, increase the substrate pressure, and then fail to provide a complete insulation effect. In addition, oxides grow under the mask, and the mask layer will form non-planar oxidation defects. In a certain way, this defect is because the oxide produced during the thermal oxidation process is about twice the thickness of Shi Xi. The formed non-planar will cause problems for the consistency of subsequent layers and photolithography.

After understanding the shortcomings of the L0C0S isolation technology, the current complementary metal-oxide semiconductor (CM0S) gradually adopts shallow trenches in the active area, especially Shallow Trench Isolation (STI) structures. Shallow trench isolation structures are typically formed using an anisotropic etching process with a

9888twf.ptd Page 8 1240362 V. Description of the invention (3) The mask defines and patterns a shallow trench on a substrate. The insulation is then filled into the shallow trench, and in a subsequent step, the insulation is planarized to form a shallow trench isolation. The shallow trench isolation structure can reduce or eliminate the bird's beak (b i r d s s b e a k) problem caused by the oxidative erosion active area. Therefore, the available space is increased, and the space used for isolation is reduced. Shallow trench isolation structures include sharp-cut corners (Abrupt 1 y-Shaped), for example, because trench isolation is formed using anisotropic etching techniques. These sharp-cut geometries can cause unnecessary electrical characteristics. For example, edge conduction, where excess leakage current occurs at the top of the isolation trench structure and above the area between adjacent active components. If the active device is close to a small radius corner of the isolation trench, it will produce high-edge conductive electrical properties including unnecessary parasitic leakage paths. This unnecessary effect is the conventional active device I-V curve (U.S. Patent No. 6, 0 7 4, 9 3 1) Double hump properties. In addition, the steeply cut corners of the trench isolation structure can also cause difficulty in subsequent deposition of dielectric material in the trench. For example, the sharp-cut corners at the opening above the trench can cause pinching-off at the trench opening during the deposition of dielectric material and before the trench is completely filled, leaving excess unnecessary in the trench fill. Hole. As the trend continues toward component miniaturization and component density development, narrower deep trench isolation structures are needed more, which have larger aspect ratios. However, as the aspect ratio of trench isolation structures increases, the problem of hole formation becomes worse. For example, if an isolation trench with a large aspect ratio is formed, it is likely that during the filling of the isolation trench with silicon dioxide, the silicon dioxide will form in the trench.

9888twf.ptd Page 9 1240362 V. Description of the invention (4) The opening of the outlet becomes smaller, which prevents the silicon dioxide from completely filling the trench, and causes a void. Rounding the edges or rounding the corners of a shallow trench isolation structure can reduce some of the above-mentioned problems with sharp corners. However, in some instances, corner filleting of trench isolation structures is necessary, but in other instances, corner filleting of trench isolation structures is sometimes impossible or inappropriate. For example, the critical dimension of the memory element, that is, the width of the shallow trench isolation structure in the memory cell region is generally smaller than the critical dimension of the shallow trench isolation structure in the peripheral region. Although rounded corners of the shallow trench isolation structure in the peripheral area of the memory element can reduce the bimodal effect unique to the I-V curve, it cannot be maintained in the relatively small critical size of the shallow trench isolation structure in the memory cell area. . In this example, the rounding of the apex corners would reduce the critical dimensions of the shallow trench isolation structure in the memory cell area, and would not be acceptable. In addition, as discussed earlier, the shallow trench isolation structure with reduced width makes it more difficult to fill the shallow trench isolation structure with insulation. According to this example, it is necessary for the shallow trench isolation structure of the memory cell area to be non-rounded. However, the use of apex filleted shallow trench isolation structures in the peripheral area is still worthwhile. When forming integrated circuits, it is necessary to have some shallow trench isolation structures with rounded corners and shallow trench isolation structures with non-rounded corners. Of course, the use of different processes to form rounded corners and non-rounded corners with shallow trench isolation structures can lead to inefficiencies, cost, and impact on productivity. Therefore, there is a need for a method that can simultaneously form a rounded corner shallow trench isolation structure and a non-rounded corner shallow trench isolation structure. [Summary of the Invention]

9888twf.ptd Page 10 1240362 V. Description of the invention (5) The purpose of the present invention is to provide a method for manufacturing a shallow trench isolation structure in order to increase productivity and increase its value, and to solve the problems caused by steep corners in the trench isolation area. Difficulty of filling a trench with a dielectric substance. Another object of the present invention is to provide a method for forming a trench with a shallow trench isolation structure, which can solve the conventional problem that a shallow trench isolation structure in a memory cell area cannot reach a small size, and a non-rounded trench isolation structure is used in a peripheral area. Problems such as inefficiency, cost, and impact on productivity arise. Another object of the present invention is to provide a method for forming a trench with a shallow trench isolation structure, in order to solve the difficulty of filling the trench with a dielectric substance caused by the steep edges of the trench isolation area, and reduce the IV curve of the adjacent active device. Bimodal characteristics. φ Another object of the present invention is to provide a shallow trench isolation structure, which solves the problem that the conventional shallow trench isolation structure cannot reach a small size in the memory cell area, and solves the problem of using a non-rounded trench isolation structure in the peripheral area. Problems such as inefficiency, cost, and impact on productivity. Another object of the present invention is to provide an integrated circuit, which solves the problem that the conventional shallow trench isolation structure in the memory cell area cannot reach a small size, and solves the conventional use of a non-rounded trench isolation structure in the peripheral area, resulting in inefficiency. , Expensive and affecting yield and other issues. Another object of the present invention is to provide a shallow trench isolation structure, which solves the problem that the conventional shallow trench isolation structure cannot reach a small size in the memory cell area, and solves the problem of using a non-rounded trench isolation structure in the peripheral area to generate β. Problems such as inefficiency, cost, and impact on productivity. Another object of the present invention is to provide an integrated circuit,

9888twf.ptd Page 11 1240362 V. Description of the invention (6) The problem that the shallow trench isolation structure in the memory cell area cannot reach a small size and solve the conventional use of non-rounded trench isolation structures in the surrounding area, resulting in inefficiency, expensive and Affect issues such as yield. The invention provides a method for manufacturing a shallow trench isolation structure, comprising: providing a substrate, the substrate having a memory cell region and a peripheral region, forming a hard mask on the substrate to cover a part of the memory cell region and a part of the peripheral region; A patterned photoresist layer is formed above the hard mask. The photoresist layer exposes a part of the hard mask in the memory cell area and a part of the hard mask in the peripheral area, and performs a first name engraving process. In order to remove all hard masks exposed by the photoresist layer in the peripheral area and remove some hard masks exposed by the photoresist layer in the memory cell area, a second etching process is performed to form a majority in the peripheral area. A ditch with rounded corners, and removing more hard masks in the memory cell area, performing a third etch process to deepen the trenches formed in the peripheral area and retain some rounded corners and memory The cell area forms a trench, and the trench in the surrounding area is filled with an insulator and the trench in the memory cell area. The invention provides a method for forming a trench of a shallow trench isolation structure, which includes: during a first etching process, a hard mask in a peripheral region is etched deeper than a hard mask in a memory cell region. After that, during the second etching process, the hard mask of the memory cell area is further etched, and the base of the peripheral area is etched to form a trench with rounded corners, and then the memory cell area is etched during the third etching process. To form a trench in the memory cell region and a substrate etched in the peripheral region to deepen the trench formed in the peripheral region. The present invention further provides a method for forming a trench with a shallow trench isolation structure, including: etching a hard mask of a peripheral region during a first etching process.

9888twf.ptd Page 12 1240362 V. Description of the invention (7) The curtain to a pad of oxide layer, and the hard cover etched in the memory cell area is smaller than the pad to protect the exposed hard cover in the memory cell area. During the second etching process, the exposed hard mask to the pad oxide layer remains partially etched in the memory cell area, and the substrate in the peripheral area is etched to form a trench with rounded corners. Thereafter, during the third etching process, the substrate in the memory cell region is etched to form a trench, and the substrate in the peripheral region is etched to add the trench formed in the substrate in the peripheral region. The invention also provides a shallow trench isolation structure formed by the manufacturing process of the invention. The present invention further proposes an integrated circuit formed by the manufacturing process of the present invention. φ The present invention also proposes a shallow trench isolation structure, including a first trench formed in a peripheral region of the substrate, and the first trench having a rounded corner; and a second trench formed in a memory cell region of the substrate, And the second trench has a rounded corner. The invention further provides an integrated circuit, including: a substrate having a peripheral region and a memory cell region, a first trench formed in the peripheral region of the substrate, the first trench having a rounded apex, and a second A trench is formed in the memory cell region of the base, and the second trench has an apex angle that is not rounded. Because the present invention adopts a shallow trench isolation structure with rounded corners and non-rounded corners, the conventional shallow trench isolation structure with rounded corners and non-rounded corners is a conventional solution. The trench isolation structure H structure, the shallow trench isolation structure in the memory cell area cannot reach a small size, and the non-rounded trench isolation structure is used in the peripheral area, which is inefficient, expensive and affects

9888twf.ptd Page 13 1240362 V. Description of the invention (8) Yield and other issues, which will increase yield and increase its value. And the rounded corners in the peripheral area can solve the difficulty of filling the trench with the dielectric material and the sharp edges of the trench isolation area, and the pinch-off phenomenon of the hole filling the trench, which can reduce the I-V curve of adjacent active components. Bimodal characteristics. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below and described in detail with reference to the accompanying drawings. [Embodiment] Next, the embodiments of the present invention will be described in detail with reference materials, and the embodiments will be explained with reference to the drawings. Wherever possible, the same or similar reference numbers are used in the illustrations to describe the same or similar parts. It should be noted that the drawing is a simplified form, not an exact size. Direction names are referred to here, such as top, bottom, left, right, up, down, above, below, down, and back and front, for simplicity and clarity. These direction proper names cannot be used to limit the scope of the invention. Although the present invention has been disclosed here with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. The description of the manufacturing process of the shallow trench isolation structure does not cover all the manufacturing processes of the entire shallow trench isolation structure. The invention can be used with different integrated circuit manufacturing techniques, and only generally skilled process steps are included here to provide an understanding of the invention. The present invention is generally applicable in the field of semiconductor elements and manufacturing. But for illustrative purposes, the next

9888twf.ptd Page 14 1240362 5. The description of invention description (9) is about the manufacturing method of multiple shallow trench isolation structures, that is, there are some shallow trench isolation structures with rounded corners and some are not rounded Corner shallow trench isolation structure. The present invention provides a method for forming a shallow trench isolation structure. The method includes simultaneously forming a trench that is not a rounded corner at a memory cell region of a substrate, and a trench having a rounded corner at a peripheral region of the substrate. The invention provides a method for manufacturing a shallow trench isolation structure, which includes: providing a substrate, the substrate having a memory cell region and a peripheral region, forming a hard mask on the substrate to cover part of the memory cell region and part of the peripheral region, and A patterned photoresist layer is formed above the mask. The photoresist layer exposes a part of the hard mask in the memory cell area and a part of the hard mask in the peripheral area. A first etching process is performed to remove all the hard masks exposed by the photoresist layer in the peripheral region and to remove a part of the hard masks exposed by the photoresist layer in the memory cell region. Next, a second etching process is performed to form a trench with a plurality of rounded corners in the peripheral region, and to remove more hard masks in the memory cell region. Then, a third etching process is performed to deepen the trench formed in the peripheral region while retaining the rounded corners and to form a trench in the memory cell region. Thereafter, the trenches in the peripheral area and the trenches in the memory cell area are filled with an insulator, and they are preferably the same process steps. It is best to remove the photoresist after completing the third etching process. After filling the trench with insulation, it is best to remove the hard mask. The hard cover is formed before the substrate, preferably a layer on top of the substrate

9888twf.ptd Page 15 1240362 V. Description of the Invention (ί) The oxide layer. After the photoresist is removed, the pad oxide layer is removed. A first etching process is performed to remove all the hard masks exposed by the photoresist layer in the peripheral area and remove a part of the hard masks exposed by the photoresist layer in the memory cell area. The second etching process is performed to form a trench with a plurality of rounded apex angles in the peripheral area, and to remove more hard masks in the memory cell area. Is the top angle of the trench formed in the memory cell area better? Rounded corners. The etching gas used in the first etching process preferably includes CF4 / CH2F2 or cf4 / chf3. Thereafter, the etching gas used in the second etching process preferably includes CF4 / CHF3. The etching gas used in the third etching process preferably includes Cl 2/02. The trenches in the surrounding area and the trenches in the memory cell area are preferably filled with the same material. The trenches in the peripheral area and the trenches in the memory cell area are preferably filled with a dielectric oxide, such as silicon dioxide. Other dielectric materials are also suitable for filling trenches. The filleted apex of the trench formed in the peripheral area preferably has a radius between about 30 nm and about 60 nm, and preferably has a trench with a radius of about 60 nm. The trenches of the memory cell area are preferably formed to have approximately the same depth. However, the trenches in the peripheral area and the trenches in the memory cell area can also be selected to have different depths from each other. Please refer to Figs. 1-5, which illustrate a preferred embodiment of the present invention. A rounded top formed at the same time as an insulated shallow trench structure with non-rounded or squared corners or edges. Corner or edge insulation shallow trench structure.

9888twf.ptd Page 16 1240362 V. Description of the invention (π) Those skilled in the art will understand that although the structures 19 depict the top corners, in fact, the edges of these structures are along the upper side of the trench. So here it is called edge or corner, and the two names can be replaced. Referring to FIG. 1, a substrate 11 includes a memory cell region and a peripheral region. The material of the substrate 11 is, for example, a stone substrate, and these are generally used in the manufacture of integrated circuits such as memory elements. Alternatively, the substrate 11 can be made of other materials. A pad oxide layer 12 may be formed on the substrate 11. The pad oxide layer 12 can reduce the stress caused by the lattice structure mismatch between the substrate 11 and the hard mask 13. According to a preferred embodiment of the present invention, a hard mask 13 may be formed on the substrate 11 and the pad oxide layer 12. The material of the hard cover 1 3 is, for example, silicon nitride. The hard cover 1 3 can also be replaced with other materials. The hard mask 13 and the photoresist layer 14 provided later are used as a mask to determine which part of the substrate is to be etched or processed according to known principles, and a substance is deposited on the substrate . A patterned photoresist layer 14 may be formed on the hard mask 13. The patterned photoresist layer 14 has patterned openings 15 and openings 16 to assist in the similar patterning of the hard mask 1 3, and subsequently to facilitate etching and materials according to known principles. Deposited on. Other methods of patterning a hard mask 1 3 are equally suitable. For example, laser cutting or ion milling is used. Some openings 15 in the photoresist layer 14 can be formed on the memory cell region of the substrate to help the formation of apex corners that are not rounded. As mentioned earlier, sometimes it is necessary to form culverts that are not rounded to maintain a better relationship.

9888twf.ptd Page 17 1240362 V. Description of the invention (12) Key dimension (critical dimension). In particular, when the formed trenches are located in a dense area of semiconductor elements, the critical dimensions of the trenches must be maintained to avoid physical interference with adjacent semiconductor elements. Some of the openings 16 in the photoresist layer 14 can also be formed over the peripheral area of the substrate in order to promote the formation of rounded corner trenches. As mentioned earlier, the formation of rounded apex trenches is beneficial to reduce the unique bimodal nature of the I-V curve between adjacent semiconductor elements. Referring to FIG. 1, the opening 15 in the photoresist 14 in the memory cell area is smaller than the opening 16 in the photoresist 14 in the peripheral area. Smaller openings 15 are beneficial for shallow trench isolation structures in the memory cell area to have smaller critical dimensions, and larger openings 16 are beneficial for shallow trench isolation structures in the peripheral area to have larger critical dimensions φ inch. It is worth noting that in the embodiment of the present invention, a plurality of memory cell regions and many peripheral regions of one wafer in a chemical vapor deposition (CVD) process are very close to each other. Referring to FIG. 2, a first etching process is performed to remove a part of the hard mask 13 exposed in the memory cell area to form an etched part 17 and to remove all exposed hard parts in the peripheral area. The mask 13 forms an etched portion 18. Therefore, all the hard masks 13 in the peripheral area are preferably etched to the pad oxide layer 12. Various methods can be used to remove the material to achieve the required _.depth_ degree. For example, the hard mask 1 3 in the memory cell area can be processed thicker, otherwise it is necessary to etch the hard mask 13 in the peripheral area with more photoresist. In the # 刻 process, the micro-load (m i c r 〇-1 〇 a d i n g) effect exists

9888twf.ptd Page 18 1240362 V. Description of the invention (13) Different key dimensions. Generally, hard mask technology uses low polymer gas (for example, cf4, cf4 / o2) to reduce these effects. In the present invention, a high polymer gas (CHF3, CH2F2) may be added to selectively improve the etching microload effect. Using this technique, a large hard mask can be formed in the memory cell area, and the hard mask in the peripheral area will be completely removed. The etching gas in the first process is, for example, C F 4 / C H 2 F 2 or C F 4 / C H F 3. The ratio of CF4 and (: 1132 is preferably between 2 and 5. The ratio of CF4 and 0 ^ 3 is preferably between 3 and 5. Similarly, other ratios of etching gas can be used. After that, please refer to FIG. 3 A second etching process is performed to remove the remaining hard mask in the memory cell area and start to form a trench in the memory cell area. The trench formed in the memory cell area generally has a vertex that is not rounded or square. At the same time, the second etching process will start to form a trench in the peripheral area, and the trench in the peripheral area has rounded corners 19. In order to generate rounded corners in the peripheral area, for example, when a trench is formed, use CF4 / CHF3 gas, a heavy polymer is formed on the side wall of the trench. Using the sidewall polymer deposition method, the top fillet can be naturally formed. After the second etching process, the etched portion 17 in the memory cell area is preferably extended to the pad. The oxide layer 13 and the etched portion 18 in the peripheral area will extend to etch well into the substrate 11. The etching gas in the second etching process preferably includes: CF4 / CHF3. The CF4 to C HF3 ratio is preferably about 4 Up to 6. The same can be used Other ratios of etching gas. Please refer to FIG. 4 to perform a third etching process to form a trench 17 in the substrate 11 of the memory cell region, and to complete the formation of the trench 11 in the substrate 11 in the peripheral region.

9888twf.ptd Page 19 1240362 V. Description of the invention (14) Ditch 18. The apex of the trench 17 in the memory cell area is non-rounded or quadrangular, and the apex of the trench 18 in the peripheral area is rounded. The etching gas of the third etching process preferably includes Cl2 / 02. The ratio of Cl2 to 02 is preferably about 6 to 12. In this embodiment, the etching plasma gas contains Cl2 of 60-120 sccm and 02 of 5-12 sccm. Similarly, other etching plasma gases may be used. Please refer to FIG. 5, remove the photoresist layer 14 and deposit insulators 2 1, 2 2 such as silicon dioxide in the trenches 17 and 18 to form a shallow trench isolation structure. After the insulators 2 1, 2 2 are deposited in the trenches 17, 18, the hard mask 17 and the pad oxide layer 12 are preferably removed. The shallow trench isolation structure in the memory cell area is square corner apex or non-rounded corners in order to preserve key dimensions (for example, when a shallow trench isolation structure shows a rounded corner, there is a tendency to invade adjacent active components) . The shallow trench isolation structure in the surrounding area generally has a rounded corner angle of 19, which can reduce the double-peak characteristic of the I-V curve adjacent to the active element. Therefore, the shallow trench isolation structure that can form the memory cell area at the same time is a square apex and the shallow trench isolation structure in the surrounding area is a rounded apex to avoid adding other process steps that reduce productivity and increase costs. Reviewing the foregoing description, the present invention is a method of forming a shallow trench isolation structure with rounded corners or non-rounded corners. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

9888twf.ptd Page 20 1240362 Brief Description of Drawings Figure 1 is a cross-sectional view according to a preferred embodiment of the present invention, which shows an oxide layer formed on a memory cell region and a peripheral region of a substrate, and a hard cover. Screen, and a photoresist layer. Figure 2 is a cross-sectional view showing the removal of a part of the hard mask exposed in the memory cell region and the removal of all hard masks exposed in the peripheral region. Figure 3 shows the removal of the remaining hard mask exposed from the memory cell area and the pad oxide layer underneath, and the removal of the substrate exposed in the peripheral area. At this time, a trench with rounded corners began to form. Sectional view. Fig. 4 is a cross-sectional view showing the formation of a trench in the memory cell region of the substrate and the formation of a trench completed in the substrate of the peripheral region. Fig. 5 is a sectional view showing that the trenches in the memory cell area and the trenches in the peripheral area are filled with an insulating substance. [Icons] 11: Substrate 12: Oxidation layer 13: Hard cover 14: Photoresistive layer 15 and 16

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Claims (1)

1240362 6. Application scope \ / 1. A method for manufacturing a shallow trench isolation structure, comprising: providing a substrate having a memory cell region and a peripheral region; forming a hard mask on the substrate to cover a portion The memory cell area and a part of the peripheral area; forming a patterned photoresist layer over the hard cover, the photoresist layer exposing a part of the hard cover in the memory cell area and exposing in the peripheral area A part of the hard mask is performed; a first etching process is performed to remove all the hard masks exposed by the photoresist layer in the peripheral region and remove the exposed photoresist layer in the memory cell region Part of the hard mask; performing a second etching process to form a trench with a plurality of φ filleted apex angles in the peripheral region, and removing a third performing more in the memory cell region An etching process to deepen the trench formed in the peripheral region and retain the rounded corners and form a trench in the memory cell region; and fill the trench and the memory cell region in the peripheral region with an insulator The ditch. 2. The method for manufacturing a shallow trench isolation structure as described in item 1 of the patent application scope, further comprising removing the photoresist after the third etching process. 3. The method for manufacturing a shallow trench isolation structure as described in item 1 of the patent application scope, further comprising removing the hard mask after filling the trench with the insulator. 4. The method for manufacturing a shallow trench isolation structure as described in item 1 of the scope of the patent application, further comprising forming an oxide layer on the substrate before forming the hard mask on the substrate. 9888twf.ptd Page 22 1240362 6. Scope of patent application 5. The manufacturing method of the shallow trench isolation structure described in item 1 of the scope of patent application, further includes forming a pad oxide layer before forming the hard mask on the substrate And after filling the trench with the insulator, removing the pad oxide layer. 6. The method for manufacturing a shallow trench isolation structure according to item 1 of the scope of patent application, wherein performing the first etching process includes removing all the hard masks exposed by the photoresist layer in the peripheral area. . 7. The method for manufacturing a shallow trench isolation structure as described in item 1 of the patent application scope, wherein performing the second etching process includes removing all the hard masks exposed by the photoresist layer in the memory cell area screen. 8. The method for manufacturing a shallow trench isolation structure as described in item 1 of the patent application scope, wherein the hard mask includes a silicon nitride layer. 9. The method for manufacturing a shallow trench isolation structure as described in item 1 of the scope of patent application, wherein the apex of the trench formed in the memory cell region is not rounded. 10. The method for manufacturing a shallow trench isolation structure as described in item 1 of the scope of the patent application, wherein the etching gas in the first etching process includes one of CF4 / CH2F2 and CF4 / CHF3. 1 1. The method for manufacturing a shallow trench isolation structure as described in item 1 of the patent application scope, wherein the etching gas package CF4 / CHF3 in the second etching process. 1 2. The method for manufacturing a shallow trench isolation structure as described in item 1 of the scope of the patent application, wherein the etching gas in the third etching process includes Cl2 / 02. 1 3. The method for manufacturing a shallow trench isolation structure as described in item 1 of the scope of patent application, wherein the trench in the peripheral area and the cell in the memory cell area are filled in. 9888twf.ptd Page 23 1240362 6. Scope of patent application The trench includes the trench filled with the same material in the peripheral area and the trench in the memory cell area. 14. The method for manufacturing a shallow trench isolation structure as described in item 1 of the scope of patent application, wherein the trench filled in the peripheral region and the trench in the memory cell region are filled with an oxide during a single process step The trench in the peripheral region and the trench in the memory cell region. 1 5. The method for manufacturing a shallow trench isolation structure according to item 1 of the scope of patent application, wherein the trench filled in the peripheral area and the trench in the memory cell area include the silicon filled in the peripheral area with the silicon The ditch and the > ditch of the memory cell area. 16. The method for manufacturing a shallow trench isolation structure according to item 1 of the scope of patent application, wherein the rounded corners of the trench formed in the peripheral region have a radius between 30 nm and 60 nm. 1 7. The method for manufacturing a shallow trench isolation structure according to item 1 of the scope of the patent application, wherein the rounded corners of the trenches formed in the peripheral region have a radius of 60 nm. 1 8. The method for manufacturing a shallow trench isolation structure according to item 1 of the scope of the patent application, wherein the trench formed in the peripheral region and the trench formed in the memory cell region have the same depth. 19. A method for forming a trench in a shallow trench isolation structure, comprising: during a first etching process, etching a hard mask of a peripheral region deeper than a hard mask of a memory cell region; During the process, the hard mask of the memory cell region is further etched, and the substrate of the peripheral region is etched to partially form a circle having a plurality of circles. 9888twf.ptd Page 24 1240362 VI. Patent application scope keratinizing a ditch; and during a third etching process, etching the base of the memory cell area to form a trench in the memory cell area and etching The base in the peripheral region so as to deepen the trench formed in the peripheral region. 2 0. A shallow trench isolation structure is formed using the method described in item 19 of the scope of patent application. 2 1. A method for forming a trench with a shallow trench isolation structure, comprising: during a first etching process, etching a hard mask in a peripheral region to an oxide layer, and a hard mask remaining in a memory cell region The curtain does not have an oxide layer to retain the hard mask exposed in the memory cell area. During a second etching process, the hard mask exposed in the memory cell area is exposed. To the pad oxide layer, and etching the substrate in the peripheral region to form a trench with rounded corners; and etching the substrate in the memory cell region to form a trench during a third etching process, and The substrate in the peripheral region is etched to deepen the trench formed in the substrate in the peripheral region. 2 2. —A kind of shallow trench isolation structure is formed by using the method such as item 21 of the scope of patent application. 2 3. A kind of integrated circuit having a shallow trench isolation structure on a substrate, the shallow trench isolation structure is formed by using a method such as the application of the patent No. 21. 2 4. A shallow trench isolation structure comprising: a first trench formed in a peripheral region of a base, the first trench having a rounded corner; and 9888twf.ptd Page 25 1240362 VI. Scope of patent application A second trench is formed in a memory cell area of the substrate, and the second trench has a vertex that is not rounded. 25. A seed integrated circuit, comprising: a substrate having a peripheral region and a memory cell region; a first trench formed in the peripheral region of the substrate, the first trench having a rounded corner; and A second trench is formed in the memory cell region of the substrate, and the second trench has an apex angle that is not rounded. 9888twf.ptd Page 26