KR20040070648A - Method for manufacturing sti gap fill margin - Google Patents

Method for manufacturing sti gap fill margin Download PDF

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Publication number
KR20040070648A
KR20040070648A KR1020030006822A KR20030006822A KR20040070648A KR 20040070648 A KR20040070648 A KR 20040070648A KR 1020030006822 A KR1020030006822 A KR 1020030006822A KR 20030006822 A KR20030006822 A KR 20030006822A KR 20040070648 A KR20040070648 A KR 20040070648A
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photoresist
nitride
substrate
sti
oxide layer
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KR1020030006822A
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KR100509811B1 (en
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명정학
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아남반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE: A method for forming an STI(Shallow Trench Isolation) gap-fill margin is provided to prevent a gap-fill error due to an overhang by improving a profile of a nitride. CONSTITUTION: A pad oxide layer(12), a nitride(14), and an oxide layer are laminated on a substrate(10). A photoresist is selectively patterned on the substrate except for an STI region. The oxide layer and the nitride except for the photoresist region are removed. A round-etch process for the oxide layer is performed. The inside of the photoresist is etched selectively. A trench is formed by etching the substrate as much as the predetermined depth. The photoresist is removed therefrom. The oxide layer is removed therefrom. An STI gap-fill oxide layer(20) is formed on the entire surface of the substrate.

Description

ＳＴＩ 갭필 마진 제조 방법{METHOD FOR MANUFACTURING STI GAP FILL MARGIN}ST gap gap margin manufacturing method {METHOD FOR MANUFACTURING STI GAP FILL MARGIN}

본 발명은 STI 갭필 마진(Shallow Trench Isolation gap fill margin) 제조 방법에 관한 것으로, 특히, STI를 이루는 트렌치(trench)의 상층부를 넓혀 후속 산화막 채우기 공정의 마진을 제조하는 방법에 관한 것이다.The present invention relates to a method of manufacturing a shallow trench isolation gap fill margin, and more particularly, to a method of manufacturing a margin of a subsequent oxide filling process by widening an upper layer portion of a trench forming an STI.

반도체 소자가 점차 쉬링크(shrink)되어감에 따라 소자간 절연의 중요성이 더욱 더 대두되고 있으며, 또한 얼마나 폭을 작게하고 깊게 트렌치를 형성 할 수 있느냐 하는 것이 중요한 문제로 등장하고 있다.As semiconductor devices are gradually shrunk, the importance of inter-device isolation becomes more and more important, and how small the width and the depth of trench can be formed.

그러나, 트렌치의 폭을 작게 하면서 깊게 형성함에 따라 갭필은 더욱 어려워지게 되고, 그에 따른 갭필 불량은 후속 화학적 기계적 연마(CMP) 공정에서 평탄화에 많은 문제를 유발시킨다.However, the gap fill becomes more difficult as the trench is formed deeper with a smaller width, and thus the gap fill defect causes many problems in planarization in subsequent chemical mechanical polishing (CMP) processes.

본 발명은 상술한 결점을 해결하기 위하여 안출한 것으로, STI를 이루는 나이트라이드(nitride)의 프로파일(profile)을 개선하여 오버 행(over hang)에 의한 갭필 불량을 방지하는 STI 갭필 마진 제조 방법을 제공하는 데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-described drawbacks, and provides an STI gap fill margin manufacturing method that prevents gap fill failure due to overhang by improving a profile of nitride forming STI. Its purpose is to.

도 1a 내지 도 1h는 본 발명에 따른 STI 갭필 마진 제조 방법의 일 실시예를 공정별로 나타낸 단면도.1A to 1H are cross-sectional views illustrating one embodiment of an STI gap fill margin manufacturing method according to the present invention.

이하, 첨부된 도면을 참조하여 본 발명에 따른 실시예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1h는 본 발명에 따른 STI 갭필 마진 제조 방법의 일 실시예를 공정별로 나타낸 단면도이다.1A to 1H are cross-sectional views illustrating one embodiment of an STI gap fill margin manufacturing method according to the present invention.

먼저, 도 1a와 같이 실리콘 기판(10) 위에 패드 산화막(pad oxide)(12), 나이트라이드(14), 및 산화막(16)을 차례로 적층한다. STI 영역을 제외한 표면에 포토 레지스트(Photo Resist : PR)(18)를 선택적으로 패터닝(patterning)한다.First, as shown in FIG. 1A, a pad oxide 12, a nitride 14, and an oxide 16 are sequentially stacked on the silicon substrate 10. Photoresist (PR) 18 is selectively patterned on the surface except the STI region.

도 1b와 같이 건식 식각을 수행하여 필드(field) 역할을 수행 할 STI 영역 즉, 포토 레지스트(18) 영역 이외의 산화막(16) 전부와 나이트라이드(14)의 일정 깊이 까지를 제거한다.As shown in FIG. 1B, all of the oxide layer 16 and the nitride 14 other than the STI region, that is, the photoresist 18 region, which will serve as a field, are removed by dry etching.

도 1c와 같이 습식 식각을 수행하여 패턴에 영향을 주지 않으면서 산화막(16)만 라운드(round) 식각한다.As shown in FIG. 1C, only the oxide layer 16 is round-etched without performing a wet etching.

도 1d와 같이 개구부 영역을 확장하기 위해 포토 레지스트(18)의 내측을 일정량 제거한다. 이때, 다른 막질에 영향을 주지 않는 O2 플라즈마(plasma)를 이용한다.As shown in FIG. 1D, a predetermined amount of the inside of the photoresist 18 is removed to expand the opening region. At this time, an O2 plasma that does not affect other film quality is used.

도 1e와 같이 나이트라이드(14)를 추가로 식각하여 나이트라이드(14) 내측상면 모서리 부분이 경사 형태로 되도록 한다. 즉, 남아있는 나이트라이드(14)의 두께만큼만 식각을 하게되고, 또한 패턴 자체가 확대된 상태이며 상부의 산화막(16)이 라운드 형태로 식각되어져 있으므로 자연스럽게 경사 식각 프로파일(slope etched profile)이 만들어지게 된다.As shown in FIG. 1E, the nitride 14 is additionally etched so that the upper edge portion of the inner surface of the nitride 14 is inclined. That is, since only the thickness of the remaining nitride 14 is etched, and the pattern itself is enlarged and the oxide layer 16 is etched in a round shape, a slope etched profile is naturally created. do.

도 1f와 같이 드러난 기판(10)을 일정 깊이 제거하여 트렌치를 형성한다. 이때, Cl 플라즈마 베이스(plasma base)로 기판(10)을 식각하여 나이트라이드(14)에 대한 영향은 없다.A trench is formed by removing the substrate 10 exposed to a predetermined depth as shown in FIG. 1F. At this time, the substrate 10 is etched with a Cl plasma base so that there is no influence on the nitride 14.

도 1g와 같이 포토 레지스트(18)를 제거한다. 습식 식각하여 산화막(16)을 제거한다.The photoresist 18 is removed as shown in FIG. 1G. The wet etching is performed to remove the oxide film 16.

도 1h와 같이 STI 채우기용인 산화막(20)을 전표면에 증착한다.As shown in Fig. 1H, an oxide film 20 for STI filling is deposited on the entire surface.

한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주 내에서 당업자에 의해 여러 가지 변형이 가능하다.Meanwhile, the present invention is not limited to the above-described embodiments, but various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims below.

이상에서 설명한 바와 같이, 본 발명은 트렌치 영역의 상층부를 넓혀서 후속 산화막 채우기(oxide gap fill) 공정의 마진을 확보하여 STI 갭필이 잘 이루어지도록 한다. 따라서, 소자간의 절연이 극대화되고 후속 화학적 기계적 연마 공정에서 평탄화가 잘 이루어진다.As described above, the present invention widens the upper portion of the trench region to secure a margin of a subsequent oxide gap fill process so that the STI gap fill can be made well. Thus, insulation between devices is maximized and planarization is well achieved in subsequent chemical mechanical polishing processes.

Claims (6)

기판 위에 패드 산화막, 나이트라이드, 및 산화막을 차례로 적층하는 제 1 단계;A first step of sequentially laminating a pad oxide film, a nitride, and an oxide film on the substrate; STI 영역을 제외한 표면에 포토 레지스트를 선택적으로 패터닝하는 제 2 단계;Selectively patterning photoresist on a surface other than the STI region; 상기 포토 레지스트 영역 이외의 상기 산화막 전부와 상기 나이트라이드의 일정 깊이 까지를 제거하는 제 3 단계;A third step of removing all of the oxide film other than the photoresist area and a predetermined depth of the nitride; 상기 산화막만 라운드 식각하는 제 4 단계;A fourth step of round etching only the oxide film; 상기 포토 레지스트의 내측을 일정량 제거하는 제 5 단계;A fifth step of removing a predetermined amount of an inner side of the photoresist; 상기 나이트라이드를 추가로 식각하여 상기 나이트라이드 내측 상면 모서리 부분이 경사 형태로 되도록 하는 제 6 단계;A sixth step of further etching the nitride such that the upper inner corner portion of the nitride is inclined; 드러난 상기 기판을 일정 깊이 제거하여 트렌치를 형성하는 제 7 단계;A seventh step of forming a trench by removing the exposed substrate to a predetermined depth; 상기 포토 레지스트를 제거하는 제 8 단계;An eighth step of removing the photoresist; 상기 산화막을 제거하는 제 9 단계; 및A ninth step of removing the oxide film; And STI 채우기용인 산화막을 전표면에 형성하는 제 10 단계를 포함하는 STI 갭필 마진 제조 방법.An STI gap fill margin manufacturing method comprising a tenth step of forming an oxide film for filling an STI on an entire surface thereof. 제 1 항에 있어서, 상기 기판은 실리콘 기판인 STI 갭필 마진 제조 방법.The method of claim 1, wherein the substrate is a silicon substrate. 제 1 항에 있어서, 상기 제 3 단계의 상기 산화막 전부와 상기 나이트라이드의 일정 깊이 까지 제거는 건식 식각으로 수행되는 STI 갭필 마진 제조 방법.The method of claim 1, wherein the removal of all of the oxide layer and the nitride to a predetermined depth in the third step is performed by dry etching. 제 1 항에 있어서, 상기 제 4 단계의 상기 라운드 식각 시 습식 식각을 수행하는 STI 갭필 마진 제조 방법.The method of claim 1, wherein the wet etching is performed during the round etching of the fourth step. 제 1 항에 있어서, 상기 제 5 단계의 상기 포토 레지스트를 일정량 제거할 때 O2 플라즈마를 이용하는 STI 갭필 마진 제조 방법.The method of claim 1, wherein an O 2 plasma is used to remove a predetermined amount of the photoresist of the fifth step. 제 1 항에 있어서, 상기 제 7 단계의 상기 트렌치 형성 시 Cl 플라즈마 베이스로 상기 기판을 식각하는 STI 갭필 마진 제조 방법.The method of claim 1, wherein the substrate is etched with a Cl plasma base when the trench is formed in the seventh step.
KR10-2003-0006822A 2003-02-04 2003-02-04 Method for manufacturing sti KR100509811B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100801062B1 (en) * 2006-07-07 2008-02-04 삼성전자주식회사 Method for trench isolation, method of forming a gate structure using the method for trench isolation and method of forming a non-volatile memory device using the method for trench isolation

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100865455B1 (en) * 2007-07-31 2008-10-28 주식회사 동부하이텍 Dimple preventing method at shallow trench isolation process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100801062B1 (en) * 2006-07-07 2008-02-04 삼성전자주식회사 Method for trench isolation, method of forming a gate structure using the method for trench isolation and method of forming a non-volatile memory device using the method for trench isolation

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