KR20050026144A - Method for forming isolation layer of semiconductor device - Google Patents
Method for forming isolation layer of semiconductor device Download PDFInfo
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- KR20050026144A KR20050026144A KR1020030063109A KR20030063109A KR20050026144A KR 20050026144 A KR20050026144 A KR 20050026144A KR 1020030063109 A KR1020030063109 A KR 1020030063109A KR 20030063109 A KR20030063109 A KR 20030063109A KR 20050026144 A KR20050026144 A KR 20050026144A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000002955 isolation Methods 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims abstract description 22
- 150000004767 nitrides Chemical class 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 229920005591 polysilicon Polymers 0.000 claims abstract description 20
- 230000003647 oxidation Effects 0.000 claims abstract description 7
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000005498 polishing Methods 0.000 claims abstract description 4
- 239000000126 substance Substances 0.000 claims abstract description 4
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 239000000654 additive Substances 0.000 claims description 2
- 230000000996 additive effect Effects 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000000151 deposition Methods 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- 241000293849 Cordylanthus Species 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체소자의 소자분리막 형성방법에 관한 것으로서, 보다 상세하게는, 트렌치 상단 가장자리에서의 침식으로 인한 모트발생을 방지하기 위한 반도체소자의 소자분리막 형성방법에 관한 것이다.The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a method of forming a device isolation film of a semiconductor device for preventing the generation of mott due to erosion at the upper edge of the trench.
반도체 소자를 제조함에 있어서, 소자와 소자 사이의 전기적 분리를 위해 소자분리막을 형성하고 있으며, 이러한 소자분리막을 형성하기 위해 로코스(LOCOS) 및 STI(Shallow Trench Isolation) 공정이 이용되고 있다. In the manufacture of semiconductor devices, device isolation layers are formed for electrical separation between devices, and LOCOS and Shallow Trench Isolation (STI) processes are used to form such device isolation layers.
그런데, 로코스 공정에 의한 소자분리막은 그 상단 코너부에 새부리 형상의 버즈-빅(bird's-beak)이 발생되기 때문에 소자 형성 면적을 줄이는 단점을 가지며, 그래서, 그 이용에 한계를 갖게 되었고, 이에 따라, 현재 대부분의 반도체 소자는 작은 폭으로 형성 가능한 STI공정을 이용해서 소자분리막을 형성하고 있다. However, the device isolation film by the LOCOS process has a disadvantage of reducing the device formation area because bird's-beak of the beak shape is generated at the upper corner thereof, and thus has a limitation in its use. Therefore, at present, most semiconductor devices form an isolation layer using an STI process that can be formed in a small width.
이러한 종래의 STI공정을 이용한 반도체소자의 소자분리막 형성방법을 도 1a 및 도 1f를 참조하여 설명하도록 한다. A method of forming an isolation layer of a semiconductor device using the conventional STI process will be described with reference to FIGS. 1A and 1F.
먼저, 도 1a에 도시된 바와 같이, 반도체기판(11)상에 패드산화막(13)과 패드질화막(15)을 순차적으로 형성한다.First, as shown in FIG. 1A, the pad oxide film 13 and the pad nitride film 15 are sequentially formed on the semiconductor substrate 11.
그 다음, 도 1b에 도시된 바와 같이, 상기 패드질화막(15) 상에 감광막을 도포한 후 이를 노광및 현상해서 소자분리영역을 한정하는 감광막패턴(19)을 형성한다. 이어서, 상기 감광막패턴(19)을 마스크로 이용해서 상기 패드질화막(15)과 패드산화막(13) 및 반도체기판(11)을 식각하여 상기 반도체기판(11) 내에 소자분리용 트렌치(17)를 형성한다.Next, as shown in FIG. 1B, a photoresist film is coated on the pad nitride film 15, and then exposed and developed to form a photoresist pattern 19 defining a device isolation region. Subsequently, the pad nitride layer 15, the pad oxide layer 13, and the semiconductor substrate 11 are etched using the photoresist pattern 19 as a mask to form a device isolation trench 17 in the semiconductor substrate 11. do.
다음으로, 도 1c에 도시된 바와 같이, 감광막패턴(19)을 제거한 후, 상기 트렌치(17)와 패드질화막(15)를 포함한 전체 구조 상면에 상기 트렌치(17)를 완전히 매립할 정도의 두께로 매립산화막(21)을 증착한다.Next, as shown in FIG. 1C, after the photoresist pattern 19 is removed, the trench 17 is completely embedded in the upper surface of the entire structure including the trench 17 and the pad nitride layer 15. A buried oxide film 21 is deposited.
다음에, 도 1d에 도시된 바와 같이, 상기 매립산화막(21)과 상기 패드질화막(15)을 화학적기계연마한다.Next, as shown in FIG. 1D, the buried oxide film 21 and the pad nitride film 15 are subjected to chemical mechanical polishing.
그리고나서, 도 1e에 도시된 바와 같이, 패드질화막(15)과 패드산화막(13)을 차례로 제거하여 소자분리막(21a)을 형성한다.Then, as shown in FIG. 1E, the pad nitride film 15 and the pad oxide film 13 are sequentially removed to form the device isolation film 21a.
그러나, 상기 종래기술에 따른 반도체소자의 소자분리막 형성방법에 의하면, 도 1f에 도시된 바와 같이, 패드질화막을 제거할 때 습식식각공정을 거치면서 트렌치 상단 가장자리지역이 침식하여 가장자리 모트(Edge Moat)("A")가 발생하게 된다. 이로 인하여, 상기 트렌치 상단 가장자리구역이 침식되어 발생하는 가장자리 모트("A")는 험프(hump)현상및 INWE(Inverse Narrow Width Effect)현상을 유발하여 반도체소자와 트렌지스터의 전기적인 특성을 열화시키는 현상을 발생시킨다.However, according to the method of forming a device isolation film of a semiconductor device according to the prior art, as shown in FIG. 1F, when the pad nitride film is removed, the trench upper edge region is eroded while the wet etching process is performed. ("A") is generated. As a result, edge mott ("A") caused by erosion of the upper edge region of the trench causes a hump phenomenon and an inverse narrow width effect (INWE) phenomenon to deteriorate the electrical characteristics of the semiconductor device and the transistor. Generates.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된것으로서,Therefore, the present invention has been made to solve the above problems,
가장자리 모트 발생 및 이로 인한 소자특성저하를 방지할 수 있는 반도체소자의 소자분리막 형성방법을 제공함에그 목적이 있다.An object of the present invention is to provide a method of forming a device isolation film of a semiconductor device capable of preventing edge mottling and deterioration of device characteristics.
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 소자분리막 형성방법은, 반도체기판 상에 패드산화막, 폴리실리콘막, 버퍼산화막 및 패드질화막을 차례로 형성하는 단계; 상기 패드질화막을 소자분리영역을 한정하도록 패터닝하는 단계; 상기 패터닝된 패드질화막을 이용해서 버퍼산화막, 폴리실리콘막,패드산화막및 반도체기판을 식각하여트렌치를 형성하는 단계; 상기 트렌치를 매립하도록 기판결과물상에 매립산화막을 형성하는 단계; 상기 패드질화막이 노출되도록 매립산화막을 화학적기계연마하는 단계; 상기 패드질화막과 버퍼산화막을 제거하는 단계;A device isolation film forming method of a semiconductor device according to the present invention for achieving the above object comprises the steps of sequentially forming a pad oxide film, a polysilicon film, a buffer oxide film and a pad nitride film on a semiconductor substrate; Patterning the pad nitride layer to define an isolation region; Etching the buffer oxide film, the polysilicon film, the pad oxide film, and the semiconductor substrate by using the patterned pad nitride film to form a trench; Forming a buried oxide film on a substrate resultant to fill the trench; Chemical mechanical polishing the buried oxide film to expose the pad nitride film; Removing the pad nitride film and the buffer oxide film;
상기 기판결과물을 산화시켜 트렌치상단 가장자리의 매립산화막의 두께를 증가시키는 단계; 및 상기 기판산화에 의해 폴리실리콘막 표면에 형성된 산화막과 상기 폴리실리콘막 및 패드산화막을 제거하는 단계;를 포함하는 것을 특징으로 한다.Oxidizing the substrate resultant to increase the thickness of the buried oxide film at the top edge of the trench; And removing the oxide film and the polysilicon film and the pad oxide film formed on the surface of the polysilicon film by the substrate oxidation.
(실시예)(Example)
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
도 2a 및 도 2h는 본 발명에 따른 반도체소자의 소자분리막 형성방법을 설명하기 위한 공정단면도이다.2A and 2H are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the present invention.
도 2a에 도시된 바와 같이, 반도체기판(22) 상에 패드산화막(24)과 폴리실리콘막(26)과 버퍼산화막(28) 및 패드질화막(30)을 순차적으로 형성한다.As shown in FIG. 2A, the pad oxide film 24, the polysilicon film 26, the buffer oxide film 28, and the pad nitride film 30 are sequentially formed on the semiconductor substrate 22.
그다음, 도 2b에 도시된 바와 같이, 상기 패드질화막(30) 상에 감광막을 도포한 후, 이를 노광 및 현상해서 소자분리영역을 한정하는 감광막패턴(34)을 형성한다. 그런다음 상기 감광막패턴(34)을 마스크로 상기 패드질화막(30)과 상기 버퍼산화막(28)과 상기 폴리실리콘막(26) 및 상기 패드산화막(24)을 식각하여 소자분리영역상에 기판부분을 노출시킨다.Next, as shown in FIG. 2B, a photoresist film is coated on the pad nitride layer 30, and then exposed and developed to form a photoresist pattern 34 defining an element isolation region. Subsequently, the pad nitride layer 30, the buffer oxide layer 28, the polysilicon layer 26, and the pad oxide layer 24 are etched using the photoresist pattern 34 as a mask. Expose
이어서, 도 2c에 도시된 바와 같이, 상기 감광막 패턴(34)을 제거한 상태에서, 상기 패드질화막(30)을 하드 마스크(hard mask)로 이용하여 노출된 기판 부분을 일정깊이 만큼 식각하고, 이를 통해, 상기 반도체기판(22)내에 소자분리용 트렌치(32)를 형성한다.Subsequently, as shown in FIG. 2C, in the state where the photoresist layer pattern 34 is removed, the exposed portion of the substrate is etched to a predetermined depth by using the pad nitride layer 30 as a hard mask. An isolation trench 32 is formed in the semiconductor substrate 22.
이때, 상기 트렌치 식각은 반도체기판(22)을 Cl2를 주성분으로하는 플라즈마At this time, the trench etching is a plasma having Cl 2 as a main component of the semiconductor substrate 22.
(plasma)와 HBr 또는 HeO2등을 첨가제로 사용하여 진행한다.Proceed with (plasma) and HBr or HeO 2 as an additive.
그다음, 도 2d에 도시된 바와 같이, 상기 기판 결과물과 상기 트렌치(32)를 완전 매립할 정도의 두께로 매립산화막(36)을 증착한다. Next, as shown in FIG. 2D, the buried oxide layer 36 is deposited to a thickness sufficient to completely fill the substrate product and the trench 32.
이어서, 도 2e에 도시된 바와 같이, 상기 매립산화막(36)을 상기 패드질화막(30) 상부가 노출될 때까지 화학적기계연마한다.Subsequently, as shown in FIG. 2E, the buried oxide layer 36 is chemically mechanically polished until the upper portion of the pad nitride layer 30 is exposed.
그다음, 도 2f에 도시된 바와 같이, 상기 패드질화막(30)과 상기 버퍼산화막 (28)을 제거하여 상기 폴리실리콘막(26)을 노출시킨 상태에서 기판결과물에 대해 산화공정을 수행한다.Next, as illustrated in FIG. 2F, the pad nitride layer 30 and the buffer oxide layer 28 are removed to perform an oxidation process on the substrate resultant with the polysilicon layer 26 exposed.
이때, 도 2g에 도시된 바와 같이, 상기 폴리실리콘막(26)에 산화공정을 수행하면 상기 폴리실리콘막(26)과 상기 매립산화막(36)의 계면부위는 산화공정이 빠르게 진행되어 트렌치 상단 가장자리에 해당하는 상기 계면부위에 산화막(38)이 두텁게 형성된다.In this case, as illustrated in FIG. 2G, when the oxidation process is performed on the polysilicon layer 26, the interface between the polysilicon layer 26 and the buried oxide layer 36 is rapidly oxidized to form an upper edge of the trench. The oxide film 38 is thickly formed at the interface portion corresponding to
이어서, 도 2h에 도시된 바와 같이, 상기 산화공정으로 형성된 상기폴리실리콘막상부의 산화막(38)과 상기폴리실리콘막(26) 및 상기 패드산화막(24)을 제거하고 소자분리막(36a)을 형성한다. Subsequently, as shown in FIG. 2H, the oxide film 38, the polysilicon film 26, and the pad oxide film 24 formed on the polysilicon film formed by the oxidation process are removed to form an element isolation film 36a. .
상기와 같은 방법으로 상기 패드산화막(24) 상에 형성된 상기 폴리실리콘막(26)을 산화공정시킴으로써 상기 트렌치 상단 가장자리에 산화막층이 두텁게 형성되기때문에 이후 식각공정에서 상기 트렌치 상단 가장자리가 침식하여 발생되는 가장자리 모트현상을 제거할 수 있게 된다.Since the oxide layer is thickly formed on the upper edge of the trench by oxidizing the polysilicon layer 26 formed on the pad oxide layer 24 in the same manner as described above, the upper edge of the trench is eroded in the subsequent etching process. Edge mortise can be eliminated.
이상에서 설명한 바와 같이, 본 발명은, 반도체기판상에 패드산화막을 증착하고 상기 패드산화막상에 패드질화막을 증착하기 이전에 폴리실리콘박막과 버퍼산화막을 증착함으로써 트렌치를 형성하고 난 후에 상기 폴리실리콘막을 산화공정시키어 최종적으로 트렌치 상단 가장자리에 산화막을 두텁게 형성함으로써 이후 진행되는 식각공정에서 상기 트렌치 상단 가장자리가 침식하여 발생하는 가장자리 모트를 제거하는 효과를 얻을 수 있다.As described above, in the present invention, the polysilicon film is formed by depositing a pad oxide film on a semiconductor substrate and forming a trench by depositing a polysilicon film and a buffer oxide film before depositing a pad nitride film on the pad oxide film. By oxidizing and finally forming a thick oxide film on the top edge of the trench, the edge mottling caused by erosion of the top edge of the trench may be removed in the subsequent etching process.
따라서, 상기 모트를 제거하여 반도체소자의 험프특성과 INWE같은 전기적 열화현상을 제거함으로써 반도체소자 트랜지스터의 전기적인 특성을 향상시킬 수 있다.Therefore, the electrical characteristics of the semiconductor device transistor can be improved by removing the mote and removing the hump characteristics of the semiconductor device and electrical degradation such as INWE.
한편, 본 발명은 상술한 특정의 바람직한 실시 예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, anyone of ordinary skill in the art without departing from the gist of the invention claimed in the claims may be variously modified. will be.
도 1a 및 도 1f는 종래기술에 따른 반도체소자의 소자분리막 형성방법을 설명하기 위한 공정단면도.1A and 1F are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the prior art.
도 2a 및 도 2h는 본 발명에 따른 반도체소자의 소자분리막 형성방법을 설명하기 위한 공정단면도.2A and 2H are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
22 : 기판 24 : 패드산화막22 substrate 24 pad oxide film
26 : 폴리실리콘막 28 : 버퍼산화막26 polysilicon film 28 buffer oxide film
30 : 패드질화막 32 : 트렌치30 pad nitride film 32 trench
32a : 트렌치 34 : 감광막패턴32a: trench 34: photoresist pattern
36 : 매립산화막 36a : 소자분리막36: buried oxide film 36a: device isolation film
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