KR20050012655A - Method for forming isolation layer of semiconductor device - Google Patents
Method for forming isolation layer of semiconductor deviceInfo
- Publication number
- KR20050012655A KR20050012655A KR1020030051792A KR20030051792A KR20050012655A KR 20050012655 A KR20050012655 A KR 20050012655A KR 1020030051792 A KR1020030051792 A KR 1020030051792A KR 20030051792 A KR20030051792 A KR 20030051792A KR 20050012655 A KR20050012655 A KR 20050012655A
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- South Korea
- Prior art keywords
- film
- pad
- device isolation
- substrate
- layer
- Prior art date
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- 238000002955 isolation Methods 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 150000004767 nitrides Chemical class 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 18
- 238000004140 cleaning Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 241000293849 Cordylanthus Species 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체 소자의 소자분리막 형성방법에 관한 것으로, STI (Shallow Trench Isolation) 공정을 이용한 소자분리막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an isolation layer of a semiconductor device, and more particularly, to a method of forming an isolation layer using a shallow trench isolation (STI) process.
반도체 기술의 진보와 더불어, 반도체 소자의 고속화, 고집적화가 급속하게 진행되고 있고, 이에 수반해서 패턴의 미세화 및 패턴 칫수의 고정밀화에 대한 요구가 점점 높아지고 있다. 이러한 요구는 소자 영역에 형성되는 패턴은 물론 상대적으로 넓은 영역을 차지하는 소자분리막에도 적용된다. 이것은 소자 영역의 폭이 감소되고 있는 추세에서 상대적으로 소자 영역의 폭을 증가시키기 위해서는 소자분리 영역의 폭을 감소시켜야만 하기 때문이다.With the progress of semiconductor technology, the speed and the high integration of semiconductor devices are progressing rapidly, and with this, the demand for refinement | miniaturization of a pattern and high precision of a pattern dimension is increasing. This requirement applies not only to patterns formed in device regions, but also to device isolation films that occupy a relatively large area. This is because the width of the device isolation region must be reduced in order to increase the width of the device region relatively in the trend that the width of the device region is decreasing.
여기서, 기존의 소자분리막은 로코스(LOCOS) 공정에 의해 형성되어져 왔는데, 상기 로코스 공정에 의한 소자분리막은, 주지된 바와 같이, 그 가장자리 부분에서 새부리 형상의 버즈-빅(bird's-beak)이 발생되기 때문에 소자 분리막의 면적을 증대시키면서 누설전류를 발생시키는 단점이 있다.Here, a conventional device isolation film has been formed by a LOCOS process, and the device isolation film by the LOCOS process, as is well known, has a bird's-beak having a beak shape at its edge portion. Since it is generated, there is a disadvantage of generating a leakage current while increasing the area of the device isolation layer.
따라서, 상기 로코스 공정에 의한 소자분리막 대신에 작은 폭을 가지며 우수한 소자분리 특성을 갖는 STI 공정을 이용한 소자분리막 형성방법이 제안되었고, 현재 대부분의 반도체 소자는 STI 공정을 적용해서 소자분리막을 형성하고 있다.Therefore, a device isolation film formation method using an STI process having a small width and excellent device isolation characteristics has been proposed in place of the device isolation film by the LOCOS process. Currently, most semiconductor devices form a device isolation film by applying an STI process. have.
도 1a 내지 1d는 STI 공정을 이용한 종래의 소자분리막 형성방법을 설명하기 위한 공정 단면도로서, 이를 설명하면 다음과 같다.1A to 1D are cross-sectional views illustrating a conventional method of forming a device isolation layer using an STI process, which will be described below.
도 1a를 참조하면, 반도체 기판(11) 상에 패드산화막(12) 및 패드질화막(13)을 차례로 형성하고, 그런다음, 상기 패드질화막(13) 및패드산화막(12)을 패터닝하여 필드영역에 해당되는 기판부분을 노출시킨다. 다음으로, 상기 노출된 기판영역을 패드질화막을 식각장벽으로 이용하여 식각하여 트렌치(14)를 형성한다.Referring to FIG. 1A, a pad oxide film 12 and a pad nitride film 13 are sequentially formed on a semiconductor substrate 11, and then the pad nitride film 13 and the pad oxide film 12 are patterned to form a field region. Expose the corresponding substrate part. Next, the exposed substrate region is etched using the pad nitride layer as an etch barrier to form the trench 14.
도 1b를 참조하면, 트렌치(14)가 완전 매립되도록 결과물 상에 두껍게 HDP-산화막을 증착한다. 다음으로, 패드질화막(13)이 노출될 때까지 상기 HDP-산화막을 CMP 공정으로 연마한다. 그런다음, 트렌치 식각시에 식각 장벽으로 사용된 패드 질화막을 제거하고, 이 결과로서, 트렌치형의 소자분리막(15)을 형성한다.Referring to FIG. 1B, a thick HDP-oxide film is deposited on the resultant so that the trench 14 is completely buried. Next, the HDP-oxide film is polished by a CMP process until the pad nitride film 13 is exposed. Then, the pad nitride film used as the etch barrier during the trench etching is removed, and as a result, the trench type device isolation film 15 is formed.
소자분리막 형성 이후의 공정을 도 2를 참조하여 살펴보면, 상기 소자분리막(15)을 포함한 기판 전면을 세정하고, 기판의 액티브 영역상에 실리사이드(16)를 증착한다. 그런다음, 상기 기판 결과물 상에 층간절연막(17)을 형성한다. 다음으로, 층간절연막(17)의 일부를 식각하여 비트라인콘택홀(18)을 형성한다.Referring to FIG. 2, the process after forming the device isolation layer is performed. The entire surface of the substrate including the device isolation layer 15 is cleaned, and the silicide 16 is deposited on the active region of the substrate. Then, an interlayer insulating film 17 is formed on the substrate resultant. Next, a part of the interlayer insulating layer 17 is etched to form a bit line contact hole 18.
그러나, 전술한 바와 같은 종래의 STI 공정을 이용한 소자분리막 형성방법은 도 2에 도시된 바와 같이, CMP공정후 세정 및 식각 등에서 소자분리막 물질인 산화막의 로스(Loss)로 인해 소자분리막의 위상(Topology)이 액티브 영역의 실리사이드 보다 낮아져 정션 리키지(Junction Leakage) 현상이 일어나는 문제점이 있다.However, the method of forming a device isolation layer using the conventional STI process as described above, as shown in FIG. 2, is a phase of the device isolation layer due to the loss of the oxide film, which is a device isolation material, during cleaning and etching after the CMP process. ) Is lower than the silicide of the active region, resulting in a junction leakage phenomenon.
따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출된 것으로서, STI 공정후에 소자분리막 물질인 산화막의 로스를 방지할 수 있는 반도체 소자의 소자분리막 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a device isolation film of a semiconductor device capable of preventing the loss of an oxide film, which is a device isolation film material, after the STI process.
도 1a내지 도 1b는 종래의 기술에 따른 반도체 소자의 소자분리막 형성방법을 설명하기 위한 공정별 단면도.1A to 1B are cross-sectional views of processes for describing a method of forming a device isolation film of a semiconductor device according to the related art.
도 2는 종래의 기술의 문제점을 설명하기 위한 단면도2 is a cross-sectional view for explaining the problem of the prior art.
도 3a내지 도 3e는 본 발명의 실시예에 따른 반도체 소자의 소자분리막 형성방법을 설명하기 위한 공정별 단면도.3A to 3E are cross-sectional views of processes for describing a method of forming an isolation layer in a semiconductor device in accordance with an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
21: 실리콘 기판 22: 패드산화막21: silicon substrate 22: pad oxide film
23: 패드질화막 24: 트렌치23: pad nitride film 24: trench
25: 매립산화막 26: 소자분리막25: buried oxide film 26: device isolation film
27: 감광막 패턴 28: 질화막27: photosensitive film pattern 28: nitride film
상기와 같은 목적을 달성하기 위하여 본 발명은, 반도체 기판상에 패드산화막 및 패드질화막을 차례로 증착하는 단계; 상기 패드질화막 및 패드산화막을 패터닝하여 소자분리 영역에 해당하는 기판 부분을 노출시키는 단계; 상기 노출된 기판 필드 영역을 소정 깊이 식각하여 트렌치를 형성하는 단계; 상기 트렌치를 완전 매립하도록 기판 결과물 상에 매립 산화막을 증착하는 단계; 상기 패드질화막이 노출 되도록 상기 매립산화막을 CMP하는 단계; 상기 패드질화막을 제거하는 단계; 상기 기판상의 액티브 영역을 덮도록 감광막 패턴을 형성하는 단계; 상기 감광막으로 덮히지 않고 CMP된 매립산화막 상에 선택적으로 질화막을 형성하는 단계; 및 상기 감광막 패턴을 제거하는 단계를 포함하는 반도체 소자의 소자분리막 형성방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of depositing a pad oxide film and a pad nitride film on a semiconductor substrate in sequence; Patterning the pad nitride layer and the pad oxide layer to expose a substrate portion corresponding to an isolation region; Etching the exposed substrate field region to a predetermined depth to form a trench; Depositing a buried oxide film on a substrate resultant to completely fill the trench; CMPing the buried oxide film to expose the pad nitride film; Removing the pad nitride film; Forming a photoresist pattern so as to cover the active region on the substrate; Selectively forming a nitride film on the CMP buried oxide film without being covered with the photosensitive film; And it provides a device isolation film forming method of a semiconductor device comprising the step of removing the photosensitive film pattern.
여기서, 상기 질화막은 100~200Å이 두께로 하여 증착한다.Here, the nitride film is deposited to a thickness of 100 ~ 200Å.
본 발명에 따르면, 소자분리막 물질인 매립산화막상에 질화막을 증착함으로써, 후속의 세정 및 식각시 소자분리막이 로스되는 것을 방지 할 수 있다.According to the present invention, by depositing a nitride film on the buried oxide film which is a device isolation material, it is possible to prevent the device isolation film from being lost during subsequent cleaning and etching.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a내지 도 2f는 본 발명의 실시예에 따른 소자분리막 형성방법을 설명하기 위한 공정별 단면도이다.2A to 2F are cross-sectional views of processes for describing a method of forming a device isolation film according to an embodiment of the present invention.
도 2a를 참조하면, 실리콘 기판(21) 상에 패드산화막(22) 및 패드질화막(23)을 차례로 증착한다. 그런다음, 필드영역에 해당하는 부분을 한정하는 감광막 패턴(도시안됨)을 이용하여 패드질화막 및 패드산화막을 패터닝하여 기판을 노출 시킨다. 이어서, 상기 노출된 기판영역을 식각하여 트렌치(24)를 형성한다.Referring to FIG. 2A, a pad oxide film 22 and a pad nitride film 23 are sequentially deposited on the silicon substrate 21. Next, the pad nitride film and the pad oxide film are patterned using a photoresist pattern (not shown) defining a portion corresponding to the field region to expose the substrate. Subsequently, the exposed substrate region is etched to form a trench 24.
도 2b를 참조하면, 트렌치(24)를 완전 매립하도록 기판 결과물 상에 매립 산화막(25)을 증착한다. 그런다음, 상기 패드질화막(23)이 노출 되도록 상기 매립산화막(25)을 CMP한다.Referring to FIG. 2B, a buried oxide film 25 is deposited on the substrate output to completely fill the trench 24. Then, the buried oxide film 25 is CMP so that the pad nitride film 23 is exposed.
도 2c를 참조하면, 트렌치 식각시에 식각장벽으로 이용된 패드질화막을 제거하여, 이 결과로서, 소자분리막(26)을 형성한다.Referring to FIG. 2C, the pad nitride film used as the etch barrier during the trench etching is removed, and as a result, the device isolation layer 26 is formed.
도 2d를 참조하면, 기판상의 소자분리막(26)의 상부를 노출시키도록 감광막 패턴(27)을 형성한다. 여기서, 상기 감광막 패턴(27)은 앞선공정에서 필드영역을 한정하기 위한 감광막 패턴 형성시 사용한 레티클을 다시 사용할 수 있도록 음성감광막(Reverse Active Mask)을 사용한다.Referring to FIG. 2D, the photosensitive film pattern 27 is formed to expose the upper portion of the device isolation film 26 on the substrate. Here, the photoresist pattern 27 uses a reverse active mask so that the reticle used to form the photoresist pattern for defining the field region can be reused.
도 2e를 참조하면, 상기 감광막 패턴(27)을 이용하여 기판 필드영역의 소자분리막(26) 상에 질화막(28)을 증착하고, 그런다음, 상기 감광막 패턴을 제거한다.Referring to FIG. 2E, the nitride film 28 is deposited on the device isolation layer 26 in the substrate field region using the photoresist pattern 27, and then the photoresist pattern is removed.
여기서, 상기 질화막은 100~200Å이 두께로 하여 증착하는데, 이는 소자분리막의 위상이 필요이상으로 높아지지 않게 하기 위함이다. 또한, 상기 질화막은 후속의 세정 및 식각 공정에서 소자분리막의 로스를 방지하는 역할을 할 수 있다.Here, the nitride film is deposited to a thickness of 100 ~ 200Å, so that the phase of the device isolation film is not higher than necessary. In addition, the nitride layer may serve to prevent loss of the device isolation layer in a subsequent cleaning and etching process.
이후 도시하지는 않았지만, 소자분리막(26)을 포함한 기판 전면을 세정한다. 그런다음, 기판의 액티브 영역 상에 실리사이드막을 형성하고, 상기 소자분리막을 포함한 기판 상에 층간절연막을 증착한다. 여기서, 앞선공정에서 소자분리막 상에 질화막을 증착하였으므로, 상기 기판의 세정시 소자분리막의 로스를 방지할 수 있다.Subsequently, although not shown, the entire surface of the substrate including the device isolation layer 26 is cleaned. Then, a silicide film is formed on the active region of the substrate, and an interlayer insulating film is deposited on the substrate including the device isolation film. Here, since the nitride film is deposited on the device isolation film in the foregoing process, the loss of the device isolation film may be prevented when the substrate is cleaned.
여기까지에서, 본 발명은 필드영역의 소자분리막 상에 질화막을 선택적으로 증착함으로써, 후속의 세정 및 식각 공정에서 발생할 수 있는 매립산화막의 로스를억제하여, 소자분리막의 위상이 소자의 액티브 영역보다 낮아지지 않으므로 정션 리키지(Juntion Leakage)를 방지할 수 있다.Thus far, the present invention selectively deposits a nitride film on the device isolation film in the field region, thereby suppressing the loss of the buried oxide film that may occur in subsequent cleaning and etching processes, so that the phase of the device isolation film is lower than the active region of the device. This prevents junction leakage.
이상에서와 같이, 본 발명은 소자분리막 물질인 매립산화막 상에 질화막을 증착함으로써, 후속의 세정 및 식각시 소자분리막이 로스되는 것을 방지할 수 있고, 이에 따라, 소자분리막의 위상이 소자의 액티브 영역의 위상보다 낮아지지 않으므로, 정션 리키지를 방지할 수 있다.As described above, the present invention can prevent the device isolation film from being lost during subsequent cleaning and etching by depositing a nitride film on the buried oxide film, which is a device isolation material, and thus, the phase of the device isolation film is changed to the active region of the device. Since it is not lower than the phase of, junction leakage can be prevented.
따라서, 본 발명은 소자분리막 자체의 신뢰성을 확보할 수 있음은 물론 STI 공정의 신뢰성도 확보할 수 있고, 나아가, 소자 특성을 향상시킬 수 있다.Therefore, the present invention can secure the reliability of the device isolation film itself, as well as the reliability of the STI process, and further improve the device characteristics.
기타, 본 발명은 그 요지가 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.
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