KR20030059413A - Method of forming device isolation film of semiconductor device - Google Patents

Method of forming device isolation film of semiconductor device Download PDF

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KR20030059413A
KR20030059413A KR1020010088273A KR20010088273A KR20030059413A KR 20030059413 A KR20030059413 A KR 20030059413A KR 1020010088273 A KR1020010088273 A KR 1020010088273A KR 20010088273 A KR20010088273 A KR 20010088273A KR 20030059413 A KR20030059413 A KR 20030059413A
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South Korea
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film
forming
layer
buffer
device isolation
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KR1020010088273A
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Korean (ko)
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이용희
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주식회사 하이닉스반도체
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Priority to KR1020010088273A priority Critical patent/KR20030059413A/en
Publication of KR20030059413A publication Critical patent/KR20030059413A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE: A method for forming an isolation layer of a semiconductor device is provided to be capable of reducing pitch size of an STI(Shallow Trench Isolation) without increasing the leakage current by using a buffer HLD layer. CONSTITUTION: After sequentially forming a pad oxide pattern(250) and a pad nitride pattern(350) on a semiconductor substrate(100), a trench is formed by patterning the exposed substrate. A buffer HLD(High temperature Low pressure Deposition) layer(500) is formed on the resultant structure including the trench. Then, tilt-implantation processing is carried out. After removing the buffer HLD layer(500), a gap-fill oxide layer is formed in the trench and planarized, thereby an isolation layer is formed.

Description

반도체 소자의 소자 분리막 형성 방법{METHOD OF FORMING DEVICE ISOLATION FILM OF SEMICONDUCTOR DEVICE}Method of forming a device isolation layer of a semiconductor device {METHOD OF FORMING DEVICE ISOLATION FILM OF SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자의 소자 분리막 형성 방법에 관한 것으로, 특히 STI(shallow trench isolation)의 측벽에 누설 방지벽을 형성하여 누설 전류의 증가없이 STI의 피치 크기를 감소시키는 소자 분리막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a method of forming a device isolation film in which a leakage prevention wall is formed on a sidewall of a shallow trench isolation (STI) to reduce the pitch size of the STI without increasing leakage current.

도 1a 내지 도 1e는 종래의 소자 분리막 형성 방법을 설명하기 위한 단면도이다. 도 1a 내지 도 1e를 참조하면, 반도체 기판(10)의 상부에 버퍼 산화막(20), 질화막(30)을 순차적으로 형성한다. 소자 분리막을 형성하고자 하는 영역 상부의 질화막(30) 및 버퍼 산화막(20)을 식각하여 반도체 기판(10)을 노출시키는 질화막 패턴(35) 및 버퍼 산화막 패턴(25)을 형성한다. 다음에는 질화막 패턴(35) 및 버퍼 산화막 패턴(25)을 마스크로 하여 소자 분리막을 형성하고자 하는 영역의 반도체 기판(10)을 소정 깊이까지 식각하여 트렌치(40)를 형성한다. 그 다음에 반도체 기판(10)의 전면에 일정한 두께의 갭-필 산화막(50)을 형성한 후 질화막 패턴(35)이 노출되도록 갭-필 산화막(50)을 연마하여 소자 분리막(60)을 형성한다.1A to 1E are cross-sectional views illustrating a conventional method of forming an isolation layer. 1A to 1E, a buffer oxide film 20 and a nitride film 30 are sequentially formed on the semiconductor substrate 10. The nitride layer 30 and the buffer oxide layer 20 over the region where the device isolation layer is to be formed are etched to form the nitride layer pattern 35 and the buffer oxide layer pattern 25 exposing the semiconductor substrate 10. Next, the trench 40 is formed by etching the semiconductor substrate 10 in the region where the device isolation layer is to be formed to a predetermined depth by using the nitride layer pattern 35 and the buffer oxide layer pattern 25 as a mask. After that, a gap-fill oxide film 50 having a predetermined thickness is formed on the entire surface of the semiconductor substrate 10, and the gap-fill oxide film 50 is polished to expose the nitride film pattern 35 to form the device isolation layer 60. do.

상기 소자 분리막 형성 방법을 사용하여 소자 분리막을 형성하는 경우 고밀도 소자의 STI의 측벽 및 하부에서 누설 전류가 발생하게 되고, 이러한 누설 전류에 의해 인접한 트랜지스터의 오동작이 발생하게 되며, 특히 STI의 피치 크기가 작아지는 경우 누설 전류에 의한 오동작은 더욱 증가하게 된다는 문제점이 있었다.When the device isolation layer is formed using the device isolation layer formation method, leakage current is generated at the sidewalls and the bottom of the STI of the high density device, and the leakage current causes malfunction of adjacent transistors. In particular, the pitch size of the STI is increased. If it becomes small, there is a problem that the malfunction due to leakage current is further increased.

본 발명은 이러한 문제를 해결하기 위해 STI의 측벽에 누설 방지벽을 형성하여 누설 전류를 감소시키고, 따라서 STI의 피치 크기를 감소시켜 고밀도 소자를 제조할 수 있는 소자 분리막 형성 방법을 제공하는데 그 목적이 있다.In order to solve this problem, the present invention provides a device isolation film forming method capable of manufacturing a high-density device by reducing the leakage current by forming a leakage barrier on the sidewall of the STI, and thus reducing the pitch size of the STI. have.

도 1a 내지 도 1e는 종래의 소자 분리막 형성 방법을 설명하기 위한 단면도들.1A to 1E are cross-sectional views illustrating a conventional method of forming a device isolation layer.

도 2a 내지 도 2e는 본 발명에 따른 소자 분리막 형성 방법에 의해 제조된 반도체 소자를 도시한 단면도들.2A to 2E are cross-sectional views illustrating semiconductor devices manufactured by the device isolation film forming method according to the present invention.

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

10, 100 : 반도체 기판20, 200 : 패드 산화막10, 100: semiconductor substrate 20, 200: pad oxide film

30, 300, 350 : 패드 질화막40, 400 : 트렌치30, 300, 350: pad nitride film 40, 400: trench

500 : 버퍼 HLD막50, 600 : 갭-필 산화막500: buffer HLD film 50, 600: gap-fill oxide film

60, 700 : 소자 분리막60, 700: device separator

본 발명에 따른 반도체 소자의 소자 분리막 형성 방법은 반도체 기판 상부에 버퍼 산화막 및 실리콘 질화막을 순차적으로 형성하는 단계와, 소자 분리막을 형성하고자 하는 영역 상부의 상기 실리콘 질화막, 버퍼 산화막 전체 및 상기 소자 분리막을 형성하고자 하는 영역의 반도체 기판을 소정 깊이까지 식각하여 트렌치를 형성하는 단계와, 상기 반도체 기판의 전면에 소정 두께의 버퍼 HLD막을 형성하고 이온 주입 공정을 수행하는 단계와, 상기 버퍼 HLD막을 제거하는 단계와, 상기 반도체 기판의 전면에 상기 트렌치를 매립하는 갭-필 산화막을 형성하는 단계와, 상기 실리콘 질화막이 노출 되도록 CMP 공정을 수행하는 단계 및 상기 실리콘 질화막을 제거하는 단계를 포함하는 것을 특징으로 한다.A method of forming a device isolation layer of a semiconductor device according to the present invention includes sequentially forming a buffer oxide film and a silicon nitride film on an upper surface of a semiconductor substrate, and forming the silicon nitride film, the entire buffer oxide film, and the device isolation film on the region where the device isolation film is to be formed. Etching a semiconductor substrate in a region to be formed to a predetermined depth, forming a buffer HLD film having a predetermined thickness on the entire surface of the semiconductor substrate, performing an ion implantation process, and removing the buffer HLD film; And forming a gap-fill oxide film filling the trench on the entire surface of the semiconductor substrate, performing a CMP process to expose the silicon nitride film, and removing the silicon nitride film. .

이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

도 2a 내지 도 2e는 본 발명에 따른 소자 분리막 형성 방법에 의해 제조된 반도체 소자를 도시한 단면도이다. 도 2a 및 도 2e를 참조하면, 반도체 기판(100)의 상부에 버퍼 산화막(200), 질화막(300)을 순차적으로 형성한다(도 2a 참조). 소자 분리막을 형성하고자 하는 영역 상부의 질화막(300) 및 버퍼 산화막(200)을 식각하여 반도체 기판(100)을 노출시키는 버퍼 산화막 패턴(250) 및 질화막 패턴(350)을 형성한다(도 2b 참조). 다음에는 질화막 패턴(350) 및 버퍼 산화막 패턴(250)을 마스크로 하여 소자 분리막을 형성하고자 하는 영역의 반도체 기판(100)을 소정 깊이까지 식각하여 트렌치(400)를 형성한다(도 2c 참조).2A to 2E are cross-sectional views illustrating semiconductor devices manufactured by the device isolation film forming method according to the present invention. 2A and 2E, the buffer oxide film 200 and the nitride film 300 are sequentially formed on the semiconductor substrate 100 (see FIG. 2A). The nitride film 300 and the buffer oxide film 200 on the region where the device isolation film is to be formed are etched to form a buffer oxide film pattern 250 and a nitride film pattern 350 that expose the semiconductor substrate 100 (see FIG. 2B). . Next, the trench 400 is formed by etching the semiconductor substrate 100 in the region where the device isolation film is to be formed to a predetermined depth by using the nitride film pattern 350 and the buffer oxide film pattern 250 as a mask (see FIG. 2C).

그 다음에는, 트렌치(400)의 내부를 포함한 반도체 기판(100)의 전면에 일정 두께의 버퍼 HLD막(500)을 형성하고 경사 이온 주입 공정을 수행한다(도 2d 참조). 여기서 경사 이온 주입 공정은 질소를 이용하여 수행하는 것이 바람직하다. 그리고버퍼 HLD막(500)을 제거한다. 상기 공정에 의하여 트렌치(400) 내의 반도체 기판(100)의 표면에는 누설 방지벽이 형성된다.Next, a buffer HLD film 500 having a predetermined thickness is formed on the entire surface of the semiconductor substrate 100 including the inside of the trench 400 and a gradient ion implantation process is performed (see FIG. 2D). Here, the gradient ion implantation process is preferably performed using nitrogen. Then, the buffer HLD film 500 is removed. By the above process, a leakage preventing wall is formed on the surface of the semiconductor substrate 100 in the trench 400.

다음에는, 상기 구조물의 전면에 트렌치(400)를 매립하는 갭-필 산화막(600)을 형성(도 2e 참조)하고 실리콘 질화막(350)이 노출 되도록 갭-필 산화막(600)을 연마하는 CMP 공정을 수행한다(도 2f 참조). 그리고 실리콘 질화막(350)을 식각하면 소자 분리막(700)이 완성된다(도 2g 참조).Next, a CMP process of forming a gap-fill oxide film 600 filling the trench 400 in front of the structure (see FIG. 2E) and polishing the gap-fill oxide film 600 to expose the silicon nitride film 350. (See FIG. 2F). When the silicon nitride film 350 is etched, the device isolation film 700 is completed (see FIG. 2G).

이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자의 소자 분리막 형성 방법은 STI의 측벽에 누설 방지벽을 형성함으로써 누설 전류를 감소시키고 STI의 피치 크기를 감소시켜 고밀도 소자를 제조할 수 있는 효과가 있다.As described above, the method of forming a device isolation layer of the semiconductor device according to the present invention has the effect of reducing the leakage current and reducing the pitch size of the STI to form a high density device by forming a leakage barrier on the sidewall of the STI. .

Claims (2)

반도체 소자의 소자 분리막을 형성하는 소자 분리막 형성 방법에 있어서,In the device isolation film forming method of forming a device isolation film of a semiconductor device, 반도체 기판 상부에 버퍼 산화막 및 실리콘 질화막을 순차적으로 형성하는 단계;Sequentially forming a buffer oxide film and a silicon nitride film on the semiconductor substrate; 소자 분리막을 형성하고자 하는 영역 상부의 상기 실리콘 질화막, 버퍼 산화막 전체 및 상기 소자 분리막을 형성하고자 하는 영역의 반도체 기판을 소정 깊이까지 식각하여 트렌치를 형성하는 단계;Forming a trench by etching the silicon nitride layer, the entire buffer oxide layer, and the semiconductor substrate in the region where the device isolation layer is to be formed to a predetermined depth; 상기 반도체 기판의 전면에 소정 두께의 버퍼 HLD막을 형성하고 경사 이온 주입 공정을 수행하는 단계;Forming a buffer HLD film having a predetermined thickness on the entire surface of the semiconductor substrate and performing a gradient ion implantation process; 상기 버퍼 HLD막을 제거하는 단계;Removing the buffer HLD film; 상기 반도체 기판의 전면에 상기 트렌치를 매립하는 갭-필 산화막을 형성하는 단계;Forming a gap-fill oxide film filling the trench on an entire surface of the semiconductor substrate; 상기 실리콘 질화막이 노출 되도록 CMP 공정을 수행하는 단계; 및Performing a CMP process to expose the silicon nitride film; And 상기 실리콘 질화막을 제거하는 단계;Removing the silicon nitride film; 를 포함하는 것을 특징으로 하는 반도체 소자의 소자 분리막 형성 방법.Device isolation film forming method of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 경사 이온 주입 공정은 질소 이온 주입 공정인 것을 특징으로 하는 반도체 소자의 소자 분리막 형성 방법.And the gradient ion implantation process is a nitrogen ion implantation process.
KR1020010088273A 2001-12-29 2001-12-29 Method of forming device isolation film of semiconductor device KR20030059413A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101012046B1 (en) * 2008-12-22 2011-01-31 상도전기통신 주식회사 Instant Trip Device of Small Electrical Circuit Breaker

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101012046B1 (en) * 2008-12-22 2011-01-31 상도전기통신 주식회사 Instant Trip Device of Small Electrical Circuit Breaker

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