KR20020082024A - Trench isolation method with maintaining wafer align key - Google Patents

Trench isolation method with maintaining wafer align key Download PDF

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KR20020082024A
KR20020082024A KR1020010021755A KR20010021755A KR20020082024A KR 20020082024 A KR20020082024 A KR 20020082024A KR 1020010021755 A KR1020010021755 A KR 1020010021755A KR 20010021755 A KR20010021755 A KR 20010021755A KR 20020082024 A KR20020082024 A KR 20020082024A
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trench
depth
silicon nitride
layer
alignment key
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KR1020010021755A
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Korean (ko)
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KR100734254B1 (en
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김민철
김정석
백재철
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삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

Abstract

PURPOSE: A method for separating a semiconductor device by maintaining sensitivity of a wafer alignment key signal and using a trench is provided to prevent a lowering phenomenon of the sensitivity of the wafer alignment key signal in the semiconductor device having a shallow trench isolation layer. CONSTITUTION: A pad oxide layer and a silicon nitride layer are formed on a semiconductor substrate(10). A plurality of liners(16a) is formed along an inner wall of a trench of the first depth. A high density plasma oxide layer(18a) is deposited thereon by using a plasma CVD method. An isolation layer is formed by using the silicon nitride layer as a stop etch layer. A mask is formed on a silicon nitride layer. The trench is formed by removing the high density plasma oxide layer from a wafer alignment key forming region. The silicon nitride liner(16a) and a sacrificial oxide layer formed along an inner wall of the trench are removed by using a dry etch method. The silicon nitride layer and the semiconductor substrate(10) of a lower part of the trench are etched as much as predetermined depth by using the mask. An isolation layer of the first depth is formed in a cell region. The second trench(22a) is formed in a wafer alignment key forming region. The depth of the second trench(22a) is deeper than the depth of the first depth of the isolation layer. The mask, the silicon oxide layer, and the pad oxide layer are removed by using a wet etch method.

Description

웨이퍼 정렬키 신호 감도를 유지하면서 트렌치를 이용하여 반도체 소자를 분리하는 방법{Trench isolation method with maintaining wafer align key}Wafer Alignment Key Method to isolate semiconductor devices using trenches while maintaining signal sensitivity {Trench isolation method with maintaining wafer align key}

본 발명은 트렌치 소자 분리 방법에 관한 것으로, 특히 얕은 트렌치를 갖는 반도체 소자에 있어 감소될 수 있는 웨이퍼 정렬 키용 신호 감도를 유지시킬 수 있는 트렌치 소자 분리 방법에 관한 것이다.TECHNICAL FIELD The present invention relates to a trench element isolation method, and more particularly, to a trench element isolation method capable of maintaining signal sensitivity for a wafer alignment key that can be reduced in semiconductor devices with shallow trenches.

반도체 집적회로의 집적도가 증가함에 따라 서로 이웃하는 모스 트랜지스터들 각각을 격리시키기 위한 소자 분리 기술이 점점 중요해지고 있다. 이에 따라 종래의 소자 분리 방법인 로코스(LOCOS;LOCcal Oxidation of Silicon)공정보다 소자 분리 영역의 폭을 좁게 형성할 수 있는 트렌치 소자 분리 방법이 고집적 반도체 소자의 제조에 널리 적용되고 있다. 특히 반도체 소자의 집적화가 진행됨에 따라 소자 분리용 트렌치의 종횡비가 증가하여 얕은 트렌치를 절연물로 채울 때 소자 분리 영역 내에 보이드가 발생하게된다. 따라서, 트렌치의 깊이를 0.2㎛까지 줄이는 기술이 시도되고 있다.As the degree of integration of semiconductor integrated circuits increases, device isolation technology for isolating each of the neighboring MOS transistors becomes increasingly important. Accordingly, a trench device isolation method capable of forming a narrower device isolation region than a conventional LOCOS (LOCOS) process has been widely applied to fabrication of highly integrated semiconductor devices. In particular, as the integration of semiconductor devices proceeds, the aspect ratio of the device isolation trenches increases, and voids are generated in the device isolation regions when the shallow trenches are filled with an insulator. Therefore, a technique for reducing the depth of the trench to 0.2 mu m has been attempted.

그런데, 트렌치의 깊이가 약 0.2㎛(0.17 내지 0.23㎛)가 되면, 소자 분리막 형성 이후의 이온 주입 공정, 사진 식각 공정 등의 진행이 어렵게 된다. 구체적으로 살펴보면, 소자 분리막 형성 이후에, 소정 부분에 이온 주입 또는 사진 식각 공정을 실시하기 위해 웨이퍼는 정렬된다. 웨이퍼의 정렬은 정렬 키 신호의 인식에 의해 수행된다. 정렬키 인식은 트렌치의 깊이에 따른 감지 파장(633nm)의 신호 감지를 통해 이루어지는데, 이런 감지 파장의 신호 감도는 트렌치의 깊이에 따라 주기성을 가진다. 그러나, 017 내지 0.23㎛의 트렌치를 이용한 웨이퍼 정렬키의 신호 감도는 급격히 감소하게 되어, 결과적으로 웨이퍼의 정렬이 효과적으로 수행되지 않는다. 따라서, 트렌치 소자 분리막 형성 이후의 후속 공정이 전혀 실시되지 못하는 상황까지 발생한다.However, when the trench depth is about 0.2 μm (0.17 to 0.23 μm), it is difficult to proceed with the ion implantation process, the photolithography process, and the like after forming the isolation layer. Specifically, after forming the isolation layer, the wafers are aligned to perform an ion implantation or photolithography process on a predetermined portion. Alignment of the wafer is performed by recognition of the alignment key signal. Alignment key recognition is achieved through signal detection of the sensing wavelength (633 nm) according to the depth of the trench, and the signal sensitivity of such sensing wavelength is periodic according to the depth of the trench. However, the signal sensitivity of the wafer alignment key using trenches of 017 to 0.23 mu m is drastically reduced, and as a result, wafer alignment is not effectively performed. Therefore, a situation arises in which a subsequent process after the trench device isolation layer is not performed at all.

따라서, 본 발명이 이루고자 하는 기술적 과제는, 얕은 트렌치 소자 분리막을 갖는 반도체 소자에 있어서 웨이퍼 정렬 키용 신호 감도의 감소를 방지할 수 있는 트렌치 소자 분리 방법을 제공하는 것이다.Accordingly, an object of the present invention is to provide a trench element isolation method capable of preventing a decrease in signal sensitivity for a wafer alignment key in a semiconductor element having a shallow trench element isolation film.

도 1 내지 도 4는 본 발명에 따른 트렌치 소자 분리 방법을 나타내는 단면도들이다.1 to 4 are cross-sectional views illustrating a trench device isolation method according to the present invention.

본 발명이 이루고자 하는 기술적 과제를 달성하기 위해, 셀 영역과 웨이퍼 정렬 키 형성 영역을 포함하는 반도체 기판을 준비한다. 반도체 기판 즉 셀 영역과 웨이퍼 정렬 키 형성 영역 양쪽에 제 1 깊이를 갖으며, 절연물로 채워진 다수의 트렌치 소자 분리막들을 형성한다. 한편, 다수의 트렌치들 사이의 반도체 기판 상면에는 패드 산화막과 실리콘 질화막이 순차적으로 형성되어 있다. 다음 웨이퍼 정렬 키 형성 영역에 형성된 트렌치 소자 분리막을 노출시키는 개구부를 갖는 마스크를, 트렌치 소자 분리막 및 실리콘 질화막을 포함한 반도체 기판 상에 형성한다. 이러한 마스크의 하나로 포토레지스트를 이용할 수 있다. 웨이퍼 정렬 키 형성 영역에 제공된 트렌치 소자 분리막을 채우는 절연물질을 2단계 건식 식각을 통해 제거하여 제 1 깊이를 갖는 제 1 트렌치를 형성한다. 마스크를 이용하여, 개구부에 의해 노출된 실리콘 질화막과 제 1 트렌치 하부의 기판을 동시에 식각 하여 재 2 깊이를 갖는 제 2 트렌치를 형성한다. 그리고, 제 2 트렌치 형성 단계 이후에, 마스크, 실리콘 질화막 및 패드산화막을 제거한다. 이로써, 셀 영역에 제공된 트렌치 소자 분리막은 제 1 깊이를 가지며 정렬 키 형성 영역에 제공된 트렌치는 제 1 깊이보다 깊은 제 2 깊이를 갖게 된다.In order to achieve the technical problem to be achieved by the present invention, a semiconductor substrate including a cell region and a wafer alignment key formation region is prepared. A plurality of trench device isolation layers having a first depth and filled with an insulator are formed in both the semiconductor substrate, that is, the cell region and the wafer alignment key formation region. Meanwhile, a pad oxide film and a silicon nitride film are sequentially formed on the upper surface of the semiconductor substrate between the plurality of trenches. Next, a mask having an opening for exposing the trench element isolation film formed in the wafer alignment key formation region is formed on the semiconductor substrate including the trench element isolation film and the silicon nitride film. One of such masks can use a photoresist. The insulating material filling the trench device isolation layer provided in the wafer alignment key formation region is removed through two-step dry etching to form a first trench having a first depth. Using the mask, the silicon nitride film exposed by the opening and the substrate under the first trench are simultaneously etched to form a second trench having a second depth. After the second trench forming step, the mask, the silicon nitride film, and the pad oxide film are removed. As a result, the trench isolation layer provided in the cell region has a first depth, and the trench provided in the alignment key forming region has a second depth deeper than the first depth.

구체적인 예로, 실리콘 질화막은 500 내지 1000Å로 형성할 수 있으며, 제 2 깊이는 제 1 깊이보다 약 100 내지 1000Å 깊게 할 수 있다.As a specific example, the silicon nitride film may be formed to have a thickness of 500 to 1000 microseconds, and the second depth may be about 100 to 1000 microseconds deeper than the first depth.

본 발명에 의하면, 셀 영역의 소자들을 분리하기 위한 트렌치 소자 분리막은 얕게 하면서, 유효한 정렬키 신호감도를 확보하기 위해, 웨이퍼 정렬 키 형성용 트렌치는 보다 깊게 하였으므로, 소자 분리막 형성 이후의 이온 공정, 사진 식각 공정 등이 원활하게 진행될 수 있다.According to the present invention, in order to secure an effective alignment key signal sensitivity while reducing the trench device isolation film for separating devices in the cell region, the trench for forming the wafer alignment key is deeper, so that the ion process after forming the device isolation film, photograph Etching process can be performed smoothly.

이하 첨부된 도면을 참조로 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1에서, 반도체 기판(10) 상면에 100 내지 200Å의 패드 산화막(12)과 500 내지 1000Å의 실리콘 질화막(14)을 이용하여 증착한다. 패드 산화막(12)은 열산화를 이용하여 형성하고 실리콘 질화막(14)은 저온화학기상증착법을 이용하여 형성한다. 다음, 사진 식각 공정을 이용하여 활성 영역을 한정하는 마스크(미도시)를 사용하여 소자 분리막이 형성될 영역의 기판을 식각하여 제 1 깊이를 갖는 트렌치를 형성한다. 제 1 깊이는 약 0.2㎛ 정도이다.In FIG. 1, the upper surface of the semiconductor substrate 10 is deposited using a pad oxide film 12 of 100 to 200 mV and a silicon nitride film 14 of 500 to 1000 mV. The pad oxide film 12 is formed using thermal oxidation, and the silicon nitride film 14 is formed using low temperature chemical vapor deposition. Next, a trench having a first depth is formed by etching the substrate of the region where the device isolation layer is to be formed by using a mask (not shown) that defines an active region by using a photolithography process. The first depth is about 0.2 μm.

다음, 제 1 깊이를 갖는 트렌치 내벽을 따라 실리콘 질화물로 이루어진 라이너(16a, 16b)를 형성한다. 다음, 라이너가 형성된 반도체 기판 상에 충진 특성이 좋은 절연물 예를 들면 고밀도 플라즈마산화막을 플라즈마 화학기상증착법을 이용하여 약 5500Å로 형성한다. 그리고, 1000℃의 고온에서 약 1시간 어닐링공정을 진행한다. 이어, 실리콘 질화막(14)을 식각 저지층으로 이용하여 고밀도플라즈마 산화막을 CMP(Chemical Mechanical Polishing)하여 소자 분리막을 완성함과 동시에 기판을 평탄화한다. 미설명된 부호 18a와 18b는 트렌치 내부에 채워진 고밀도 플라즈마 산화막을 나타낸다.Next, liners 16a and 16b made of silicon nitride are formed along the trench inner walls having the first depth. Next, an insulator having good filling characteristics, for example, a high density plasma oxide film, is formed on the semiconductor substrate on which the liner is formed to about 5500 kV using plasma chemical vapor deposition. And an annealing process is performed for about 1 hour at the high temperature of 1000 degreeC. Subsequently, the silicon nitride film 14 is used as an etch stop layer to thereby form a high-density plasma oxide film by chemical mechanical polishing (CMP) to complete the device isolation film and to planarize the substrate. Reference numerals 18a and 18b, which have not been described, denote high density plasma oxide films filled in the trenches.

도 2에서, 실리콘 질화막(14) 상에 웨이퍼 정렬 키 형성 영역을 오픈시키는 개구부를 갖는 마스크(20)를 형성한다. 마스크(20)는 포토레지스트로 이루어질 수 있다. 마스크(20)를 이용하여 웨이퍼 정렬 키 형성 영역에 형성되어 있던 고밀도 플라즈마 산화막을 제거하여 트렌치(22) 를 형성한다.In FIG. 2, a mask 20 having an opening for opening a wafer alignment key formation region is formed on the silicon nitride film 14. The mask 20 may be made of photoresist. Using the mask 20, the trench 22 is formed by removing the high density plasma oxide film formed in the wafer alignment key formation region.

도 3에서, 트렌치(22)내벽을 따라 형성되어 있는 실리콘 질화물 라이너와 희생 산화막을 건식 식각으로 제거한 뒤, 마스크(20)를 이용하여 실리콘 질화막(14)과 트렌치(22) 하부의 반도체 기판을 소정 깊이 예를 들면 100 내지 1000Å 식각한다. 따라서, 셀 영역에는 제 1 깊이를 갖는 소자 분리막이 형성되어 있는 반면, 웨이퍼 정렬 키 형성 영역에는 제 1 깊이보다 약 100 내지 1000Å 깊은 제 2 트렌치(22a)가 형성된다. 미설명된 부호 14a는 제 2 트렌치(22a) 형성 시 식각되는 실리콘 질화막을 나타낸다.In FIG. 3, the silicon nitride liner formed along the inner wall of the trench 22 and the sacrificial oxide film are removed by dry etching, and then the silicon nitride film 14 and the semiconductor substrate under the trench 22 are predetermined using the mask 20. For example, etching is performed at depth of 100 to 1000 mm 3. Therefore, the device isolation film having the first depth is formed in the cell region, while the second trench 22a is formed in the wafer alignment key formation region about 100 to 1000 占 퐉 deeper than the first depth. Unexplained reference numeral 14a denotes a silicon nitride film that is etched when the second trench 22a is formed.

도 4에서, 마스크(20), 실리콘 질화막(14a) 및 패드 산화막(12)을 습식 식각으로 제거한다.In FIG. 4, the mask 20, the silicon nitride film 14a and the pad oxide film 12 are removed by wet etching.

본 발명에 의하면, 셀 영역과 웨이퍼 정렬 키 형성 영역에는 각각 다른 깊이를 갖는 트렌치가 형성될 수 있으며, 특히 셀 영역에 제공된 트렌치는 상대적으로 얕게 할 수 있고, 웨이퍼 정렬 키 형성 영역에 제공된 트렌치는 상대적으로 두껍게 할 수 있다. 따라서, 고집적화에 따라 소자 분리막내에 형성되는 보이드를 억제하면서 웨이퍼 정렬 키 신호 감도의 감소를 방지할 수 있는 효과가 있다.According to the present invention, trenches having different depths may be formed in the cell region and the wafer alignment key formation region, respectively, in particular, the trench provided in the cell region may be relatively shallow, and the trench provided in the wafer alignment key formation region may be relatively Can be thickened with. Therefore, there is an effect that the decrease in wafer alignment key signal sensitivity can be prevented while suppressing voids formed in the device isolation film due to high integration.

또한, 전술한 효과를 얻기 위해, 제 1 트렌치에서 소정 깊이 더 식각하는 공정만을 추가하여 보다 깊은 제 2 트렌치를 형성하므로, 종래의 소자 분리 공정에 적용하기 용이하다.In addition, in order to obtain the above-described effect, since the second trench is formed by adding only the process of further etching a predetermined depth in the first trench, it is easy to apply to a conventional device isolation process.

Claims (5)

셀 영역과 웨이퍼 정렬 키 형성 영역을 포함하는 반도체 기판을 제공하는 단계,Providing a semiconductor substrate comprising a cell region and a wafer alignment key forming region, 상기 반도체 기판에 제 1 깊이를 갖으며, 절연물로 채워진 다수의 트렌치 소자 분리막들을 형성하는 단계,Forming a plurality of trench device isolation layers having a first depth and filled with an insulator in the semiconductor substrate, 상기 다수의 트렌치들 사이의 반도체 기판 상면에 패드 산화막과 실리콘 질화막을 순차적으로 형성하는 단계,Sequentially forming a pad oxide film and a silicon nitride film on an upper surface of the semiconductor substrate between the plurality of trenches, 상기 웨이퍼 정렬 키 형성 영역에 형성된 트렌치 소자 분리막을 노출시키는 개구부를 갖는 마스크를, 상기 트렌치 소자 분리막 및 상기 실리콘 질화막을 포함한 반도체 기판 상에 형성하는 단계,Forming a mask having an opening for exposing the trench isolation layer formed in the wafer alignment key formation region, on a semiconductor substrate including the trench isolation layer and the silicon nitride film; 상기 웨이퍼 정렬 키 형성 영역에 제공된 트렌치 소자 분리막을 채우는 절연물질을 제거하여 제 1 깊이를 갖는 제 1 트렌치를 형성하는 단계, 및Removing the insulating material filling the trench device isolation layer provided in the wafer alignment key formation region to form a first trench having a first depth, and 상기 마스크를 이용하여, 상기 개구부에 의해 노출된 실리콘 질화막과 상기 제 1 트렌치 하부의 기판을 동시에 식각하여 재 2 깊이를 갖는 제 2 트렌치를 형성하는 단계를 포함하는 반도체 소자 분리 방법.And etching the silicon nitride film exposed by the opening and the substrate under the first trench simultaneously using the mask to form a second trench having a second depth. 제 1 항에 있어서, 상기 제 2 트렌치 형성 단계 이후에, 상기 마스크, 상기 실리콘 질화막 및 상기 패드산화막을 제거하는 단계를 더 포함하는 반도체 소자 분리 방법.The method of claim 1, further comprising removing the mask, the silicon nitride layer, and the pad oxide layer after forming the second trench. 제 1 항에 있어서, 상기 실리콘 질화막은 500 내지 1000Å인 반도체 소자 분리 방법.The method of claim 1, wherein the silicon nitride film is 500 to 1000 microns. 제 1 항에 있어서, 상기 제 2 깊이는 상기 제 1 깊이보다 약 100 내지 1000Å 깊은 반도체 소자 분리 방법.The method of claim 1, wherein the second depth is about 100 to 1000 microns deeper than the first depth. 제 1 항에 있어서, 상기 마스크는 포토레지스트인 반도체 소자 분리 방법.The method of claim 1, wherein the mask is a photoresist.
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KR20040001454A (en) * 2002-06-28 2004-01-07 주식회사 하이닉스반도체 Method for fabricating alignment key for dual damascene
KR100620430B1 (en) * 2005-04-29 2006-09-06 삼성전자주식회사 Alignment key structure of a semiconductor device and method of forming the same

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KR19990015595A (en) * 1997-08-07 1999-03-05 윤종용 Method of manufacturing semiconductor memory device having trench isolation region and semiconductor memory device manufactured thereby
KR100476372B1 (en) * 1997-12-30 2005-07-07 주식회사 하이닉스반도체 Trench type isolation layer formation method for semiconductor devices with different trench widths

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040001454A (en) * 2002-06-28 2004-01-07 주식회사 하이닉스반도체 Method for fabricating alignment key for dual damascene
KR100620430B1 (en) * 2005-04-29 2006-09-06 삼성전자주식회사 Alignment key structure of a semiconductor device and method of forming the same

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