TWI239089B - Manufacturing process of semiconductor device - Google Patents

Manufacturing process of semiconductor device Download PDF

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Publication number
TWI239089B
TWI239089B TW090106044A TW90106044A TWI239089B TW I239089 B TWI239089 B TW I239089B TW 090106044 A TW090106044 A TW 090106044A TW 90106044 A TW90106044 A TW 90106044A TW I239089 B TWI239089 B TW I239089B
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TW
Taiwan
Prior art keywords
electrode
frame
semiconductor device
upper frame
manufacturing
Prior art date
Application number
TW090106044A
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English (en)
Inventor
Hirokazu Fukuda
Original Assignee
Sanyo Electric Co
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Publication date
Application filed by Sanyo Electric Co filed Critical Sanyo Electric Co
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Publication of TWI239089B publication Critical patent/TWI239089B/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49562Geometry of the lead-frame for devices being provided for in H01L29/00
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    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
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    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Connection Of Batteries Or Terminals (AREA)

Description

1239089 A7 B7 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 五、發明說明(1 ) [、發明所屬技術領域] 本發明係有關一種半導體裝置及其製造方法,尤指在 主面具備大量電流通過電極之半導體裝置及其製造方法。 [習知之技術] 伴隨著攜帶式終端裝置之普及,小型且大容量之鋰離 子電池成為追求之目標。為迎合攜帶式終端裝置輕量化之 需求’此種進行鐘離子電池充放電電源管理之保護電路基 板’亦不得不具備小型化及耐短路之效能。此保護電路基 板因内藏於鐘離手電池,故亦需隨之小型化,因而採行大 量運用晶片零件之COB(Chip 〇n Board)技術以回應其需 要…:而在另一方面’由於經離子電池與開關(switching) 疋件串聯連接,因此須同時顧及此開關元件之接通⑴…電 阻亦須縮小之課題。此為行動電話為延長其通話時間及待 機時間所不可欠缺之要素。 為了實現此低接通電阻(RDS(〇n))之目標,在晶片之製 造技術上,必須進行提升(積體電路)單元(cell)密度之開發 工作。 具體言之,於半導體基板表面形成通道(channei)之平 面構造中’單元密度為萬個/平方英时,而其接通電阻 則為27mQ。但在通道形成於溝渠(trench)側面之第i代溝 渠構造中’其單元密度大幅提升為2500萬個/平方英叶, 苴,乂:阻可降至l7mD。又,進而在第2代溝渠構造中, =,、度更大幅提升至·萬個/平方英吁 ”降為—。但此微細 作亦…… 本紙張尺度適用中國國家標準(CNS)A4規格⑵〇 χ 297公爱1-- 又 312328 * f --------------------^---------^ (請先閱讀背面之注意事項再填寫本頁)
I 1239089 A7
再 I 1¾. 2 312328 請 先 閱 讀 背 面 之 注 意 事 項 訂 線 1239089 A7 __________Β7_ 五、發明說明(3 ) 樣品B則和第13圖之構造相對應。表中結果顯示,將接 合細線自4條短線改為2條短線、2條長線之組合時,接 (請先閱讀背面之注意事項再填寫本頁) 通電阻成功地自13·43πιΩ減少了 1·33πιΩ,而成為12 1〇m Ω。 * [發明所欲解決之問題] 然而’現實狀況中,對於攜帶式終端裝置之小型化、 輕量化,以及延長内藏電池之使用時間等功能需求日切, 因而需要突破現有之P0WER M〇SFET等半導體裝置的實 際安裝構造及其組装方法,尋找能夠更有效減少接通電阻 之解決方法。 又’習知之技術中雖確立將p〇WER MOSFET等半導 體裝置以一個框架組合之製造方法,但在此製造方法中, 半導體晶片上面之電極的引出,仍須依賴線接合(wire bonding),因而具有在影響最大之半導體晶片上面之電流 通過電極(亦即源極)之引出方面仍沒有改善p〇WER MOSFET之接通電阻之解決方案之問題。 [解決問題之方案] 經濟部智慧財產局員工消費合作社印製 本發明係鑒於别述各問題點而開發者,其特徵在具 備:下框架’由能夠固著半導體晶片之晶片座以及和該晶 片座連結成一體之外部引線(lead)所構成;半導體晶片,固 著於該晶片座;上框架,由固著在形成於該半導體晶片上 面之電極上之抵接電極以及和該抵接電極連結成一體之外 部引線所構成;模塑樹脂,被覆該下框架之該晶片座及該 外部引線之一部分、以及該上框架之該抵接電極及外部引 本紙張尺度適用中國國家標準(CNS)A4規格⑵G χ 297公髮) 3 312328 1239089 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(4 ) 線之一部分。 又,其特徵在具備:準備下框架之步驟,該下框架係 由能夠固著半導體晶片之晶片座以及和該晶片座連結成一 體之外部弓丨線所構成;將半導體晶片固著於該晶片座之步 驟;準備上框架之步驟,該上框架係由固著在形成於該半 導體晶片上面之電極上之抵接電極以及和該抵接電極連結 成一體之外部引線所構成;進行該下框架與該上框架之對 位’使該上框架之該抵接電極固著於該半導體晶片之預定 電極之步驟;以絕緣性樹脂被覆該下框架之該晶片座及該 外部引線之一部分、該上框架之該抵接電極及該外部引線 之一部分、及該半導體晶片以進行模塑之步驟。 [發明之實施形態] 以下參照第1圖至第10圖詳細說明本發明之實施形 態: 第1圖和第2圖所顯示者為本發明之半導體裝置實際 安裝構造。本半導體裝置包括:下框架4,由能夠固著^ 導體晶片1之晶片座2以及和晶片座2連結成一體之外部 引線3d所構成;半導體晶片!,固著於晶片座2;上框架 ’由固著在形成於半導體晶片!上面之電流通過電極5 上之抵接電極6以及和抵接電極6連結成—體之 3s;模塑樹脂8,被覆下框架4之底座2和外部引線μ之 -部分、以及上框架7之抵接電極6和外部弓丨線Μ —, 7 分 第1圖中,A顯示下框架4與半導體 本紙張尺度適用中國國家標準(CNS)A4規格⑵〇 x 297公爱) 晶片1之關係, 4 312328 (請先閱讀背面之注意事項再填寫本頁) 1239089
五、發明說明(5 -------------,¾ (請先閱讀背面之注意事項再填寫本頁) 而B則為下框架4之χ_χ線剖面圖。下框架*為以鋼為素 材所作之穿孔框架,正如第1圖Α所示,其構成部分有:、 位於中央部之晶片座2;與晶片座2連結成一體,並向周 圍=部9延伸之3條外部引線3d; 一端接近晶片座2,另 一端延伸至周圍之框部9,並與電極10相對應之外部引線 3g °而下框架4之剖面圖則如第工圖B所示,晶片座2與 和電極10才目對應之外部弓I線3g之前#,和其他部分之外 部引線3d、3g相比,呈現略為凸起之形狀。此乃為了使所 有之外部引線3d、3g、3s之表面幾乎一致之緣故。 半導體晶片1之上面設有佔據其大部分面積之電流通 過電極5及小面積之控制電極丨〇,而其背面則全部為電流 通過電極(未圖示)。半導體晶片1本身使用絕緣閘型半導 體元件之POWER MOSFET或將POWER MOSFET與電晶 體組合而成之複合元件IGBT (Insulated Gate BipQlar
Transister)。 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 POWER MOSFET之下面為有鍍金電極所形成之汲極 (未圖不),其上面有以蒸鍍方式鍍鋁/鈦/鎳/金或銀之閘極 10或源極5。汲極與源極以電流通過電極5之姿運作,而 閘極10則以控制電極之姿控制通道(channel)之開關。因 此,半導體晶片1之上面幾乎為源極5所佔據,而閘極i 〇 則位於其一角。下框架4之晶片座2上既定位置藉焊錫或 銀膠所構成之預先成型材而固著有p〇WER m〇SFET之裸 晶片1。閘極以使用金質接合細線u之球焊法與控制端子 之外部引線3 g電氣連接 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公 ^ 312328 1239089
經 濟 部 智 慧 財 產 局
I 社 印 製 第2圖中,A顧一 而B則為上框架7上框架7與半導體晶片1之關係, Lg ρη .Α ^ 之Yd線剖面圖。上框架7與下框孥4 相同,均係以鋼為素材所 、下U 4 固著在形成於半導體 框架S'構成部分有: 上之抵接電極6,以“面之源極等電流通過電極5 線3s。 抵接電極6連結成一體之外部引 此抵接電極6 >游# ^ t t/狀與本身為電流通過電 幾乎相同,而能將嗎拉入,勺“㈣电極5之源極 “、王邛覆蓋為理想。然而,實際上者 慮其與半導體晶片丨之斜#姓& 貫際上考 .〇 ^ L 之對位精度而決定其大小即可。又, 有2條外部引線3 J 又 4立 抵接電極6延伸至周圍之框部9。 口又〇十夺需主忍的是’此 邛引線3 s之配置必須不能盥下框 架4之4條外部弓丨線3d 〜、下汇 1 1嚭政私1 g相且a,並且不能與接合細線 11短路始可,而1於且脒〜 之形狀。 具體元成之狀態下,則會呈現S0P6 第2圖B所顯示者則為 W馮上框架之剖面圖。上框竿 從抵接電極6向上方及下方轡把 I呆刀別 方彎折,而自模塑樹脂8露出 部份則與下框架4之外部弓丨蠄w <外線3d、3g對齊,又,苴盥 架4之框部9相疊合之 /…、下r 刀,、而再向上彎折下框架4之展 度份即可。接著,下框架4扁盥午之厚 一 在一上框架7之外部引線3S 相疊合之框部9上設右缺口 上叹有缺口 12。此外,將抵接電極6向上 彎折係由於欲防止半導髅曰 千導體曰曰片1與外部引線3s短路之故。 又,此抵接電極6幾半盥、、塔权c 于一源極5之全部重疊,並以焊 錫或銀膠之預先成型材固定。 時之抵接電極6由於外部 引線3 s之彈簧作用而被壓著 ---原極5上,因此可形成良好 本紙張尺度適用中國國家標準(CNS)A4規 Ψ 屬 ----------------------^---------線 1^--- (請先閱讀背面之注意事項再填寫本頁) 6 312328 1239089
發明說明(7 之連接構造。 (請先閱讀背面之注意事項再填寫本頁) 模塑樹脂8係如第1圖A和第2圖八之虛線部份所 示’被覆下框架4之晶片座2及外部引線3d、3g之一部分, 以及上框架7之抵接電極6及外部$丨線&之—部分。故完 成後之半導體裝置上6條外部引線3d、以及3§係以如同 形成於一個框架的方式從模塑樹脂8伸出。 第9圖顯示應用本發明之樣品C、D之接通電阻的實 測值。由第9圖可知採用上框架7之抵接電極6時,本發 明之樣品C較習知之樣品B改善了 3 43ιηΏ。又,從金質 接合細線改變為上框架7之抵接電極6,相對於金質接合 細線時之電阻2·3πιΩ,上框架7之抵接電極6之電阻減至 〇·2ιηΩ,因此具有減低金質接合細線電阻2 1ιηΩ<效果。 從過去之接合細線改變為抵接電接6,則半導體晶片表面 之銘電極所具電阻之減低效果大約為〗33ιηΩ。 •線· 連接上框架7之抵接電極6之焊錫和銀膠之差別,比 較樣品C及樣品D,僅有0·07ιηΩ,與材質之特性幾乎無 關,此係由於預先成型材相對於其面積而言極薄之故。 經濟部智慧財產局員工消費合作社印製 接下來參照第1圖至第10圖說明本半導體褒置之製造 方法。 本發明之半導體裝置之製造方法包括:準備下框架4 之步驟,該下框架4係由能夠固著半導體晶片1之晶片座 2以及和晶片座2連結成一體之外部引線3 d所構成;將半 導體晶片1固著於晶片座2之步驟;準備上框架7之步驟, 該上框架7係由固著在形成於半導體晶片1上面之電流通 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) " ''—---- 7 312328 1239089
經濟部智慧財產局員工消費合作社印製 過電極5上之抵接電極6以及和抵接電極6連結成一體之 外部引線3s所構成;進行下框架4與上框架7,使上框架 7之抵接電極6固著在半導體晶片j之電流通過電極$上' 之步驟;以絕緣性樹脂被覆下框架4之晶片座2、外部今I 線3d、3g之一部分、上框架7之抵接電極6和外部引線 3s之一部分以及半導體晶片1以進行模塑之步驟。 第7圖所顯示者為半導體裝置之製造方法的流程圖。 依據此流程圖,半導體裝置包括切晶步驟、黏晶步驟、焊 線步驟、電極安裝步驟、模塑步驟、焊劑電鍍步驟和切割 折彎(cutbend)步驟。 於切晶步驟中,以切割鋸在劃線(scribe Hne)上,將由 多個絕緣閘型半導體元件之p〇WEr MOSFET或多個 POWERMOSFET與電晶體組合而成之複合元件1(^1所形 成之半導體晶圓(wafer)(未圖示)予以切割,使其分離成為 個別之半導體晶片1。接著,在各個半導體晶片i上面設 置佔據大部分面積之電流通過電極5和佔據小部分面積之 控制電極10,其背面亦全面設有電流通過電極。以p〇WER MOSFET為例’其下面有鍍金電極所形成之汲極(未圖 示)’其上面有以蒸鍍方式鍍銘/鈦/錄/金或銀之閘極或 源極5。汲極與源極以電流通過電極5之姿運作,而閘極 1 〇則以控制電極之姿控制通道(ehannei)之開關。 於黏晶步驟中,準備下框架4,而使半導體晶片1固 著在下框架4的晶片座2上。 第3圖與第4圖為顯示下框架4整體之平面圖。下框 本紙張尺度過用中關家標準(CNS)A4規格⑵G x 297公爱) 8 312328 (請先閱讀背面之注意事項再填寫本頁) ¾ L^T· •線. 1239089 A7 B7 五、發明說明(9 架4係以鋼為素絲 空 材之牙孔框架,其個別之引線圖宰正如第 1圖所示,包括位於令央邱圃茱正如弟 甲夹部伤之晶片座2;與晶片座2連結 成一體,並向周圍框部9 甲之3條外部引線3d ;以及〆 端接BB片座2’另一端延伸 哪、1甲至周圍之框部9,並與 1〇 相對應之外部弓1線3g。而其剖面圖則如第1 ® Μ^晶 片座d電極1〇相對應之外部引線3g之前端部,和其 他部分之外部引線3d、3 卜 swtt 呈現略為凸起之形狀。 由第3圖可知,各製造步驟之輸送及定位係利用等 間隔形成於下框架4之框部9兩端之圓形定位孔12。又, 下框架4之框部9上端另設有兩個正方形之對位13m,此 訂 對位孔在進仃上、下框架之對位時使用(參照第4圖)。此 外,下框架4之框部+ 下端之圓形疋位孔12正好以等間隔 之距離設置於與隼瞢φ…^ 果e中“線相一致之位置。為框部9所包 線 圍之一單元領域14中則有2個晶片座2及外部引線3d。 由第4圖可知’下框架4共有2〇行、3列之單元領域 14配置於上下端部之定位孔12之間,故i個下框架4共 有6〇個單元領域,而固定半導體晶片1之晶片座2則有 120個。附帶一提的是,第4圖中省略了各單元領域μ之 晶片座2及外部引線3d。 消 費 合 作 社 印 製 曰接下來則分別將半導體晶片丨黏接於各個單元領域Μ 之晶片座2之上。亦即,將POWER MOSFET的裸晶片等 半導體曰曰片1 錫或銀膠之預先成型材,並採用黏接 之方式固定於下框架4之晶片座2上。此時係利用上下端 •之定位孔12進行晶片座2之定位,且一格一格移動而將半 本紙張尺度適种關家標準(CNS)A7^_ (21G χ 297公爱) 9 312328 五、發明說明(10 ) 導體晶片1固定在下框架4的所有晶片座2上。 片座=:為:先成型材之情形,先料錫熔解於“ /後,再將半導體晶片置於其上並予以冷卻固 二而在以銀膠為預先成型材之情形,先在各晶片座2塗 ==,再將半導體晶片1暫時接上,然後在非氧 化乳體中加熱處理,使之固定。 :焊線步驟巾,係以金屬細線丨j連接半導體晶片1 之閘極等以外的電極1 〇及盥 對應之外部引線。閘極 等以外的電極1G係由自動辨認之接合機(bGnder)a球焊的 方2與金質接合細線u作電氣連接。此時亦使用上下端部 之疋位孔12進行晶片座之定位,並且自動地一袼一袼移動 而將下框架4上所有的半導體晶片1之閘極等之電極10 及與之對應之外部引線3g接合。 又,不使用此種接合方式之其他實施形態已於第W 圖中說明,故在此省略。 電極安裝步驟包括:準備上框架7之步驟,該上框架 7係由固著在形成於半導體晶片1上面之電流通過電極5、 上之抵接電極6以及和抵接電極6連結成一體之外部弓丨線 3d所構成,以及進行下框架4與上框架7之對位,使上框 架7之抵接電極6固著在半導體晶片1之電流通過電極5 上之步驟。 第5圖及第6圖為顯示上框架7整體之平面圖。上框 架7係以銅為素材所作之穿孔框架,其個別之導腳圖案已 如第2圖所示’由固著在形成於半導體晶片1上面之源3 本紙張尺_ ^關家鮮g)A_ (210 x 297公齣 、^ 1239089 五、發明說明(11 ) 等電流通過電極5上之 結成-體之外部如所構:以及和抵接電極6連 此抵接電極6之开彡灿丨、,1 極幾乎相同,而能將源極全部覆::::通=極::源 慮其與半導體晶片i之對位二:決 之框部9:=:::::S自此抵接電極6延伸至周圍 不能與下框架Q 4 /、疋’此外部引線3s之配置必須 斑接人细缭L祐1、外部引線3d、3g相疊合’並且不能 ,、接口、、,田線1 1短路始可,1 呈現SOP6之形狀。 -於』元成之狀態下’則會 第®B所顯不者則為上框架之剖面圖。上框架係從 抵接電極ό向上方彎折麸 、 8霞…… 下方弯折,而自模塑樹脂 8露出之部份則與下框竿 … 外部⑽3d、3g對齊,又, 其與下框架4之框部9相疊合之部分只需 4之厚度份即可。此外,下框架4在與上框架7之外部^ 向3s相疊合之框部9上設有缺口 12。又,將抵接電極$ 向上彎折係由於欲防止本莫辦 故。 止半導體晶片1與外部引線3s短路之 從第6圖中可清楚看出’上框架7之框部9與下框架 4同’為了各製造步驟之輸送及定位,其兩端形成有等間 ^之圓敎位孔U。又,上框架7之框部9上端另設有_ 圓形定位孔12交錯排列之正方形之對位孔,此正方妒 對位孔Uu係在進行上、下兩框架4、7之對位時使用,且/ 與下框架4之對位孔13m相同。對位孔13m、Uu 本紙張尺度適用中國國家標準(CNS)A4規格(210 χ 297公釐) 11 312328 1239089
製 12 之使用方法詳後述。又,為框部9所包圍之一單元領域14 中形成有2個抵接電極6及外部引線3 s。 此外’在第6圖中同時可看出,上框架7為了與下框 架4相對應,亦有20行、3列之單元領域配置於上下端部 之定位孔12之間’故1個上框架7共有6〇個單元領域14, 而抵接電極6則有12(M固。附帶一提的是,第6圖中亦省 略了各單元領域14之抵接電極6及外部引線3s。 接下來進行將下框架4與上框架7之對位。換言之’ 即係將分別設置於兩框架之對位孔13m、1刊相疊合。 第8圖A、B中只顯示設置於下框架4之對位孔i3m。 下框架4之對位孔13m在四邊設有向上彎折之導片i3G, 而其功能是為了嵌入第8圖c中和其相同大小之上框架7 之對位孔13u。此導片13G設計為最小限度之高度以免 造成黏晶步驟或焊線步驟之輸送障礙。 又’尚有其他之對位方法,其並不使用導片13G,而 是將導銷(guide pin)(未圖示)插入上、下框部之圓形定位孔 12,或是將同樣形成為正方形之導銷插入正方形之對位孔 13m、l3u。在此情況下由於沒有導片ΐ3ϋ,故不會造成黏 晶步驟或焊線步驟之輸送障礙。 在結束前述之對位工作後,上框架7之抵接電極6正 好位於源電極等之電流通過電極5之上方,而以焊錫或銀 膠之預先成型材固定。此時抵接電極6因外部引線之彈 女作用而壓著於源極5,故成為良好之連接構造。其工程 條件則與黏晶步騾相同。 认度適用中國國家標準(C_NS)A4規格⑽x29 ) 312328 --------^---------^ (請先閱讀背面之注意事項再填寫本頁) ί 1239089 A7 B7
於模塑工程φ 成 ^
Λ 程中,係以環氧樹脂等之絕緣性樹脂8fiT 框架4之晶片座2、外邱g丨綞μ ^ 野下 外部引線3d、3g之一部分、上框 接電極6和外部引線3s之一部分和半導體晶片ι進行 模塑法(transfer则叫。模塑範圍之大小正如第 和第2圖之虛線部份所示 曰 部引線3d、3g之一邮八 復[架4之日曰片座2及外 冑刀’以及上框架7之抵接電極6及外 :引 部分。故完成後之半導體裝置上6條外部5| 、’’ 3d、3g及3S係以如同形成於一個框架的方式從模塑 脂Μ申出,而S〇P6之形狀。 於焊劑電鑛步驟中,為使自模塑樹脂8露出之外部引 線3d、3g、3s能夠安裝於電路基板表面將外部引線以錫 等之焊接金屬被覆。 於切割折f步驟中,以切斷金屬模具,將上、下兩框 架7之外部引線3d、3g、3s及兩框架之框部9切斷, 使之分離為個別之半導體裝置。其後若有需要,再將從模 塑樹脂8伸出之外部引線3d、3g、3s衝壓(press)成所需之 形狀。 部 -------------¾ ί請先閱讀背面之注意事項再填寫本頁) --線· 第10圖所顯示者為本發明之其他實施形態。本實 施开/匕、為不進行焊線之方法。此方法係在上框架7上設置 閘電極等之電極10的抵接電極15,以及和抵接電極成 為一體,並延伸至框部之外部引線3g。此閘極抵接電極15 係在電極安裝步驟中與抵接電極6一起以預先成型材固定 於閘電極1 〇之上。在此方法中,由於對位精密之關係,相 ,較於焊線之方法必須將閘電極10之體積放大,如此將導致 本紙張尺度適用中國國A準(CNS)A4規格⑽x 297公爱1---— 13 312328 Ϊ239089
電流通過電極5之面積縮小,而使接通電阻略為增加。但 由於可省略焊線步驟,因此在縮短其製造流程上有其長 處。 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 再者’本發明並不限於S0P6之封裝,在s〇P8或將2 個半導體晶片裝入同一個封裝體之實際安裝構造中亦可採 用。 [發明之功效] 按照本發明之半導體裝置,第一、由於在下框架4設 置晶片座2、在上框架7設置抵接電極6,使得半導體晶片 1能夠黏接在晶片座2上,且抵接電極6與半導體晶片1 之電流通過電極5幾乎重叠,因而成為能夠安裝電極之安 ^構造。按此結果,接通電阻由於烊線之改良,自原本樣 之12·10ηιΩ降至本發明樣品€之867πιΩ,其 達 30〇/〇 〇 第二、由於半導體晶片1與下框架4之晶片座2相接, 其:方大部分能夠與上框架7之抵接電極6相接合,因此 性極佳之良好構造。因此,負載短路或過電流通 向來之例如金線之接合細線不同,不至於立刻將抿 接電極ό熔斷,又,即使發哉 一 堅固之半導體裝置。迅速散熱,因此成為極 皆之構造在接通電阻及散熱方面表現 亦能將半導體晶片!之尺寸規7可之情況下, 護電路基板小型化之要求。為縮小,進一步能夠呼應保 1本紙張尺_ _ _ _A4 (請先閱讀背面之注意事項再填寫本頁) 導 訂·· •線· 14 312328 1239089
五、發明說明(I5 ) 經濟部智慧財產局員工消費合作社印製 依據本半導體裝置之製造方法,第一、由於使用上、 下兩個框架4、7,因而能使接在半導體晶片i下面之晶片 座2與接在半導體晶片1上面之電流通過電極5上之抵接 電極6重疊,進而能夠使用廉價之穿孔框架進行裝配工 作。因此能夠提升相關之MOSFET、IGBT等從事進行開關 動作之半導體晶片1之裝配的量產性。 第二、由於在上、下框架4、7之相對應位置設有對位 孔13m、13u,並且以導片13G進行對位,因此上框架7 之抵接電極6與半導體晶片1之電流通過電極5能夠自動 對位,具有與一個框架相同之優點。又,能夠省略與電流 通過電極5之接合,故能夠同時縮短其工作流程。 第三、由於上框架7設有閘電極等之電極1〇之抵接電 極15,以及與該抵接電極15成為一體,並向框部延伸之 外部引線3 g之故,能夠省略焊線步驟,亦能縮短工作流 程。 第四、即使使用兩個框架,亦能直接使用以往一個框 架時之裝配線,其所完成之半導體裝置亦可形成為與丨個 框架所組成者相同之封裝形狀。 [圖面之簡單說明] 第1圖為用以說明本發明之半導體裝置的圖,第1圖 A為其平面圖,而第1圖b則為第1圖a之χ_χ剖面圖。 第2圖為用以說明本發明之半導體裝置的圖,第2圖 Α為其平面圖’而第2圖Β則為第2圖Α之Υ-Υ剖面圖。 第3圖為用以說明本發明之半導體裝置所用的下框架 本紙張尺度適用中國國家標準(CNS)A4規格(21G X 297公爱) -----— 15 312328 (請先閱讀背面之注意事項再填寫本頁) ¾ · --線- 1239089 A7 經濟部智慧財產局員Η消費合作社印製 五、發明說明(16 ) 的平面圖。 第4圖為用以說明本發明之半導體裝置所用的下框架 整體的平面圖。 第5圖為用以說明本發明之半導體裝置所用的上框架 的平面圖。 第6圖為用以說明本發明之半導體裝置所用的上框架 的整體平面圖。 第7圖為用以說明本發明之製造方法的步驟流程圖。 第8圖為用以說明本發明之製造方法的對位步驟的 圖’第8圖A為用以說明設置於下框架之對位孔的平面 圖,第8圖B則為第8圖八之z_z線剖面圖,第8以 為用以說明設置於上框架之對位孔的平面圖。 第9圖為用以說明本發明及習知技術之特性的圖。 第1 〇圖為用以說明本發明之其他實施形態的平面 第11圖為用以說明習知之開關元件的實際安裝構造 的圖。 第12圖為用以說明習知之開關元件的實際安襞構造 的圖。 第13圖為用以說明習知之開關元件的實際安裴構造 的圖。 [元件符號說明] 1 半導體晶片 2 3d 外部引線 3g G氏張尺度適用中國國家標準(CNS)A4規格⑽x 297公£) (請先閱讀背面之注意事項再填寫本頁) % •線- 晶片座 外部引線 16 312328 A7 1239089 B7 五、發明說明(17 ) 經濟部智慧財產局員工消費合作杜印製 3s 外部引線 4 下框架 5 電流通過電極 6 抵接電極 7 上框架 8 模塑樹脂 9 框部 10 控制電極 12 圓形定位孔 13G 導片 13m 正方形對位孔 13u 正方形對位孔 14 單元領域 15 抵接電極 21 晶片座 22 預先成型材 23 裸晶片 24 接合細線 25 汲極端子 26 閘極端子 27 源極端子 (請先閱讀背面之注意事項再填寫本頁)
-----HP 訂---------線 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 17 312328

Claims (1)

1239089
H3 a 第090106044號專利申請案 申請專利範圍修正本 _ (92年3月25日: •一種半導體裝置之製造方法,其特徵在包括: ^準備下框架之步驟,該下框架係在以框部所包圍之 單元領域中配置固著半導體晶片之晶片座以及和該晶 片座連結成一體之外部引線; 將半導體晶片固著於該晶片座之步驟; ^準備上框架之步驟,該上框架係在以框部所包圍之 T元領域中配置固著在形成於該半導體晶片上面之電 /爪通過電極上之抵接電極,以及和該抵接電極連結成一 體之外部引線所構成; 將該下框架與該上框架互相重疊,且使各框架所對 應之該單元領域之該外部引線對位,而使該上框架之該 -接電極固著於該半導體晶片之該電流通過電極之步 驟;以及 經濟部中央標準局員工福利委員會印製 以絕緣性樹脂被覆該下框架之該晶片座及該外部 引線之一部分、該上框架之該抵接電極及外部引線之一 4刀以及半導體晶片以進行模塑之步驟。 2·如申請專利範圍第丨項之半導體裝置之製造方法,其 中,該下框架與該上框架之對位,係以在該下框架設置 對位孔,然後使由該對位孔之周邊彎折而成的導片嵌入 該上框架之對位孔的方式進行。 3·如申請專利範圍第丨項之半導體裝置之製造方法,i i紙張尺度適用中國國家標準(CNS) Α4規格(21〇χ 297公爱) 312328 1239089 H3 中該下框架設有鄰接於該晶片座之該半導體晶片之其 他電極的外部引線。 4·如申請專利範圍第3項之半導體裝置之製造方法,其 中,在將半導體晶片固著於該晶片座之步驟後,具有以 金屬細線連結該半導體晶片之其他電極及與之對應之 該外部引線之步驟。 5·如申請專利範圍第〗項之半導體裝置之製造方法,其 中,該上框架設有大致與該抵接電極及和該抵接電極連 成一體之外部引線並行延伸之與該半導體晶片之其他 電極相抵接之該其他電極的抵接電極及和該抵接電極 連結成一體之外部引線。 6. 如申請專利範圍第5項之半導體裝置之製造方法,其 中,在使該上框架之該抵接電極固著於該半導體晶片之 該電流通過電極的步驟中,同時該其他電極的抵接電極 固著於該其他電極。 7. 如申請專利錢第!項至第6項中任—項之半導體裝置 之製造方法,其中,該半導體晶片係由絕緣閉型 元件所構成。 8. 如申請專利範圍第】項至第6項中任—項之半導體裝置 之製造方法,其中,該半導體晶片係由 所構成。 9. 如申請專利範圍第!項至第6項中任一項之半導體裝置 之製造方法’其中,該下框架之該晶片座及該外部I線 係由單一之框架材料所形成。 V 312328 本紙張尺度適用中關家標準(〖NS) A4規袼 1239089 經濟部中央標準局員工福利委員會印製 H3 1〇.如申請專利範圍第!項至第6項中任一項之半導體裝置 之製造=法’其中’該上框架之該抵接電極及該外部引 線係由單一之框架材料所形成。 η·如申請專利範圍第1項之半導體裝置之製造方法,i 中,形成多數個該上框架之該單元領域及該下框架之、咳 單元領域。 w 12·如申請專利範圍帛!項之半導體裝置之製造方法,其 中,在該上框架之該單元領域及該下框架之該單元領域 設置2組該外部引線。 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 3 312328
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