TWI236607B - A common data model representing a circuit that will be fabricated on an integrated circuit chip - Google Patents
A common data model representing a circuit that will be fabricated on an integrated circuit chip Download PDFInfo
- Publication number
- TWI236607B TWI236607B TW089107888A TW89107888A TWI236607B TW I236607 B TWI236607 B TW I236607B TW 089107888 A TW089107888 A TW 089107888A TW 89107888 A TW89107888 A TW 89107888A TW I236607 B TWI236607 B TW I236607B
- Authority
- TW
- Taiwan
- Prior art keywords
- scope
- patent application
- circuit
- item
- model
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/300,540 US6505328B1 (en) | 1999-04-27 | 1999-04-27 | Method for storing multiple levels of design data in a common database |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TWI236607B true TWI236607B (en) | 2005-07-21 |
Family
ID=23159532
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW089107888A TWI236607B (en) | 1999-04-27 | 2000-05-04 | A common data model representing a circuit that will be fabricated on an integrated circuit chip |
Country Status (6)
| Country | Link |
|---|---|
| US (4) | US6505328B1 (https=) |
| EP (1) | EP1092201A1 (https=) |
| JP (1) | JP2002543498A (https=) |
| AU (1) | AU4370100A (https=) |
| TW (1) | TWI236607B (https=) |
| WO (1) | WO2000065492A1 (https=) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI424327B (zh) * | 2008-10-27 | 2014-01-21 | Synopsys Inc | 用於處理電路設計之電腦實作表示的方法、設備、資料處理系統及提供相應軟體的產品 |
| TWI895559B (zh) * | 2020-11-30 | 2025-09-01 | 美商賽諾西斯公司 | 用於翻譯電子電路之設計規格之非暫時性電腦可讀儲存媒體、方法及系統 |
Families Citing this family (73)
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| US7197724B2 (en) * | 2002-01-17 | 2007-03-27 | Intel Corporation | Modeling a logic design |
| US20030145311A1 (en) * | 2002-01-25 | 2003-07-31 | Wheeler William R. | Generating simulation code |
| FR2836734B1 (fr) * | 2002-03-01 | 2004-07-02 | Prosilog S A | Procede d'extraction de la topologie d'un systeme a partir de sa description textuelle |
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| US7627842B1 (en) | 2003-06-03 | 2009-12-01 | Cadence Design Systems, Inc. | Method and system for verification of circuits with encoded signals |
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| JP4183182B2 (ja) * | 2003-08-22 | 2008-11-19 | 株式会社リコー | 設計支援装置および設計支援方法 |
| US7493492B2 (en) * | 2004-04-17 | 2009-02-17 | International Business Machines Corporation | Limiting access to publicly available object-oriented interfaces via password arguments |
| JP2006079447A (ja) * | 2004-09-10 | 2006-03-23 | Fujitsu Ltd | 集積回路設計支援装置、集積回路設計支援方法及び集積回路設計支援プログラム |
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| US7523423B1 (en) * | 2004-12-10 | 2009-04-21 | Synopsys, Inc. | Method and apparatus for production of data-flow-graphs by symbolic simulation |
| US7483823B2 (en) | 2005-06-21 | 2009-01-27 | Nvidia Corporation | Building integrated circuits using logical units |
| EP1736905A3 (en) * | 2005-06-21 | 2007-09-05 | Nvidia Corporation | Building integrated circuits using logical units |
| US7363610B2 (en) * | 2005-06-21 | 2008-04-22 | Nvidia Corporation | Building integrated circuits using a common database |
| US7191412B1 (en) * | 2005-09-28 | 2007-03-13 | Xilinx, Inc. | Method and apparatus for processing a circuit description for logic simulation |
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| US8653857B2 (en) * | 2006-03-09 | 2014-02-18 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
| US8448102B2 (en) | 2006-03-09 | 2013-05-21 | Tela Innovations, Inc. | Optimizing layout of irregular structures in regular layout context |
| US9009641B2 (en) | 2006-03-09 | 2015-04-14 | Tela Innovations, Inc. | Circuits with linear finfet structures |
| US9563733B2 (en) * | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
| US8247846B2 (en) * | 2006-03-09 | 2012-08-21 | Tela Innovations, Inc. | Oversized contacts and vias in semiconductor chip defined by linearly constrained topology |
| US9230910B2 (en) | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
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| US7917879B2 (en) * | 2007-08-02 | 2011-03-29 | Tela Innovations, Inc. | Semiconductor device with dynamic array section |
| US8245180B2 (en) * | 2006-03-09 | 2012-08-14 | Tela Innovations, Inc. | Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same |
| US9035359B2 (en) | 2006-03-09 | 2015-05-19 | Tela Innovations, Inc. | Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods |
| US7446352B2 (en) * | 2006-03-09 | 2008-11-04 | Tela Innovations, Inc. | Dynamic array architecture |
| US8839175B2 (en) | 2006-03-09 | 2014-09-16 | Tela Innovations, Inc. | Scalable meta-data objects |
| US7943967B2 (en) * | 2006-03-09 | 2011-05-17 | Tela Innovations, Inc. | Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments |
| US7956421B2 (en) * | 2008-03-13 | 2011-06-07 | Tela Innovations, Inc. | Cross-coupled transistor layouts in restricted gate level layout architecture |
| US8225261B2 (en) * | 2006-03-09 | 2012-07-17 | Tela Innovations, Inc. | Methods for defining contact grid in dynamic array architecture |
| US8658542B2 (en) | 2006-03-09 | 2014-02-25 | Tela Innovations, Inc. | Coarse grid design methods and structures |
| US8541879B2 (en) | 2007-12-13 | 2013-09-24 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
| US8302042B2 (en) * | 2006-07-24 | 2012-10-30 | Oasys Design Systems | Generating a convergent circuit design from a functional description using entities having access to the functional description and to physical design information |
| US8286107B2 (en) * | 2007-02-20 | 2012-10-09 | Tela Innovations, Inc. | Methods and systems for process compensation technique acceleration |
| US7979829B2 (en) | 2007-02-20 | 2011-07-12 | Tela Innovations, Inc. | Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods |
| US8667443B2 (en) | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
| US8453094B2 (en) | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
| US7939443B2 (en) | 2008-03-27 | 2011-05-10 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
| KR101903975B1 (ko) * | 2008-07-16 | 2018-10-04 | 텔라 이노베이션스, 인코포레이티드 | 동적 어레이 아키텍쳐에서의 셀 페이징과 배치를 위한 방법 및 그 구현 |
| US9122832B2 (en) * | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
| US9489477B2 (en) | 2008-09-24 | 2016-11-08 | Synopsys, Inc. | Method and apparatus for word-level netlist reduction and verification using same |
| US8136063B2 (en) * | 2008-11-14 | 2012-03-13 | Synopsys, Inc. | Unfolding algorithm in multirate system folding |
| US8661392B2 (en) | 2009-10-13 | 2014-02-25 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the Same |
| US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
| US9652572B2 (en) | 2013-01-08 | 2017-05-16 | Nxp Usa, Inc. | Method and apparatus for performing logic synthesis |
| CN107967704A (zh) * | 2016-10-20 | 2018-04-27 | 上海复旦微电子集团股份有限公司 | 一种fpga芯片版图连线显示方法 |
| US10755017B2 (en) | 2018-07-12 | 2020-08-25 | International Business Machines Corporation | Cell placement in a circuit with shared inputs and outputs |
| US10742218B2 (en) | 2018-07-23 | 2020-08-11 | International Business Machines Corpoartion | Vertical transport logic circuit cell with shared pitch |
| US10733341B1 (en) * | 2019-03-27 | 2020-08-04 | Architecture Technology Corporation | Version control of an integrated circuit design and tracking of pre-fabrication, fabrication, and post-fabrication processes |
| US11087059B2 (en) * | 2019-06-22 | 2021-08-10 | Synopsys, Inc. | Clock domain crossing verification of integrated circuit design using parameter inference |
| WO2025127015A1 (ja) * | 2023-12-11 | 2025-06-19 | 株式会社Fsmc | 設計支援システム、設計支援装置および設計支援方法 |
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-
1999
- 1999-04-27 US US09/300,540 patent/US6505328B1/en not_active Expired - Lifetime
-
2000
- 2000-04-24 AU AU43701/00A patent/AU4370100A/en not_active Abandoned
- 2000-04-24 WO PCT/US2000/011012 patent/WO2000065492A1/en not_active Ceased
- 2000-04-24 JP JP2000614166A patent/JP2002543498A/ja active Pending
- 2000-04-24 EP EP00923607A patent/EP1092201A1/en not_active Withdrawn
- 2000-05-04 TW TW089107888A patent/TWI236607B/zh not_active IP Right Cessation
-
2002
- 2002-05-31 US US10/159,531 patent/US20020188922A1/en not_active Abandoned
-
2006
- 2006-01-05 US US11/327,550 patent/US20060117279A1/en not_active Abandoned
-
2008
- 2008-05-01 US US12/113,834 patent/US20080209364A1/en not_active Abandoned
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI424327B (zh) * | 2008-10-27 | 2014-01-21 | Synopsys Inc | 用於處理電路設計之電腦實作表示的方法、設備、資料處理系統及提供相應軟體的產品 |
| TWI895559B (zh) * | 2020-11-30 | 2025-09-01 | 美商賽諾西斯公司 | 用於翻譯電子電路之設計規格之非暫時性電腦可讀儲存媒體、方法及系統 |
Also Published As
| Publication number | Publication date |
|---|---|
| AU4370100A (en) | 2000-11-10 |
| JP2002543498A (ja) | 2002-12-17 |
| EP1092201A1 (en) | 2001-04-18 |
| WO2000065492A1 (en) | 2000-11-02 |
| US20020188922A1 (en) | 2002-12-12 |
| US6505328B1 (en) | 2003-01-07 |
| US20080209364A1 (en) | 2008-08-28 |
| US20060117279A1 (en) | 2006-06-01 |
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