TWI236607B - A common data model representing a circuit that will be fabricated on an integrated circuit chip - Google Patents

A common data model representing a circuit that will be fabricated on an integrated circuit chip Download PDF

Info

Publication number
TWI236607B
TWI236607B TW089107888A TW89107888A TWI236607B TW I236607 B TWI236607 B TW I236607B TW 089107888 A TW089107888 A TW 089107888A TW 89107888 A TW89107888 A TW 89107888A TW I236607 B TWI236607 B TW I236607B
Authority
TW
Taiwan
Prior art keywords
scope
patent application
circuit
item
model
Prior art date
Application number
TW089107888A
Other languages
English (en)
Chinese (zh)
Inventor
Ginneken Lukas P P P Van
Patrick R Groeneveld
Wilhelmus J M Philipsen
Original Assignee
Magma Design Automation Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Magma Design Automation Inc filed Critical Magma Design Automation Inc
Application granted granted Critical
Publication of TWI236607B publication Critical patent/TWI236607B/zh

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/32Circuit design at the digital level
    • G06F30/327Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
TW089107888A 1999-04-27 2000-05-04 A common data model representing a circuit that will be fabricated on an integrated circuit chip TWI236607B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/300,540 US6505328B1 (en) 1999-04-27 1999-04-27 Method for storing multiple levels of design data in a common database

Publications (1)

Publication Number Publication Date
TWI236607B true TWI236607B (en) 2005-07-21

Family

ID=23159532

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089107888A TWI236607B (en) 1999-04-27 2000-05-04 A common data model representing a circuit that will be fabricated on an integrated circuit chip

Country Status (6)

Country Link
US (4) US6505328B1 (https=)
EP (1) EP1092201A1 (https=)
JP (1) JP2002543498A (https=)
AU (1) AU4370100A (https=)
TW (1) TWI236607B (https=)
WO (1) WO2000065492A1 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI424327B (zh) * 2008-10-27 2014-01-21 Synopsys Inc 用於處理電路設計之電腦實作表示的方法、設備、資料處理系統及提供相應軟體的產品
TWI895559B (zh) * 2020-11-30 2025-09-01 美商賽諾西斯公司 用於翻譯電子電路之設計規格之非暫時性電腦可讀儲存媒體、方法及系統

Families Citing this family (73)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6519754B1 (en) * 1999-05-17 2003-02-11 Synplicity, Inc. Methods and apparatuses for designing integrated circuits
US6691286B1 (en) * 2000-10-31 2004-02-10 Synplicity, Inc. Methods and apparatuses for checking equivalence of circuits
US6801884B2 (en) * 2001-02-09 2004-10-05 Hewlett-Packard Development Company, L.P. Method and apparatus for traversing net connectivity through design hierarchy
JP2003030269A (ja) * 2001-05-16 2003-01-31 Internatl Business Mach Corp <Ibm> メタモデルを用いた単一マイクロプロセッサ上の並列シミュレーションのための方法
US7082104B2 (en) * 2001-05-18 2006-07-25 Intel Corporation Network device switch
WO2002103551A1 (en) * 2001-06-15 2002-12-27 Cadence Design Systems, Inc. Enhancing mergeability of datapaths and reducing datapath widths by rebalancing data flow topology
US7093224B2 (en) 2001-08-28 2006-08-15 Intel Corporation Model-based logic design
US6983427B2 (en) * 2001-08-29 2006-01-03 Intel Corporation Generating a logic design
US7073156B2 (en) * 2001-08-29 2006-07-04 Intel Corporation Gate estimation process and method
US6859913B2 (en) * 2001-08-29 2005-02-22 Intel Corporation Representing a simulation model using a hardware configuration database
US20030046054A1 (en) * 2001-08-29 2003-03-06 Wheeler William R. Providing modeling instrumentation with an application programming interface to a GUI application
US20030046051A1 (en) * 2001-08-29 2003-03-06 Wheeler William R. Unified design parameter dependency management method and apparatus
US7107201B2 (en) * 2001-08-29 2006-09-12 Intel Corporation Simulating a logic design
US7130784B2 (en) * 2001-08-29 2006-10-31 Intel Corporation Logic simulation
US7197724B2 (en) * 2002-01-17 2007-03-27 Intel Corporation Modeling a logic design
US20030145311A1 (en) * 2002-01-25 2003-07-31 Wheeler William R. Generating simulation code
FR2836734B1 (fr) * 2002-03-01 2004-07-02 Prosilog S A Procede d'extraction de la topologie d'un systeme a partir de sa description textuelle
US6848084B1 (en) * 2002-07-02 2005-01-25 Cadence Design Systems, Inc. Method and apparatus for verification of memories at multiple abstraction levels
US7155708B2 (en) * 2002-10-31 2006-12-26 Src Computers, Inc. Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation
US6983456B2 (en) * 2002-10-31 2006-01-03 Src Computers, Inc. Process for converting programs in high-level programming languages to a unified executable for hybrid computing platforms
US7627842B1 (en) 2003-06-03 2009-12-01 Cadence Design Systems, Inc. Method and system for verification of circuits with encoded signals
JP4414690B2 (ja) * 2003-07-14 2010-02-10 株式会社日立ハイテクノロジーズ 半導体製造システム
US7584460B2 (en) * 2003-07-22 2009-09-01 Lsi Corporation Process and apparatus for abstracting IC design files
US7100134B2 (en) * 2003-08-18 2006-08-29 Aprio Technologies, Inc. Method and platform for integrated physical verifications and manufacturing enhancements
JP4183182B2 (ja) * 2003-08-22 2008-11-19 株式会社リコー 設計支援装置および設計支援方法
US7493492B2 (en) * 2004-04-17 2009-02-17 International Business Machines Corporation Limiting access to publicly available object-oriented interfaces via password arguments
JP2006079447A (ja) * 2004-09-10 2006-03-23 Fujitsu Ltd 集積回路設計支援装置、集積回路設計支援方法及び集積回路設計支援プログラム
US7155688B2 (en) * 2004-11-17 2006-12-26 Lsi Logic Corporation Memory generation and placement
US7523423B1 (en) * 2004-12-10 2009-04-21 Synopsys, Inc. Method and apparatus for production of data-flow-graphs by symbolic simulation
US7483823B2 (en) 2005-06-21 2009-01-27 Nvidia Corporation Building integrated circuits using logical units
EP1736905A3 (en) * 2005-06-21 2007-09-05 Nvidia Corporation Building integrated circuits using logical units
US7363610B2 (en) * 2005-06-21 2008-04-22 Nvidia Corporation Building integrated circuits using a common database
US7191412B1 (en) * 2005-09-28 2007-03-13 Xilinx, Inc. Method and apparatus for processing a circuit description for logic simulation
US7392492B2 (en) * 2005-09-30 2008-06-24 Rambus Inc. Multi-format consistency checking tool
US7424687B2 (en) * 2005-11-16 2008-09-09 Lsi Corporation Method and apparatus for mapping design memories to integrated circuit layout
US7932545B2 (en) 2006-03-09 2011-04-26 Tela Innovations, Inc. Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers
US8225239B2 (en) * 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining and utilizing sub-resolution features in linear topology
US8653857B2 (en) * 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US9563733B2 (en) * 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8247846B2 (en) * 2006-03-09 2012-08-21 Tela Innovations, Inc. Oversized contacts and vias in semiconductor chip defined by linearly constrained topology
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US7917879B2 (en) * 2007-08-02 2011-03-29 Tela Innovations, Inc. Semiconductor device with dynamic array section
US8245180B2 (en) * 2006-03-09 2012-08-14 Tela Innovations, Inc. Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US7446352B2 (en) * 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US7943967B2 (en) * 2006-03-09 2011-05-17 Tela Innovations, Inc. Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments
US7956421B2 (en) * 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US8225261B2 (en) * 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining contact grid in dynamic array architecture
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8302042B2 (en) * 2006-07-24 2012-10-30 Oasys Design Systems Generating a convergent circuit design from a functional description using entities having access to the functional description and to physical design information
US8286107B2 (en) * 2007-02-20 2012-10-09 Tela Innovations, Inc. Methods and systems for process compensation technique acceleration
US7979829B2 (en) 2007-02-20 2011-07-12 Tela Innovations, Inc. Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
KR101903975B1 (ko) * 2008-07-16 2018-10-04 텔라 이노베이션스, 인코포레이티드 동적 어레이 아키텍쳐에서의 셀 페이징과 배치를 위한 방법 및 그 구현
US9122832B2 (en) * 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US9489477B2 (en) 2008-09-24 2016-11-08 Synopsys, Inc. Method and apparatus for word-level netlist reduction and verification using same
US8136063B2 (en) * 2008-11-14 2012-03-13 Synopsys, Inc. Unfolding algorithm in multirate system folding
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US9652572B2 (en) 2013-01-08 2017-05-16 Nxp Usa, Inc. Method and apparatus for performing logic synthesis
CN107967704A (zh) * 2016-10-20 2018-04-27 上海复旦微电子集团股份有限公司 一种fpga芯片版图连线显示方法
US10755017B2 (en) 2018-07-12 2020-08-25 International Business Machines Corporation Cell placement in a circuit with shared inputs and outputs
US10742218B2 (en) 2018-07-23 2020-08-11 International Business Machines Corpoartion Vertical transport logic circuit cell with shared pitch
US10733341B1 (en) * 2019-03-27 2020-08-04 Architecture Technology Corporation Version control of an integrated circuit design and tracking of pre-fabrication, fabrication, and post-fabrication processes
US11087059B2 (en) * 2019-06-22 2021-08-10 Synopsys, Inc. Clock domain crossing verification of integrated circuit design using parameter inference
WO2025127015A1 (ja) * 2023-12-11 2025-06-19 株式会社Fsmc 設計支援システム、設計支援装置および設計支援方法

Family Cites Families (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5212650A (en) * 1986-09-12 1993-05-18 Digital Equipment Corporation Procedure and data structure for synthesis and transformation of logic circuit designs
AU7728187A (en) * 1986-09-12 1988-03-17 Digital Equipment Corporation Cad of logic circuits: rule structure for inserting new elements
CA1300265C (en) * 1987-06-22 1992-05-05 William Curtis Newman Block diagram simulator
EP0431532B1 (en) * 1989-12-04 2001-04-18 Matsushita Electric Industrial Co., Ltd. Placement optimization system aided by CAD
US5541849A (en) * 1990-04-06 1996-07-30 Lsi Logic Corporation Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of timing parameters
JPH05121547A (ja) * 1991-10-25 1993-05-18 Nec Corp 半導体集積回路の配線処理方法
US5491640A (en) * 1992-05-01 1996-02-13 Vlsi Technology, Inc. Method and apparatus for synthesizing datapaths for integrated circuit design and fabrication
US5432707A (en) * 1993-02-12 1995-07-11 International Business Machines Corporation Automated circuit design
US5528508A (en) * 1993-02-19 1996-06-18 International Business Machines Corporation System and method for verifying a hierarchical circuit design
US5761664A (en) 1993-06-11 1998-06-02 International Business Machines Corporation Hierarchical data model for design automation
US5487018A (en) * 1993-08-13 1996-01-23 Vlsi Technology, Inc. Electronic design automation apparatus and method utilizing a physical information database
JPH0765040A (ja) * 1993-08-24 1995-03-10 Matsushita Electric Ind Co Ltd 機能データインターフェース方法および機能データインターフェース装置
JP3227056B2 (ja) * 1994-06-14 2001-11-12 富士通株式会社 図形処理方法及び図形処理装置
US5764534A (en) 1994-10-13 1998-06-09 Xilinx, Inc. Method for providing placement information during design entry
JPH08188211A (ja) * 1994-11-09 1996-07-23 Honda Motor Co Ltd 自動倉庫における在庫状態の補正方法及びその補正装置と搬送状態の補正方法及びその補正装置
US5696693A (en) * 1995-03-31 1997-12-09 Unisys Corporation Method for placing logic functions and cells in a logic design using floor planning by analogy
US5784534A (en) * 1995-03-31 1998-07-21 Motorola, Inc. Circuit and method for representing fuzzy rule weights during a fuzzy logic operation
US5666288A (en) * 1995-04-21 1997-09-09 Motorola, Inc. Method and apparatus for designing an integrated circuit
US5726902A (en) * 1995-06-07 1998-03-10 Vlsi Technology, Inc. Method and apparatus for characterizing timing behavior of datapaths for integrated circuit design and fabrication
US5727187A (en) * 1995-08-31 1998-03-10 Unisys Corporation Method of using logical names in post-synthesis electronic design automation systems
US5699265A (en) * 1995-09-08 1997-12-16 Lsi Logic Corporation Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints
US5841663A (en) * 1995-09-14 1998-11-24 Vlsi Technology, Inc. Apparatus and method for synthesizing integrated circuits using parameterized HDL modules
US5757657A (en) 1996-02-07 1998-05-26 International Business Machines Corporation Adaptive incremental placement of circuits on VLSI chip
US6480995B1 (en) * 1996-04-15 2002-11-12 Altera Corporation Algorithm and methodology for the polygonalization of sparse circuit schematics
US5818729A (en) * 1996-05-23 1998-10-06 Synopsys, Inc. Method and system for placing cells using quadratic placement and a spanning tree model
US6349401B2 (en) * 1996-09-12 2002-02-19 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit, design method and computer-readable medium using a permissive current ratio
GB2318664B (en) * 1996-10-28 2000-08-23 Altera Corp Embedded logic analyzer for a programmable logic device
US6209123B1 (en) * 1996-11-01 2001-03-27 Motorola, Inc. Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors
US5960184A (en) * 1996-11-19 1999-09-28 Unisys Corporation Method and apparatus for providing optimization parameters to a logic optimizer tool
US5864487A (en) * 1996-11-19 1999-01-26 Unisys Corporation Method and apparatus for identifying gated clocks within a circuit design using a standard optimization tool
US6088693A (en) * 1996-12-06 2000-07-11 International Business Machines Corporation Data management system for file and database management
JP2954894B2 (ja) * 1996-12-13 1999-09-27 株式会社半導体理工学研究センター 集積回路設計方法、集積回路設計のためのデータベース装置および集積回路設計支援装置
JP4058127B2 (ja) * 1997-02-24 2008-03-05 富士通株式会社 半導体装置のレイアウト変更方法
US5956497A (en) * 1997-02-26 1999-09-21 Advanced Micro Devices, Inc. Methodology for designing an integrated circuit using a reduced cell library for preliminary synthesis
US6321366B1 (en) * 1997-05-02 2001-11-20 Axis Systems, Inc. Timing-insensitive glitch-free logic system and method
US6370679B1 (en) * 1997-09-17 2002-04-09 Numerical Technologies, Inc. Data hierarchy layout correction and verification method and apparatus
US6011911A (en) * 1997-09-30 2000-01-04 Synopsys, Inc. Layout overlap detection with selective flattening in computer implemented integrated circuit design
US6145874A (en) * 1997-10-29 2000-11-14 Trw Inc. Passenger air bag disable switch
US6148432A (en) * 1997-11-17 2000-11-14 Micron Technology, Inc. Inserting buffers between modules to limit changes to inter-module signals during ASIC design and synthesis
US6145117A (en) * 1998-01-30 2000-11-07 Tera Systems Incorporated Creating optimized physical implementations from high-level descriptions of electronic design using placement based information
US6080201A (en) * 1998-02-10 2000-06-27 International Business Machines Corporation Integrated placement and synthesis for timing closure of microprocessors
US6263483B1 (en) * 1998-02-20 2001-07-17 Lsi Logic Corporation Method of accessing the generic netlist created by synopsys design compilier
US6216258B1 (en) * 1998-03-27 2001-04-10 Xilinx, Inc. FPGA modules parameterized by expressions
US6154874A (en) * 1998-04-17 2000-11-28 Lsi Logic Corporation Memory-saving method and apparatus for partitioning high fanout nets
US6915249B1 (en) * 1998-05-14 2005-07-05 Fujitsu Limited Noise checking method and apparatus
US6862563B1 (en) * 1998-10-14 2005-03-01 Arc International Method and apparatus for managing the configuration and functionality of a semiconductor design
US6477683B1 (en) * 1999-02-05 2002-11-05 Tensilica, Inc. Automated processor generation system for designing a configurable processor and method for the same
US6289489B1 (en) * 1999-02-23 2001-09-11 Stephen L. Bold Method and apparatus for automatically cross-referencing graphical objects and HDL statements
US6308309B1 (en) * 1999-08-13 2001-10-23 Xilinx, Inc. Place-holding library elements for defining routing paths
AU2003274370A1 (en) * 2002-06-07 2003-12-22 Praesagus, Inc. Characterization adn reduction of variation for integrated circuits
US7055113B2 (en) * 2002-12-31 2006-05-30 Lsi Logic Corporation Simplified process to design integrated circuits

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI424327B (zh) * 2008-10-27 2014-01-21 Synopsys Inc 用於處理電路設計之電腦實作表示的方法、設備、資料處理系統及提供相應軟體的產品
TWI895559B (zh) * 2020-11-30 2025-09-01 美商賽諾西斯公司 用於翻譯電子電路之設計規格之非暫時性電腦可讀儲存媒體、方法及系統

Also Published As

Publication number Publication date
AU4370100A (en) 2000-11-10
JP2002543498A (ja) 2002-12-17
EP1092201A1 (en) 2001-04-18
WO2000065492A1 (en) 2000-11-02
US20020188922A1 (en) 2002-12-12
US6505328B1 (en) 2003-01-07
US20080209364A1 (en) 2008-08-28
US20060117279A1 (en) 2006-06-01

Similar Documents

Publication Publication Date Title
TWI236607B (en) A common data model representing a circuit that will be fabricated on an integrated circuit chip
US5726902A (en) Method and apparatus for characterizing timing behavior of datapaths for integrated circuit design and fabrication
US6317860B1 (en) Electronic design automation tool for display of design profile
US5831869A (en) Method of compacting data representations of hierarchical logic designs used for static timing analysis
US9798840B1 (en) Methods, systems, and computer program product for implementing a simulation platform with dynamic device model libraries for electronic designs
US7949987B1 (en) Method and system for implementing abstract layout structures with parameterized cells
US5528508A (en) System and method for verifying a hierarchical circuit design
US5497334A (en) Application generator for use in verifying a hierarchical circuit design
US8516418B2 (en) Application of a relational database in integrated circuit design
US6263483B1 (en) Method of accessing the generic netlist created by synopsys design compilier
JP4768896B1 (ja) 製造ワークフローの為のチップデザインにおけるセルの整合性、変更、由来を独立評価する方法、及び、装置
US20020162086A1 (en) RTL annotation tool for layout induced netlist changes
US9934354B1 (en) Methods, systems, and computer program product for implementing a layout-driven, multi-fabric schematic design
US10558780B1 (en) Methods, systems, and computer program product for implementing schematic driven extracted views for an electronic design
US6289491B1 (en) Netlist analysis tool by degree of conformity
CN114925647A (zh) 门级网表迁移方法、机器可读介质及集成电路设计系统
JP2022536648A (ja) 平坦化されたネットリストからの挙動設計回復
Chhabria et al. OpenROAD and CircuitOps: Infrastructure for ML EDA research and education
Fu et al. Temacle: A technology mapping-aware area-efficient standard cell library extension framework
US7000206B2 (en) Timing path detailer
Baumgartner et al. Min-area retiming on flexible circuit structures
US20030229612A1 (en) Circuit design duplication system
US10997333B1 (en) Methods, systems, and computer program product for characterizing an electronic design with a schematic driven extracted view
CN120530396A (zh) 定制标准单元的自动创建
JPH07287051A (ja) 論理シミュレータ用入力データ作成装置

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees