TWI235418B - Method of producing semiconductor device - Google Patents

Method of producing semiconductor device Download PDF

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Publication number
TWI235418B
TWI235418B TW089119361A TW89119361A TWI235418B TW I235418 B TWI235418 B TW I235418B TW 089119361 A TW089119361 A TW 089119361A TW 89119361 A TW89119361 A TW 89119361A TW I235418 B TWI235418 B TW I235418B
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Taiwan
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silicon film
amorphous
film
semiconductor device
patent application
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TW089119361A
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Chinese (zh)
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Naoki Makita
Hiromi Sakamoto
Masao Moriguchi
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Sharp Kk
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02686—Pulsed laser beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1277—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using a crystallisation promoting species, e.g. local introduction of Ni catalyst
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

Abstract

In a production method of a semiconductor device, a catalyst element 104, e.g. Ni, is added to an amorphous silicon film 103, formed on a substrate 101 with an insulating surface, for promoting crystallization of the amorphous silicon film. Thereafter, the amorphous silicon film 103 is subjected to heat treatment to cause crystal growth therein. Next, the crystal growth is stopped in a state where minute amorphous regions (uncrystallized regions) remain in the film. Next, the silicon film is irradiated with strong light (laser light) 105 so as to be further crystallized. As a result, a crystalline silicon film 103a that has high quality and is excellent in uniformity is obtained.

Description

經濟部智慧財產局員工消費合作社印製 1235418 A7 ----------2Z_______ 五、發明說明（1 ) 發明之背景 ^發明與一種製造半導體裝置之方法有關，特別與使得 一無定形矽膜晶化而獲得結晶矽膜用做一作用區之製造半 導體裝置之方法有關。本發明尤其對使用在一個有絕緣表 面之基體上能形成薄膜電晶體（TFT)之半導體裝置有效且 可適用於活性矩陣型列晶顯示裝置、接觸式圖像感測器及 立體積體電路等。 近來大家均希望能有大型高析像度液晶顯示器、高速高 析像度接觸式圖像感測器及立體積體電路等並曾試圖在例 如玻璃之絕緣基體上或絕緣薄膜上形成高性能半導體裝 置。一般而言是將薄膜型矽半導體用爲上述各種裝置中所 用艾半導體裝置。薄膜型矽半導體大致可分爲兩類，亦即 無定形矽半導體所製造之半導體與結晶矽半導體製造之半 導體。 製造溫度低之無定形矽半導體很容易以汽相法製造且極 適於大量生產，所以最爲普遍使用，但無定形半導體在導 電特性方面卻不如具有晶性之矽半導體。因此希望能有以 晶性矽半導體製造半導體裝置之方法俾能獲得對高速特性 之改善。於是晶性矽半導體、多晶矽、微晶矽等已爲人所 知0 獲得具有晶性薄膜矽半導體之方法，已知者有下述三 種： (1)在形成薄膜時直接形成具有晶性薄膜之方法； (2 )形成一無定形半導體薄膜並使用雷射光能而使之結 -4- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公髮） ---.-----^---------^ (請先閱讀背面之注意事項再填寫本頁) 1235418Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1235418 A7 ---------- 2Z_______ V. Description of the Invention (1) Background of the Invention ^ The invention relates to a method for manufacturing a semiconductor device, and is particularly related to making an amorphous A method for manufacturing a semiconductor device using a crystalline silicon film to obtain a crystalline silicon film as an active region is related. The invention is particularly effective for a semiconductor device capable of forming a thin film transistor (TFT) on a substrate having an insulating surface, and is applicable to an active matrix columnar crystal display device, a contact image sensor, and a volumetric body circuit. . Recently, everyone hopes to have a large high-resolution liquid crystal display, a high-speed high-resolution contact image sensor, and a volumetric body circuit. They have tried to form a high-performance semiconductor on an insulating substrate such as glass or an insulating film. Device. Generally, a thin-film silicon semiconductor is used as the Ai semiconductor device used in the various devices described above. Thin-film silicon semiconductors can be roughly classified into two types, namely semiconductors made of amorphous silicon semiconductors and semiconductors made of crystalline silicon semiconductors. Amorphous silicon semiconductors with low manufacturing temperatures are easily manufactured by the vapor phase method and are very suitable for mass production, so they are most commonly used. However, amorphous semiconductors are not as good as crystalline silicon semiconductors in terms of electrical conductivity. Therefore, it is desirable to have a method for manufacturing a semiconductor device using a crystalline silicon semiconductor, which can improve the high-speed characteristics. Therefore, crystalline silicon semiconductors, polycrystalline silicon, microcrystalline silicon, etc. have been known. There are three methods for obtaining crystalline silicon semiconductors with crystalline thin films: (1) directly forming crystalline thin films when forming thin films Method; (2) Forming an amorphous semiconductor film and using laser light energy to make it a knot -4- The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 issued) ---.---- -^ --------- ^ (Please read the notes on the back before filling out this page) 1235418

經濟部智慧財產局員工消費合作社印製 五、發明說明（2 ) 晶之方法；及 (3)形成-無定料導體薄膜並對其加上熱能而使之結 晶之方法。 在第（1 )種万法中’結晶過程與薄膜之形成同時進行， 因此必須將膜加厚俾能有大顆粒之結晶矽，但在一基體之 整個表面上形成有均衡良好半導體物理特性之薄膜：：技 術上甚爲困難。 在第（2)種方法中，因爲是利用溶解至固化過程中之社 晶現象，雖然晶ft之難小，但適#處理顆粒邊界仍可獲 得高品質結晶矽膜。不過最常用者是激態分子雷射，但激 態分子雷射至今尚無足夠之穩定性。所以-個大面積基體 之整個表面作均句性之處理甚爲困難而且在硬體方面須有 進一步之改進。 第（3 )種方法在基體内部之均勻性與穩定性方面較之第 (1)與（2)種方法爲佳，但熱處理需要在6〇〇χ：經過約三十 個小時之長時間。因此有了長處理時間與低生產量之問 題。在改善結晶方面曾用一種使用氧氣以丨〇〇(rc高溫作熱 處理之技術。但普遍廉價之玻璃基體不能用於此項處理。 另外就裝置特性而言，在薄膜電晶體中僅能達到大約 100 cm2/Vs場效電子移動率之低性能。 在曰本第JP-A-6-244l〇3號專利曾建議一種改進第（3)種 方法來獲得咼品質結晶碎膜之方法做爲對上述三方法之對 應措施。此一方法疋欲能達到降低加熱溫度，縮短加熱時 間並使用促使典疋形石夕膜結晶之金屬元素來改善結晶。特 -5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I——·—訂---------線—^wi (請先閱讀背面之注意事項再填寫本頁) 1235418 五、發明說明（3 ) 刎疋對供疋形矽膜表面加上少量諸如鎳、鈀等金屬元素然 後、再加熱。 低溫結晶之機制如下：在成核之早期，金屬元素之作用 =同晶核，然後以金屬元素做爲促使晶體生成之觸媒，於 是即能快速晶化。就此方面而言，該金屬元素在下文中稱 爲「觸媒元素」。在經觸媒元素促使晶化而生成之結晶矽 膜中，其中每個顆粒之内部是由有若干個柱狀晶體之網所 構成而以傳式固態相位生成法所結晶之結晶發膜每一顆粒 ^内邵則有兩個晶體結構。每個柱狀晶體之内部均幾乎是 理想之單一晶體狀態。 ，按照日本第JP-A_7_221017號專利，將觸媒元素加入無定 形矽膜然後僅爲形成晶核而進行短時間之熱處理。接著再 用雷射光照射而促使其結晶。 經濟部智慧財產局員工消費合作社印製 _雖然使用觸媒元素結晶之碎膜有良好之晶性，但每個晶 體顆粒均有很多缺點。因石夕膜是用做高性能半導體裝置之 活性層，需要有高品質且缺點少之結晶石夕膜。爲求進一步 改善晶性，另一種方法是使用觸媒元素結晶後於氧化情形 =進行高溫（__11G(rc)熱處理，又—方法是使用觸媒元 晶後進行雷射S照射。前-方法（高溫氧化熱處理）被 %馬鬲溫加工，所以廉價之玻璃基體無法使用。 昭因此初步使用廉價之玻璃基體再採取後一種方法（雷射 …、射2)。在加入觸媒元素並經熱處理而獲得之結晶矽膜 !贿母一晶體顆粒均是由一柱狀晶體網所構成，每一柱狀 日曰肢〈寬度爲800-1000又。雖然個柱狀晶體之内部均爲單 -6 - 本紙張尺度適用中國^^NS)A4規格— X 297公釐） 1235418 A7 發明說明（ ::體狀態’纟因柱狀晶體之f曲或 會有諸如位錯等許多晶體㈣。雷射照射 ，瑕戚從有良好晶性之柱狀晶體成分中消失。== 到此點非常困難。 π上做 事實上當經過觸媒元素催化結晶切 X低功率雷射幾乎毫無效果。低功率雷射照射僅能= 原有又結晶狀態而並無任何顯著改善。另一方面，古工^ 雷射照射則會將原來之結晶狀態重組成類似僅用雷：：: t結晶之狀態。甚難形成一種低功率雷射所獲狀態與高 2雷射所獲狀態中間之結晶狀態而且雷射功率並無界限 功 言 可 經濟部智慧財產局員工消費合作社印製 因此以雷射光照射借助觸媒元素而結晶之矽膜來改善薄 膜電晶體作用區之晶性非常困難。尤其是即使進行雷射光 照射，結果造成之薄膜電晶體可能會有低電流驅動能力 特性’幾乎與具有僅使用觸媒元素而不作雷射照射所結 碎膜之薄膜電晶體之電流驅動能力並無太大差別。另一 情形是結果造成之薄膜電晶體雖然有類似具有僅以雷射照 射所結晶矽膜之薄膜電晶體之電流驅動能力但卻有很大之 特性變化。也就是説即使借助觸媒元素而結晶之矽膜再 上述傳統方法以雷射照射也不會有進一步之改善。 在前述之日本第JP-A-7-221017號專利曾説明將觸媒元 加入無定形矽膜後再進行短時間之熱處理僅能形成晶 核’然後再以雷射照射才使無定形矽膜結晶。也就是説 要之晶化是以雷射光之照射來完成而此種晶化方法足以從 之 種 用 素 體 主 —*—訂---------IAW1 (請先閱讀背面之注音？事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1235418 A7 五Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (2) Method of crystallizing; and (3) Method of forming-amorphous conductive film and adding thermal energy to it to crystallize. In the first method (1), the crystallization process and the formation of the thin film are performed simultaneously. Therefore, the film must be thickened so that large particles of crystalline silicon can be formed, but a well-balanced semiconductor physical property is formed on the entire surface of a substrate. Film: Technically it is difficult. In the (2) method, because the crystallizing phenomenon during the dissolution to solidification process is used, although the crystal ft is difficult, it is possible to obtain a high-quality crystalline silicon film by appropriately processing the grain boundary. However, the most commonly used is an excimer laser, but excimer lasers have not yet had sufficient stability. Therefore, it is very difficult to treat the entire surface of a large-area substrate with a uniform sentence and further improvements in hardware are required. The method (3) is better than the methods (1) and (2) in terms of uniformity and stability inside the substrate, but the heat treatment needs to be performed at 600 ×: after a period of about thirty hours. Therefore, there are problems of long processing time and low throughput. In the improvement of crystallization, a technology using oxygen to heat treatment at a high temperature has been used. However, generally inexpensive glass substrates cannot be used for this treatment. In addition, in terms of device characteristics, only about Low performance of 100 cm2 / Vs field-effect electron mobility. In Japanese Patent No. JP-A-6-24410, a method has been proposed to improve the method (3) to obtain a rubidium-quality crystalline film. Corresponding measures of the above three methods. This method is intended to reduce the heating temperature, shorten the heating time, and use the metal elements that promote the crystallization of the canonical stone-shaped film to improve the crystallization. Special-5 This paper is applicable to Chinese national standards (CNS ) A4 specification (210 X 297 mm) I—— · —Order --------- line— ^ wi (Please read the notes on the back before filling this page) 1235418 V. Description of the invention (3)刎 疋 Add a small amount of metal elements such as nickel and palladium to the surface of the silicon substrate, and then reheat. The mechanism of low temperature crystallization is as follows: in the early stage of nucleation, the role of metal elements = isomorphic nuclei, and then metal elements Catalyst for crystal formation It can be crystallized quickly. In this regard, the metal element is hereinafter referred to as "catalyst element". In the crystalline silicon film produced by the crystallization promoted by the catalyst element, the interior of each particle is formed by A crystal hair film formed by a network of several columnar crystals and crystallized by the transmission solid-state phase generation method has two crystal structures per particle. The interior of each columnar crystal is almost an ideal single crystal. State. According to Japanese Patent No. JP-A_7_221017, the catalyst element is added to the amorphous silicon film and then heat-treated for a short time just to form crystal nuclei. Then it is illuminated by laser light to promote its crystallization. Printed by the employee consumer cooperative_Although the broken film using catalyst element crystals has good crystallinity, each crystal particle has many shortcomings. Because Shixi film is used as the active layer of high-performance semiconductor devices, it needs high quality Crystal stone film with few defects. In order to further improve the crystallinity, another method is to use the catalyst element to crystallize and then oxidize = high temperature (__11G (rc) heat treatment, —The method is to use the catalyst element crystal and then perform laser S irradiation. The front-method (high-temperature oxidation heat treatment) is processed by% Ma Wen, so the cheap glass substrate cannot be used. So the preliminary use of the cheap glass substrate is adopted. Method (laser ..., shot 2). The crystalline silicon film obtained by adding the catalyst element and heat treatment! The crystal particles are composed of a columnar crystal network, and each columnar limb is <width It is 800-1000 again. Although the inside of each columnar crystal is single -6-This paper size is applicable to China ^^ NS) A4 size-X 297 mm) 1235418 A7 Description of the invention (:: body state '纟 因 Columnar The crystal f curve may have many crystals such as dislocations. With laser irradiation, the blemishes disappear from the columnar crystal components with good crystallinity. == This is very difficult. Doing on π In fact, low-power lasers have almost no effect when catalyzed by catalyst crystallization. Low-power laser irradiation can only = original and crystalline state without any significant improvement. On the other hand, the ancient work ^ laser irradiation will reorganize the original crystalline state similar to the state using only laser :: t crystal. It is very difficult to form a crystalline state between the state obtained by the low power laser and the state obtained by the high 2 laser and the laser power has no limit. It can be printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. It is very difficult to improve the crystallinity of the thin film transistor active region with a silicon film crystallized by a dielectric element. In particular, even if laser light is irradiated, the resulting thin film transistor may have a low current driving capability characteristic, which is almost the same as the current driving capability of a thin film transistor with a broken film formed by using only a catalyst element without laser irradiation. Too much difference. Another situation is that the resulting thin film transistor has a large characteristic change, although it has a current driving capability similar to that of a thin film transistor which is irradiated with a silicon film only by laser irradiation. That is to say, even if the silicon film crystallized by the catalyst element is further improved by laser irradiation in the above-mentioned conventional method. In the aforementioned Japanese Patent No. JP-A-7-221017, it was stated that adding a catalyst element to an amorphous silicon film and then performing a short time heat treatment can only form a crystal nucleus, and then using laser irradiation to make the amorphous silicon film. crystallization. That is to say, the crystallization is completed by the irradiation of laser light, and this crystallization method is sufficient to use the elemental master from the seed — * — Order --------- IAW1 (Please read the note on the back first ? Please fill in this page again) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 1235418 A7 5

、發明說明（S B7 雷射照射獲得良好之纟士 難、，所以在f μ #、口 。旦无份控制晶核之形成仍很困 在貫用上使用此-方法仍有困難。 本發明之摘要 產量上述之問題並提供-種簡單而有高 化少之半導體裝置絕緣表面之基體上製造高性能且特性變Description of the invention (S B7 Laser irradiation is difficult to obtain a good reputation, so at f μ #, the mouth. Once you have no control over the formation of crystal nuclei, it is still difficult to use this method. It is still difficult to use this method. Summary of the above-mentioned problems and provide-a simple and high-performance semiconductor substrate with high insulation performance

:發明各發明人之注意力集 J加7L素步驟_對無足形硬膜添加觸媒元來益 ^膜之晶化，該無定料膜係形成在具有絕緣表“基 第一次晶化步驟-對該無定形矽膜進行熱處理使之生成 :體，晶體之生成在仍有微小無定形區域之狀態下停止； 線 第二次晶化步驟·將在仍有微小無定形區之狀態下已停 止晶體生成之無定形矽膜用強光照射而使之進一步钟晶^ 經濟部智慧財產局員工消費合作社印製 按照此一方法是將觸媒元素加入無定形矽膜而以熱處理 使無定形矽膜生成晶體。但熱處理並未使無定形矽膜完全 晶化。晶體之生成在仍存有微小無定形區域（未結晶區域） 之狀態下停止。此一混合有微小無定形區與結晶區之碎膜 被強光照射而使之進一步結晶。本發明之此一方法可以科 得具有良好柱狀網晶體結構且每個晶體顆粒均很小之結曰^ 矽膜。 相反地，在傳統方法中則是先以觸媒元素無定形石夕膜全 -8 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公董） 1235418 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（6 ) 部結晶，然後再以諸如雷射光之強光對之照射來改善已晶 化矽膜之晶性。但如上所述此一方法並無充份效果。 相較之下，按照本發明是以本發明之方法所形成之結晶 碎膜做爲薄膜電晶體之作用區顯示出較之以傳統方法所形 成薄膜電晶體之場效電子移動率改進二至三倍。其理由爲 何目前正在分析尚不知道。但目前之假定是：留下某種程 度之無定形區域而在強光照射時優先被熔解，此等熔解區 域在晶化時僅反射已晶化區域中之良好晶體成分。 本發明之方法與日本第jP-A-7_22i〇i7號專利中所述之方 法有下述各方面之不同。 第JP-A-7-221017號專利中所述之方法是無定形矽膜在加 入觸媒元素後即經過短時間之熱處理僅爲形成晶體核，然 後再以雷射光照射無定形矽膜促使其結晶。 本發明之方法則是使用觸媒元素來使無定形矽膜之大部 分結晶。亦即不但成核而且大部分區域首先藉觸媒元素之 助而結晶。結晶區域之比例爲極重要之因素，將在下文中 説明。本發明之方法與jp_A_7-221〇17號專利中所述方法之 最大不同處是在用雷射光照射前僅使用觸媒元素使之成 核。 本發明之另一方面提供一種製造半導體裝置之方法包括 下述步驟： 添加元素步驟_對具有絕緣表面之基體加上觸媒元素促 使無定形矽膜之晶化； 形成矽膜步驟-在已添加觸媒元素之基體上形成一無定 -9- 本紙張尺度適财®國家標準（CNS)A4規格（210 X 297公楚） 丨丨----------%! (請先閱讀背面之注意事項再填寫本頁) 訂_丨 線-蜂· 1235418 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（7 ) 形矽膜； 第一次晶化步驟·將無定形矽膜加以熱處理俾促使晶體 之生成，晶體之生成在尚存有微小無定形區域之狀態下停 止；及 弟一次晶化步驟-將在尚存有微小無定形區域狀態下已 停止晶體生成之無定形矽膜以強光照射促使其進一步晶 化。 八 明 在此一方法中並非將觸媒元素直接加至無定形矽膜而是 加至具有一絕緣膜之基體，然後在已加上觸媒元素之基體 上形成一無定形矽膜。此處所稱之「具有絕緣表面之基 體」係指直接在無定形矽膜下面之内層。在有了諸如基底 塗層之絕緣膜後’觸媒元素即加至此一絕緣膜。在此方法 中，觸媒元素是來自無定形矽膜下面之底層。即使如此， 此一方法仍有將觸媒元素直接加至無定形矽膜而有之類似 晶體生成。此外，若觸媒元素之添加是將觸媒元素溶入一 溶液中再以旋轉塗敷法添加，可有穩定之處理。此是因爲 當矽膜表面爲疏水性時，絕緣膜表面通常則有高度吸 性。 又 然後如將觸媒元素直接加至無定形矽膜之同樣情形，晶 體之生成在尚存有微小無定形區域（未結晶區）狀況下^ 止’接著即進行強光照射使其進一步晶化。 在本發明中，尚留存無定形矽區域之比例爲獲得高品質 與均勾晶體之一大因素。爲準確控制此一比例，最好是以 加至無定形矽膜表面或具有絕緣表面基體之觸媒元素量爲 -10- 本紙張尺度適ffl中國國家鮮（CNS)A4祕（21G X 297^7 —I —.-----β--------- (請先閱讀背面之注意事項再填寫本頁) 1235418 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（8 ) 準。亦即以增減無定形咬膜所含之觸媒元素量來控制在晶 體生成熱處理後尚留存微小無定形區（未結晶區）比例之增 減。重點是晶體生成並不以熱處理之時間爲準。即使熱處 理超過in A之時間，晶體生成也不會繼續進行。亦即以較 少量（觸媒7L素用於整個矽膜中之晶體生成，在晶體生成 進行到某一私度後，觸媒元素已被用完。因此即使延長時 晶體之生成也不會再進行。如此可在晶體生成後以穩 定方式及有良好複現性情形下來控制剩餘無定形區域之比 例而不受時間影響。此爲本發明之一項重點。再者，即使 在溫度上升或下降時剩餘無定形區域之比例不會受到基體 内溫度分佈之影響且經過第一次晶化步驟之矽膜於平面内 有極高之均句性。 特別是加至無定形矽膜表面或具有絕緣表面基體之觸媒 元素量之表面濃度最好爲1X 1〇12至1χ1〇13原子/平方公 分。若觸媒元素量少於lx 1〇12原子/平方公分則發生晶體 生成不足。若該量超過1 X 1〇U原子/平方公分，全部矽膜 將被觸媒元素晶化，尤其是矽膜之厚度爲2〇 11111至6〇 nm時 (此一範圍是根據薄膜電晶體内斷開電流所需之抑止而定） 即非常可能不會有剩餘之無定形區域。 在添加觸媒元素與經過熱處理後矽膜内剩餘無定形區域 之比例’亦即在一平面内無定形區域（未結晶區域）之面積 與整個矽膜之比最好爲1 0 %至5 0 %。也就是説在平面内結 晶區域面積之比例爲90_50%。這些値是發明人由實驗中獲 得。 又 -11 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 丨丨 %.! (請先閱讀背面之注意事項再填寫本頁) 11111 線！ 1235418 A7 B7: Attention of each inventor of the invention J plus 7L element step _ Add catalyst element to the footless hard film to benefit the crystallization of the film, the amorphous film is formed on the first crystallized Step-heat treatment of the amorphous silicon film to generate it: the generation of bulk and crystals is stopped while there is still a small amorphous area; the second crystallization step of the wire will be in a state where there is still a small amorphous area The amorphous silicon film whose crystal formation has been stopped is further illuminated by strong light. ^ Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. According to this method, the catalyst element is added to the amorphous silicon film and the amorphous is treated by heat treatment. The silicon film generates crystals. However, the heat treatment does not completely crystallize the amorphous silicon film. The generation of crystals is stopped while micro-amorphous regions (uncrystallized regions) still exist. This is a mixture of micro-amorphous regions and crystalline regions The broken film is irradiated with strong light to further crystallize it. This method of the present invention can obtain a silicon film with a good columnar network crystal structure and each crystal particle is very small. In contrast, in the conventional method in First, the catalyst element amorphous Shixian film is full -8-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public directors) 1235418 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 5. Description of the Invention (6) part of the crystal is then irradiated with strong light such as laser light to improve the crystallinity of the crystallized silicon film. However, this method as described above has no sufficient effect. In contrast, according to In the present invention, the crystalline chip formed by the method of the present invention is used as the active region of a thin film transistor, and the field-effect electron mobility of the thin film transistor formed by the conventional method is improved by two to three times. Why? It is unknown at the moment of analysis. But the current assumption is that a certain amount of amorphous regions are left and are preferentially melted when exposed to strong light. These melted regions reflect only good crystal components in the crystallized regions when crystallized. The method of the present invention is different from the method described in Japanese Patent No. jP-A-7_22i〇i7 in the following aspects. The method described in Japanese Patent No. JP-A-7-221017 is an amorphous silicon film After adding the catalyst element After a short period of heat treatment, only the crystal core is formed, and then the amorphous silicon film is irradiated with laser light to promote its crystallization. The method of the present invention is to use a catalyst element to crystallize most of the amorphous silicon film. And most of the regions are first crystallized with the help of catalyst elements. The proportion of the crystalline regions is a very important factor, which will be explained below. The method of the present invention is the biggest difference from the method described in the jp_A_7-221〇17 patent Before irradiating with laser light, only the catalyst element is used to nucleate it. Another aspect of the present invention provides a method for manufacturing a semiconductor device including the following steps: Adding element step_adding a catalyst element to a substrate having an insulating surface Promote the crystallization of amorphous silicon film; Step of forming silicon film-forming an amorphous on the substrate to which the catalyst element has been added-9-This paper is suitable for National Standards (CNS) A4 (210 X 297)丨 丨 ----------%! (Please read the notes on the back before filling out this page) Order_ 丨 line-bee · 1235418 Printed by A7 of the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 7) Shaped silicon film; the first crystallization step; heat treatment of the amorphous silicon film to promote the formation of crystals, the generation of crystals is stopped in the state where there are tiny amorphous regions; and the primary crystallization step-will The amorphous silicon film, which has stopped crystal formation in the state where there are tiny amorphous regions, is irradiated with strong light to promote its further crystallization. In this method, the catalyst element is not directly added to the amorphous silicon film but to a substrate having an insulating film, and then an amorphous silicon film is formed on the substrate to which the catalyst element has been added. The "substrate with an insulating surface" as referred to herein refers to an inner layer directly below the amorphous silicon film. After having an insulating film such as a base coat, a catalyst element is added to this insulating film. In this method, the catalyst element comes from the bottom layer below the amorphous silicon film. Even so, this method still adds the catalyst element directly to the amorphous silicon film with similar crystal formation. In addition, if the catalyst element is added by dissolving the catalyst element in a solution and then adding the catalyst element by a spin coating method, a stable treatment is possible. This is because when the surface of the silicon film is hydrophobic, the surface of the insulating film is usually highly absorbent. Then, if the catalyst element is directly added to the amorphous silicon film, the crystals are generated under the condition that there are still small amorphous regions (uncrystallized regions) ^ and then the light is irradiated to further crystallize. . In the present invention, the ratio of remaining amorphous silicon regions is a major factor in obtaining high-quality and uniform-hook crystals. In order to accurately control this ratio, it is best to use the amount of catalyst element added to the surface of the amorphous silicon film or the substrate with an insulating surface to be -10-. This paper is suitable for ffl China National Fresh (CNS) A4 Secret (21G X 297 ^ 7 —I —.----- β --------- (Please read the notes on the back before filling this page) 1235418 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (8) quasi. That is to increase or decrease the proportion of the catalyst element contained in the amorphous bite film to control the increase or decrease of the proportion of tiny amorphous regions (uncrystallized regions) remaining after the heat treatment of crystal formation. The point is that crystal formation does not The time of heat treatment shall prevail. Even if the heat treatment exceeds the time of in A, the crystal formation will not continue. That is, a smaller amount (catalyst 7L element is used for crystal formation in the entire silicon film. After a degree of privacy, the catalyst element has been used up. Therefore, the formation of crystals will not be performed even when extended. This can control the proportion of remaining amorphous regions in a stable manner and with good reproducibility after crystal formation. Without being affected by time. This is the invention An important point. Furthermore, even when the temperature rises or falls, the proportion of the remaining amorphous area is not affected by the temperature distribution in the substrate and the silicon film after the first crystallization step has a very high uniformity in the plane. In particular, the surface concentration of the amount of the catalyst element added to the surface of the amorphous silicon film or the substrate with an insulating surface is preferably 1 × 1012 to 1 × 1013 atoms / cm2. If the amount of the catalyst element is less than 1x1012 Atoms / cm 2 will cause insufficient crystal formation. If the amount exceeds 1 X 10 U atoms / cm 2, the entire silicon film will be crystallized by the catalyst element, especially when the thickness of the silicon film is 2011111 to 60nm. (This range is based on the suppression required to cut off the current in the thin film transistor.) That is, it is very likely that there will be no remaining amorphous area. The ratio of the catalyst element added to the remaining amorphous area in the silicon film after heat treatment 'That is, the ratio of the area of the amorphous region (uncrystallized region) in a plane to the entire silicon film is preferably 10% to 50%. That is to say, the ratio of the area of the crystalline region in the plane is 90_50%. These値 Yu Shi In obtaining and -11-- This paper scales applicable Chinese National Standard (CNS) A4 size (210 X 297 mm) Shushu% (please read the Notes on the back to fill out this page) 11111 line 1235418 A7 B7.!!

經濟部智慧財產局員工消費合作社印製 本發明之90-50%晶化矽膜與第Jp_A-7_221〇17專利中所述 僅有晶核之膜大不㈣。圖5所示本發明人所獲得之數二 爲上述比例數値之基礎。橫軸線表無定形區域面積之= 例，亦即在對無定形矽膜添加觸媒元素並作熱處理後（但 在強光照射前）無定形區域面積與整個矽膜面積之比。縱 軸線代表使用強光照射後矽膜做爲作用區之薄膜電晶體之 場效電子移動率。曾發現在大約1〇%與5〇%之比例做^界 限時’薄膜電晶體場效電子之移動率有很大改變。與無定 形區域面積比例爲0%時（亦即全部結晶狀態）以強光照射 相比較，在比例爲10_50〇/。以強光照射可有超出很多之場效 移動率。再者，當無定形區域面積之比例超過5〇%時，場 效電子移動率則又大爲變壞。在超過5〇%之範圍時，結晶 I矽膜内將包括僅由強光照射所獲之結晶狀態，於是造成 不平均之碎膜結晶狀態並降低移動率。無定形區域面積爲 百分之百（100%)係指完全爲無定形狀態。如上所述，在熱 處理後與強光照射前無定形矽區域與整個薄膜之面積比最 好爲 10-50%。 上述面積比若爲20-40%則更好。其理由是從圖5可看出 若面積比在此一範圍内實際上看不出場效移動有何不同且 仍可獲得最高之數値。此點顯示在添加觸媒元素及熱處理 後（強光照射前）無定形區域有輕微變化時不會引起特性變 化。所以上述之面積比被視爲可穩定維持高移動率之狀 況。 如前所述，在熱處理後（強光照射前）矽膜中無定形區域 ---.-----^------ (請先閲讀背面之注意事項再填寫本頁) 線—命· -12-Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The 90-50% crystallized silicon film of the present invention and the film with only crystal nucleus described in the Jp_A-7_221〇17 patent are not large. The number two obtained by the present inventor shown in FIG. 5 is the basis of the above-mentioned proportional number. The horizontal axis indicates the area of the amorphous region = for example, that is, the ratio of the area of the amorphous region to the area of the entire silicon film after the catalyst element is added to the amorphous silicon film and subjected to heat treatment (but before strong light irradiation). The vertical axis represents the field-effect electron mobility of a thin film transistor where the silicon film is used as the active area after intense light irradiation. It has been found that the mobility of thin-film transistor field-effect electrons is greatly changed at a time limit of about 10% to 50%. Compared with the case where the area ratio of the amorphous region is 0% (that is, the entire crystalline state) with strong light, the ratio is 10-50%. Illumination with strong light can have a lot of field effect mobility. Furthermore, when the proportion of the area of the amorphous region exceeds 50%, the field-effect electron mobility is greatly deteriorated. When it exceeds the range of 50%, the crystalline I silicon film will include a crystalline state obtained only by strong light irradiation, thus causing an uneven crystalline state of the broken film and reducing the mobility. An area of 100% amorphous (100%) means completely amorphous. As described above, the area ratio of the amorphous silicon region to the entire film after the heat treatment and before the strong light irradiation is preferably 10-50%. The above area ratio is better if it is 20-40%. The reason is that it can be seen from Fig. 5 that if the area ratio is within this range, no difference in field effect movement can be actually seen and the highest number can still be obtained. This point shows that there is no change in characteristics when the amorphous area is slightly changed after the addition of a catalyst element and heat treatment (before strong light irradiation). Therefore, the above-mentioned area ratio is regarded as a condition capable of stably maintaining a high mobility. As mentioned before, after the heat treatment (before the strong light irradiation), the amorphous area in the silicon film ---------- ^ ------ (Please read the precautions on the back before filling this page) —Life · -12-

本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 1235418This paper size applies to China National Standard (CNS) A4 (210 X 297 public love) 1235418

五、發明說明（1〇 ) 經濟部智慧財產局員工消費合作社印製 ，比例爲本發明之-個重要因素。除此之外，個別無定形 區域（未結晶區）之大小爲本發明之另一點。至此一階段碎 膜之狀態疋播定形區（未結晶區）與已結晶摻雜在一起。個 別剩餘操疋形區之大小對本發明之效果有很大影響。亦即 ，二在後來之強光照射晶化中不定形區會被優先熔融而此 等區域之晶化反映出已結晶區内之良好晶體成分，但在較 大 &lt; 剩餘無定形區域内，無定形區域在從已結晶區承襲良 好晶體成分前即使固化與晶化。結果使該等區域變成與僅 被強光照射而結晶之矽膜類似之狀態。因此若個別無定形 區域較大會使矽膜顯示在一平面内有較大之晶性擴散，其 邊界約爲5 μιη。在熱處理後（但在強光照射前）之此一矽膜 中播定形區域（未結晶區）與已結晶區相互摻雜，在一個實 例中個別無定形區之平面大小爲5 μπι或更小。若平面大小 在強光照射時並未大於5 μπι，無定形區之結晶狀態是在鄰 接操疋形區之結晶區中之良好晶性會被反映出來。「平面 大小」一詞若將剩餘無定形區比爲矩形或橢圓形時係指短 邊（短軸）方向之長度，若比爲圓形時則爲直徑。亦即無定 形區短邊長度之兩端被夾在已結晶區之間，此點其爲重 要。 如上所述，減小剩餘無定形區域之大小並將之均勻分配 在基體中頗爲重要。爲達到此一狀態，在結晶區内之個別 晶體顆粒在使用觸媒元素後加熱晶化時應爲小顆粒。在_ 個實例中’每個已結晶區均由多晶碎構成’其中個別晶體 顆粒之大小爲5 μιη或更小。若個別晶體顆粒之大小未超過 -13- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I ---.-----訂---------線国-^llr (請先閱讀背面之注意事項再填寫本頁) 1235418 五 、發明說明（n 經濟部智慧財產局員工消費合作社印製 5 μηι時，即可形成复 結晶區）。—般士之、'、不超過5叫1之個別無定形區（未 各有不同且顆粒邊界’二T體顆粒之排列與/或生成方向 素會成爲半導二:=:=些:：。此等因 定製造具有良好均白地A ^ 大原因。本發明旨在穩 求減少特性變化，使個=^見性之高品質半導體裳置。爲 產生〈特性變化即在可接受之範園内。 …所 馬能在整個基體表面釋定 :無定形區域亦爲5二成之有:^ ::下含有濃度約爲—之氫。採用二^ =斤示爲在早期時無定形矽膜中之氫濃度與使用觸媒 兀素、、、口晶石夕膜中顆粒大小間之關係，此一關係是由發明人 在實驗中得來。實驗中是以鎳做爲觸媒元素。在每個樣本 中鎳之濃度均調整至一數値(添加後之表面濃度均爲5 10原子/平方么刀）。但從圖6可看出當氫之濃度減至某 數値或更低時，顆粒之大小即會突然增大。顆粒突然增 之臨界値約爲3原子％。 圖7 A所π爲含氫濃度低於3原子％無定形矽膜熱處理 之表面顯微照相。可看出其中有大小超過3〇 μηι之超大 體顆粒。再者，每個剩餘無定形區域也都很大。圖7Β 示爲含氫濃度約爲1 〇原子％無定形矽膜熱處理之表面顯 照相。雖然圖7 Β相片之放大度數與圖7 a相同，但晶體 粒卻無法以顯微鏡來確定其大小。用透射電子顯微鏡 -14- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 項 iV. Description of the invention (10) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the proportion is an important factor of the invention. Besides, the size of individual amorphous regions (uncrystallized regions) is another aspect of the present invention. At this stage, the state of the broken film is that the shaped area (uncrystallized area) is doped with the crystal. The size of the individual residual operating regions has a great influence on the effect of the present invention. That is, the amorphous region will be preferentially melted in the subsequent strong light irradiation crystallization and the crystallization of these regions reflects the good crystalline composition in the crystalline region, but in the larger &lt; remaining amorphous region, Amorphous regions are solidified and crystallized before inheriting good crystalline components from the crystallized regions. As a result, these areas are brought into a state similar to a silicon film that is crystallized only by strong light. Therefore, if the individual amorphous area is larger, the silicon film will show a larger crystalline diffusion in a plane, and its boundary is about 5 μm. After heat treatment (but before strong light irradiation), the amorphous regions (uncrystallized regions) and the crystallized regions are doped with each other. In one example, the planar size of the individual amorphous regions is 5 μm or less. . If the plane size is not larger than 5 μm when exposed to strong light, the crystalline state of the amorphous region is reflected in the good crystallinity in the crystalline region adjacent to the manipulative region. The term “planar size” refers to the length in the direction of the short side (short axis) if the remaining amorphous area is rectangular or elliptical, and the diameter is the diameter if the ratio is circular. That is, both ends of the short side length of the amorphous region are sandwiched between the crystallized regions, which is important at this point. As mentioned above, it is important to reduce the size of the remaining amorphous area and distribute it evenly in the matrix. To achieve this state, individual crystal particles in the crystallization region should be small particles when heated and crystallized after using the catalyst element. In the _ examples, "each crystallized region is composed of polycrystalline fragments" in which the size of individual crystal particles is 5 µm or less. If the size of individual crystal particles does not exceed -13- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) I ---.----- Order --------- Line country-^ llr (Please read the notes on the back before filling out this page) 1235418 V. Description of the invention (n When the 5 μηι printed by the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, a recrystallization zone can be formed). —Principle, ', individual amorphous regions with no more than 5 to 1 (they are not different and the particle boundary is not the same; the arrangement and / or generation of the T-body particles will become semiconducting two: =: = some :: .These reasons are that manufacturing has a good uniformity. The present invention aims to stably reduce the change in characteristics and make high-quality semiconductors that are transparent. In order to produce changes in characteristics, it is within an acceptable range. ... Soma can be interpreted on the entire surface of the substrate: the amorphous area is also 50% of the following: ^ :: contains hydrogen at a concentration of about-. The use of two ^ = pounds is shown in the early amorphous silicon film The relationship between the hydrogen concentration and the particle size in the catalyst film, and the crystal size of the crystal, this relationship was obtained by the inventor in the experiment. In the experiment, nickel was used as the catalyst element. The concentration of nickel in each sample was adjusted to a few 値 (the surface concentration after addition was 5 10 atoms / square meter). However, it can be seen from Figure 6 that when the concentration of hydrogen is reduced to a certain 値 or lower, The size of the particles will suddenly increase. The critical threshold for the sudden increase of particles is about 3 atomic%. Figure 7 A indicates that the concentration of hydrogen is low. A photomicrograph of a 3 atomic% amorphous silicon film heat treated surface. It can be seen that there are ultra-large particles with a size exceeding 30 μηι. Moreover, each remaining amorphous region is also large. Figure 7B shows the hydrogen concentration Approximately 10 atomic% of the heat-treated surface of the amorphous silicon film is photographed. Although the magnification of the photograph in Figure 7B is the same as that in Figure 7a, the size of the crystal grains cannot be determined with a microscope. Transmission electron microscope-14 Paper size applies to China National Standard (CNS) A4 (210 X 297 mm) item i

X 大X Big

I 後 所 微 顆 去 1235418After I go to 1235418

五、發明說明（12 ) 經濟部智慧財產局員工消費合作社印製 看，顆粒炙大小約爲i至2 μιη。從圖6中之曲線亦可看出在 ，7 A與7 B中之晶體生成狀態爲完全不同之生成模式而不 ^僅反應出氫濃度之改變。二者之間轉換生成模式臨界以 氫&lt;濃度而T爲3至5原子％。當氫之濃度不超過此一臨界 値時，核之密度極小而從每一晶核生成之晶體很大，於是 J成圖7 A所示之大晶體顆粒。相較之下，當氫濃度超過 上述臨界値時，核之密度變高而從每個晶核生成之晶體則 小，因而形成圖7 B所示之微小晶體顆粒。在兩種情形 中核之达度隨所加觸媒元素濃度而改變，但此一改變均 在各自 &lt;模式内。以任何濃度之觸媒元素均可看出因氫之 濃度不同所造成晶體生成模式之明顯不同。 此一現象之機制目前仍不是十分暸解，下面之解釋雖僅 爲想像但或可對該機制予以説明。 亦即觸媒元素在無定形矽膜晶化前（在溫度上升中）已在 矽膜中以金屬狀態擴散。當觸媒元素已與無定形矽反應而 $成矽化物時，無定形矽膜發生結晶。若爲氫濃度低之無 疋形矽膜時，以晶核之產生來判斷，所添加觸媒元素之原 子會移動至無定形矽膜内聚集而散亂形成某種大小之原子 團促使叩化。於是這些原子團即成爲形成大晶體顆粒之 核。因此在不會有新核形成之相鄰核間幾乎不會有觸媒元 素出現。 相反地若無定形矽膜中含有大量氫時，氫被認爲會阻止 觸媒疋素之移動。於是所加之觸媒元素即會幫助晶化且仍 保持原來添加時之狀態。如此則有均勻分配之晶核。因每 -15- ------------—.-----訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適格⑽x 297公^ 1235418 A7V. Description of the invention (12) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the particle size is about i to 2 μm. It can also be seen from the curve in FIG. 6 that the crystal formation states in 7 A and 7 B are completely different generation modes without reflecting only the change in the hydrogen concentration. The conversion mode between the two is critical with hydrogen &lt; concentration and T is 3 to 5 atomic%. When the concentration of hydrogen does not exceed this critical threshold, the density of the nuclei is extremely small and the crystals generated from each crystal nuclei are large, so J becomes a large crystal particle as shown in Fig. 7A. In contrast, when the hydrogen concentration exceeds the above-mentioned critical threshold, the density of the nucleus becomes higher and the crystals generated from each nucleus become smaller, thereby forming fine crystal particles as shown in Fig. 7B. In both cases, the degree of nucleus changes with the concentration of the added catalyst element, but this change is within the respective &lt; mode. At any concentration of the catalyst element, it can be seen that the crystal generation mode is significantly different due to the different concentration of hydrogen. The mechanism of this phenomenon is not well understood at present, although the following explanation is only for imagination, it may be explained. That is, the catalyst element has diffused into the silicon film in a metallic state before the amorphous silicon film is crystallized (with increasing temperature). When the catalyst element has reacted with the amorphous silicon to form a silicide, the amorphous silicon film crystallizes. In the case of a non- 疋 -shaped silicon film with a low hydrogen concentration, judging by the generation of crystal nuclei, the atoms of the added catalyst element will move into the amorphous silicon film to aggregate and scatter to form atomic groups of a certain size to promote tritiation. These groups of atoms then become the nucleus of the large crystal particles. As a result, there are few catalyst elements between adjacent cores where no new cores will form. Conversely, if the amorphous silicon film contains a large amount of hydrogen, the hydrogen is considered to prevent the catalyst from moving. Therefore, the added catalyst element will help crystallize and maintain the original state. In this way, there are uniformly distributed nuclei. Because every -15- -------------.----- order --------- line (please read the precautions on the back before filling this page) Standard scale x 297 male ^ 1235418 A7

1 閱 讀 背 面 之 注 項 再 填龜 頁i 訂 a1 Read the notes on the back and fill in the turtle page i to order a

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1235418 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（14 ) 以固m相位生成結晶狀態所產生區域之混合區域。這種情 形當然會使半導體裝置性能不良且裝置與裝置特性之變化 極大。再者，若加熱之溫度更高，剩餘之無定形區域會充 滿自生結晶區而造成熱處理結束後全部表面均已晶化之狀 態。此一狀態芫全背離本發明所要求在晶體生成已停止後 留下無定形區域之特點。 第一次晶化步驟中熱處理之溫度最好設定在52〇·57(Γ(：範 圍内。此是因爲無定形矽膜因觸媒元素而開始生成晶體之 溫度是在大約520T：而無定形矽膜不使用觸媒元素自所生 成晶核之溫度是在約57(rc。後者可能會因無定形矽膜之 品質而受到很大影響，但以電漿化學汽相澱積法所獲本發 明無定形矽膜之加熱溫度上限也是大約爲上述之數値。 關於以強光照射之步驟（第二次晶化步驟），若此時光之 強度低，矽膜甚難熔融而使得剩餘之無定形區域内反映已 結晶區晶性晶體之生成不足。另一方面，若光之強度過 高，即會使因添加觸媒元素所獲結晶區内之晶性完全失去 (稱爲復置）。結果使得結晶矽膜之整個表面變成與僅以雷 射光又傳統式晶化所獲者類似。因此不但使性能減退而且 會有雷射光不均勻晶化之問題。所以照射光之強度非常重 要。照射光之強度應在使無定形區域能反映已結晶區而晶 化但不失去已結晶區原有晶性之範圍内。照射若超出上述 強度範圍’本發明之效力即會大受影響。 一種波長不超過4〇〇 nm之激勵雷射光最適合用做強光。 波長不超過400 nm之雷射光對矽膜而言有極高之吸收係 -17- ---·-----訂---------線— (請先閲讀背面之注意事項再填寫本頁) 木紙張尺度適用中國g家標準（CNS)A4規格（21〇 x 297公釐） 1235418 A7 B7 五、發明說明（15 ) 經濟部智慧財產局員工消費合作社印製 數，因此可僅對矽膜瞬間加熱而不會損傷玻璃基體。再 者，激勵雷射光之輸出功率大且適於處理大面積基體。一 種XeCl雷射光，其波長爲308 nm，最適合用於大量生產裝 置。這是因爲XeCl雷射之輸出功率大而照射基體時光束也 大，甚易配合大面積基體，且其輸出較爲穩定。所以波長 爲308 nm之XeCl雷射最適於大量生產裝置。 在一實例中，照射步驟之進行是使用在碎膜表面之表面 月色量金度爲200-450 mJ/cm2之雷射光。 若雷射光之表面能量密度小於2〇〇 mJ/cm2時，甚難使砍 膜熔融且在剩餘無定形區域内反應已結晶區域晶性之晶體 生長不會无分進行。另一方面，若雷射光之表面能量密度 大於450 MW時，因添加觸媒元素所獲結晶區内之晶性 即會完全失去（稱爲復置）。結果使得結晶砍膜之整個表面 變成與僅以雷射光之傳統式晶化所獲者類似。結果不#使 性能減退而且會有雷射光不均句晶化之問題。顯然上述 量密度之範SI應爲能使無定龍域有反應已結晶區内晶 之晶化且不失去已結晶區内原有之晶性。 在本發明中可用爲觸媒之元素有鎳m、綱 銀、金、銦、錫、IS、銻等。從其中選出_種或多種元 即可發揮促使晶化之效果，即使是微量之效果。 鎳所獲之效果最大。茲假定其理由如下：觸媒元素並二 獨互起作用但與⑦結合切化後即會對晶體之生二 用。此時晶體結構之作用如同無定料膜晶化時之 板，因而促使無定料膜之晶化。—個鎳原予與兩個發原 月匕 性 素 用 會 ---------訂---------線—Ijnlr (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規 -18- 1235418 A7 B7 五、發明說明（16 ) 子即形成一種矽化物（NiSD。此一矽化物NiSi2顯示_種螢 石·類型之晶體結構而此一晶體結構與單晶矽之鑽石結構極 相似。再者，NiSL有5.406又之晶格常數，非常接近單晶矽 鑽石結構夂晶格常數5.430又。因此矽化物NiSi2爲使無定形 矽膜晶化之最佳模板。在本發明中所用之觸媒元素以鎳爲 最適合。 經濟部智慧財產局員工消費合作社印製 本發明之一個顯著特徵在於使用觸媒元素進行無定形矽 膜之晶化。即使其劑量並不多，但在半導體膜内出現此種 金屬元素之本身即非好事。所以本發明製造半導體裝眞之 万法進一步包括在利用觸媒元素進行無定形矽膜之晶化處 理後並進行使觸媒元素移動之步驟促使矽膜中所留存觸媒 元素之大部分原子移至半導體裝置作用區（波道區）以外之 區域。下述使觸媒元素原子移動之方法甚爲有效。亦即在 使典疋形矽膜晶化後，矽膜中除將要形成半導體裝置區域 以外之區域均摻雜以磷離子，然後以大約6〇〇Ό之溫度進 行熱處理。如此做會使至少是以矽化物形式出現之觸媒元 素（例如鎳）之原子移至摻雜有磷之區域。隨後在形成半導 體裝置時將此等區域移除。此一方法雖無法全部除去擴散 於矽中 &lt; 觸媒7C素原子，但可將矽膜中觸媒元素之濃度大 爲降低至固各之限度。不過上述之觸媒元素移動步驟應在 以強光，、、、射矽膜後進行。其理由如下：若此一步驟在以強 光照射矽膜前進行時，在本步驟中之熱處 理會使矽膜被並 非因觸媒元素之效果所獲之晶核而是被自生之晶核全部晶 化。結果本發明在尚有剩餘無定形區域狀態下進行強光照 -19 - 本紙張尺度·國^票準χ 297公ir 1235418 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（17 ) 射之特性即被消除。 本發明之其他目的、特性與優點將在後文中説明。 附圖之簡要説明 從下文中之詳細説明與附圖會對本發明有更充份之瞭 解’附圖僅爲舉例性質並非對本發明有何侷限： 圖1 A、1 B、1 C、ϊ D、i E均爲計劃圖依序示出本發明 製造半導體裝置方法第一實例中之各製造步驟； 圖2A、2B、2C、2D、2E、2F爲斷面圖依序示出本發 明第一實例之製造步驟； 圖3爲計劃圖示出本發明第二實例製造半導體裝置方法 之圖解； 圖4八、43、4(：、40、4丑、4卩爲斷面圖依序示出本發 明第二實例之製造步驟； 圖5爲特性曲線圖示出剩餘無定形區域之比例與薄膜電 晶體中場效電子移動率間之關係； 圖6爲特性曲線圖示出無定形矽膜（a_si)中氫之濃度與結 晶碎顆粒大小間之關係；及 圖7 A爲比較樣本矽膜表面之顯微照相，圖7 B爲本發明 矽膜表面之相片。 較佳實例之詳細説明 第一實例 現在對本發明製造半導體裝置方法之第一實例加以説 明。在第一實例中，本發明是用於在一玻璃基體上製造N 型薄膜電晶體之過程中。本實例中製造之薄膜電晶體不但 • ---·-----訂------ (請先閱讀背面之注意事項再填寫本頁) 線！ -20-1235418 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 V. Description of the invention (14) A mixed region in which the crystalline state is generated with a solid phase. This situation, of course, leads to poor performance of the semiconductor device and great changes in device and device characteristics. In addition, if the heating temperature is higher, the remaining amorphous area will be filled with spontaneous crystalline areas, resulting in a state where the entire surface has crystallized after the heat treatment is completed. This state completely deviates from the characteristic of the present invention that an amorphous region is left after the generation of crystals has stopped. The temperature of the heat treatment in the first crystallization step is preferably set to 52 ° 57 (Γ (: range. This is because the temperature at which the amorphous silicon film starts to form crystals due to the catalyst element is about 520T: and the amorphous The temperature of the silicon film without the use of a catalyst element is about 57 (rc. The latter may be greatly affected by the quality of the amorphous silicon film, but the cost obtained by plasma chemical vapor deposition method The upper limit of the heating temperature of the invented amorphous silicon film is also about the above-mentioned number. Regarding the step of irradiating with strong light (second crystallization step), if the intensity of light is low at this time, the silicon film is difficult to melt and the remaining The formation of crystalline crystals in the crystalline region reflects insufficient generation of crystals. On the other hand, if the intensity of light is too high, the crystallinity in the crystalline region obtained by adding the catalyst element is completely lost (called resetting). As a result, the entire surface of the crystalline silicon film becomes similar to that obtained by only laser light and traditional crystallization. Therefore, not only the performance is degraded, but also the problem of uneven crystallization of the laser light is caused. Therefore, the intensity of the irradiation light is very important. Light strength It should be within a range that enables the amorphous region to reflect and crystallize the crystallized region without losing the original crystallinity of the crystallized region. If the irradiation exceeds the above intensity range, the effectiveness of the present invention will be greatly affected. One wavelength does not exceed 4 〇〇nm excitation laser light is most suitable for use as strong light. Laser light with a wavelength not exceeding 400 nm has a very high absorption system for silicon films. ---- Line — (Please read the notes on the back before filling in this page) The paper size is applicable to China Standard (CNS) A4 (21〇x 297 mm) 1235418 A7 B7 V. Description of the invention (15) Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs have printed the number of consumer cooperatives, so they can only heat the silicon film instantaneously without damaging the glass substrate. In addition, the output power of the excitation laser light is large and suitable for processing large-area substrates. Its wavelength is 308 nm, which is most suitable for large-scale production equipment. This is because the output power of XeCl laser is large and the beam is large when irradiating the substrate. It is easy to cooperate with a large area substrate and its output is stable. Therefore, the wavelength is 308 nm XeCl laser is most suitable for mass production In an example, the irradiation step is performed using laser light with a luminous amount of 200-450 mJ / cm2 on the surface of the broken film surface. If the surface energy density of the laser light is less than 200 mJ / cm2, It is very difficult to melt the chopped film and react to the crystal growth of the crystalline region in the remaining amorphous region. Crystal growth will not proceed indiscriminately. On the other hand, if the surface energy density of the laser light is greater than 450 MW, it is caused by the addition of a catalyst The crystallinity in the crystallization region is completely lost (called resetting). As a result, the entire surface of the crystalline film is similar to that obtained by traditional crystallization using only laser light. The result does not degrade performance and will There is a problem of crystallization of laser light unevenness. Obviously, the range SI of the above-mentioned density should be the crystallization of the amorphous region in the amorphous dragon region without losing the original crystallinity in the crystallized region. Elements usable as catalysts in the present invention include nickel m, gang silver, gold, indium, tin, IS, antimony, and the like. Selecting one or more kinds from them can exert the effect of promoting crystallization, even a small amount of effect. Nickel has the greatest effect. It is assumed that the reason is as follows: the catalyst element does not interact with each other, but it will be used for the second life of the crystal after it is cut with plutonium. At this time, the crystal structure functions as a plate when the amorphous film is crystallized, thereby promoting the crystallization of the amorphous film. —One Ni Yuan Yu and Two Hair Primitives --------- Order --------- Line—Ijnlr (Please read the precautions on the back before filling this page ) This paper size is in accordance with Chinese National Standard (CNS) A4 regulations-18-1235418 A7 B7 V. Description of the invention (16) A silicide is formed (NiSD. This silicide NiSi2 shows _ a kind of fluorite · type crystal structure This crystal structure is very similar to the diamond structure of single crystal silicon. In addition, NiSL has a lattice constant of 5.406, which is very close to the single crystal silicon diamond structure. The lattice constant is 5.430 again. Therefore, silicide NiSi2 is used to make amorphous silicon. The best template for film crystallization. Nickel is the most suitable catalyst element used in the present invention. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, a significant feature of the present invention is the use of catalyst elements for amorphous silicon films. Crystallization. Even if its dosage is not large, it is not a good thing to have such a metal element in the semiconductor film itself. Therefore, the method for manufacturing semiconductor devices of the present invention further includes crystallization of an amorphous silicon film by using a catalyst element. After processing and making catalyst element The step of moving the element causes most of the atoms of the catalyst element remaining in the silicon film to move to a region outside the active region (channel region) of the semiconductor device. The following method of moving the catalyst element atom is very effective. After the crystalline silicon film is crystallized, all regions of the silicon film except the region where the semiconductor device is to be formed are doped with phosphorus ions, and then heat-treated at a temperature of about 600 ° F. This will at least be in the form of a silicide. The atoms of the appearing catalyst element (such as nickel) are moved to the region doped with phosphorus. These regions are subsequently removed when the semiconductor device is formed. Although this method cannot completely remove the diffusion in the silicon &lt; catalyst 7C element Atom, but the concentration of the catalyst element in the silicon film can be greatly reduced to the limit of the solid. However, the above-mentioned step of moving the catalyst element should be performed after the silicon film is shot with strong light. The reasons are as follows: When this step is performed before the silicon film is irradiated with strong light, the heat treatment in this step will crystallize the silicon film not by the crystal nuclei obtained by the effect of the catalyst element but by the spontaneous crystal nuclei. invention Strong light in the state of the remaining amorphous area-19-Paper size · National standard 297 public ir 1235418 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of invention (17) Radiation characteristics That is, other objects, characteristics and advantages of the present invention will be described later. Brief description of the drawings The detailed description and drawings below will make the present invention more fully understood. What are the limitations of the present invention: FIGS. 1 A, 1 B, 1 C, ϊ D, i E are plan diagrams sequentially showing the manufacturing steps in the first example of the method for manufacturing a semiconductor device according to the present invention; FIGS. 2A, 2B, 2C , 2D, 2E, 2F are sectional views sequentially showing the manufacturing steps of the first example of the present invention; FIG. 3 is a plan view showing a method of manufacturing a semiconductor device according to the second example of the present invention; :, 40, 4 and 4 are sectional views sequentially showing the manufacturing steps of the second example of the present invention; FIG. 5 is a characteristic curve diagram showing the proportion of the remaining amorphous region and the field-effect electron mobility in the thin film transistor Relationship between them; Figure 6 shows the characteristic curve Figure 7 shows the relationship between the hydrogen concentration in the amorphous silicon film (a_si) and the size of the crystalline particles; and Figure 7 A is a photomicrograph of the surface of a comparative sample silicon film, and Figure 7B is a photo of the silicon film surface of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT First Example A first example of a method for manufacturing a semiconductor device according to the present invention will now be described. In a first example, the present invention is used in the process of manufacturing an N-type thin film transistor on a glass substrate. The thin-film transistor manufactured in this example not only • --- · ----- Order ------ (Please read the precautions on the back before filling this page) Wire! -20-

1235418 經濟部智慧財產局員工消費合作社印製 A7 _—- B7 五、發明說明（18 ) 可用於驅動電路及活性矩睐刑凃曰 丨王祀丨早空履晶顯不裝置之圖元並且可 y故薄膜積體電路構成之元件。在本實射具有代表性者 疋用於液晶顯示裝置之活性矩陣基體上之圖元驅動薄膜電 晶體特別需要數十萬至數百萬個製造—致之N型薄膜電晶 體。 第一實例中在活性矩陣基體上製造圖元薄膜電晶體之計 劃依照製造步驟如圖1A、1B、lc、1D、1E所示。實際 上活性矩陣基體至少有數十萬個薄膜電晶體，但在圖1 1E中僅簡單顯示三排四行共十二個薄膜電晶體。 圖2 A、2 B、2 C、2 D、2 E、2 F按照製造步驟之順序顯 不出每一步騍中圖1A_1E*所示一個薄膜電晶體之斷面 圖。 首先，如圖2A所示在一玻璃基體101上以濺射法（舉例） 形成厚度約爲300-500 nm之氧化矽底膜1 〇2。氧化矽所製 之底膜1 0 2是防止雜質從玻璃基體丨0 1擴散。接著以電漿 化學汽相澱積法形成一厚度爲20-60 nm，例如30 nm，之原 質（I型）無定形矽（a-Si)膜103。此時對基體加熱之溫度最 好不要超過400°C。在此一實例中是將溫度定在3〇〇°c。同 時以平行板電漿化學汽相澱積系統做爲化學汽相澱積系統 並以甲矽烷（SiH4)及氫（H2)氣體做爲來源氣體。射頻功率 之舍度没定在10與10 mW/cm2之間（例如80 mW/cm2)，此 爲較低之密度’此時之殿積率設定在大約5 〇 nm/分鐘。如 此所獲在無定形矽膜103中之氫濃度爲10-15原子％。 接下來在碎膜1 〇 3之表面添加微量之鎳1 0 4。在此例中 -21 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---.-----^--------- (請先閱讀背面之注意事項再填寫本頁) 1235418 A7 B7 五、發明說明（彳9 ) 添加微量鎳1 0 4之方法是在矽膜]〇 3上保持一種其中溶有 鎳之溶液並將此溶液以旋轉器均勻塗在基體1〇1上然後使 之變乾。在第一實例中以鎳醋酸做爲溶質而以乙醇做爲溶 劑。落液中鎳之濃度調整至i ppm。以χ光螢光總反射分析 法測量珍膜中所加鎳之濃度發現大約爲5 χ 1 〇 12原子/平方 公分。然後將結果之基體在一惰性氣壓（例如氮氣）下加以 熱處理。在熱處理中首先進行脱氫處理而在溫度上升時使 虱從石夕膜1 0 3分離’然後在已提升之溫度中進行碎膜1 〇 3 之曰曰化。熱處理之第一步驟是在45〇-520°C之溫度範圍内 進行一至二小時之退火。其第二步驟是在52〇巧7〇ό之溫 度範圍内進行二至八小之退火。在第一實例中在以5〇(rc 進行一小時之熱處理後又在550。(：進行四小時之熱處理。 在熱處理中即發生加至矽膜丨〇 3表面鎳之矽化。然後石夕膜 1 0 3以矽化之鎳做爲晶核而結晶。 但因觸媒元素之量並不足以使矽膜完全結晶，晶體之生 成在某一點上即停止。在溫度低於57(^c時矽膜不會有自 生晶體之情形，因此矽膜在晶體之生成尚未到達之未結晶 區仍保持爲無定形。結果在經過四小時55〇aC熱處理所獲 之矽膜中是摻雜有無定形區域與已結晶區之狀態。亦即如 圖7 B中所示之狀態。無定形區與整個矽膜之面積比約爲 3 0%。再者，每一無定形區之大小，最大爲2 μιη。同時已 結晶區中每個晶體顆粒之平均大小約爲K1.5 ， 如圖2 Β所示矽膜1 〇 3以雷射光丨〇 5照射改進一步晶化而 獲得結晶矽膜1 03 a。此時是以xec 1激勵雷射（其波長爲 -22 本紙張尺度適用中國國家標準（CNS)h規格⑵Q χ撕公爱） 請 先 閲 讀 背 面 之 注 項 再 填 寫 本 頁 經濟部智慧財產局員工消費合作社印製 1235418 A71235418 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _—- B7 V. Description of the invention (18) Can be used to drive circuits and active moments. Thin film integrated circuit components. In this real shot, a pixel-driven thin-film transistor on an active matrix substrate for a liquid crystal display device requires hundreds of thousands to millions of fabrication-specific N-type thin-film transistors. The plan for manufacturing the element thin film transistor on the active matrix substrate in the first example is shown in Figs. 1A, 1B, lc, 1D, and 1E according to the manufacturing steps. Actually, there are at least hundreds of thousands of thin film transistors in the active matrix matrix, but only a total of twelve thin film transistors in three rows and four rows are shown in FIG. 1E. Fig. 2 A, 2 B, 2 C, 2 D, 2 E, and 2 F do not show each step in the order of the manufacturing steps. A sectional view of a thin film transistor shown in Figs. 1A_1E * in Fig. 1A. First, as shown in FIG. 2A, a silicon oxide base film 102 is formed on a glass substrate 101 by sputtering (for example) to a thickness of about 300-500 nm. The base film 1 0 2 made of silicon oxide prevents impurities from diffusing from the glass substrate 0 1. A plasma chemical vapor deposition method is then used to form a primary (type I) amorphous silicon (a-Si) film 103 having a thickness of 20-60 nm, such as 30 nm. At this time, the temperature of heating the substrate should not exceed 400 ° C. In this example, the temperature was set at 300 ° C. At the same time, a parallel plate plasma chemical vapor deposition system was used as the chemical vapor deposition system, and silane (SiH4) and hydrogen (H2) gases were used as source gases. The radio frequency power is not set between 10 and 10 mW / cm2 (for example, 80 mW / cm2), which is a lower density. At this time, the area ratio is set at about 50 nm / minute. The thus obtained hydrogen concentration in the amorphous silicon film 103 is 10-15 atomic%. Next, a small amount of nickel 104 was added to the surface of the broken film 103. In this example -21-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ---.----- ^ --------- (Please read the back first Note: Please fill in this page again) 1235418 A7 B7 V. Description of the invention (彳 9) The method for adding trace nickel 1 0 4 is to keep a solution in which nickel is dissolved on the silicon film] and use this solution on a spinner. Apply uniformly to the substrate 101 and then dry it. In the first example, nickel acetic acid was used as the solute and ethanol was used as the solvent. The concentration of nickel in the falling liquid was adjusted to i ppm. The x-ray fluorescence total reflection analysis method was used to measure the concentration of nickel added to the rare earth film and found to be about 5 x 1012 atoms / cm2. The resulting substrate is then heat treated under an inert gas pressure (e.g. nitrogen). In the heat treatment, a dehydrogenation treatment is performed first, and the lice are separated from the Shi Xi membrane 103 when the temperature rises, and then the membrane is broken down at a raised temperature. The first step of heat treatment is annealing at a temperature range of 45-520 ° C for one to two hours. The second step is to anneal for two to eight hours in a temperature range of 5280 ° 7 °. In the first example, one hour of heat treatment was performed at 50 ° C and then at 550. (: Four hours of heat treatment. During the heat treatment, silicidation of nickel added to the surface of the silicon film 〇03. Then Shi Xi film 1 0 3 Crystallized with silicified nickel as the nucleus. However, the amount of the catalyst element is not sufficient to completely crystallize the silicon film, and the generation of the crystal stops at a certain point. When the temperature is lower than 57 ° C, the silicon The film does not have spontaneous crystals, so the silicon film remains amorphous in the uncrystallized regions where the crystal formation has not yet reached. As a result, the silicon film obtained after 4 hours of heat treatment at 55aC is doped with amorphous regions and The state of the crystalline region. That is, the state shown in FIG. 7B. The area ratio of the amorphous region to the entire silicon film is about 30%. Furthermore, the size of each amorphous region is a maximum of 2 μm. At the same time, the average size of each crystal particle in the crystallized area is about K1.5, as shown in Figure 2B, the silicon film 10 is irradiated with laser light 05 and further crystallized to obtain a crystalline silicon film 1 03a. The laser is excited by xec 1 (the wavelength is -22) Standard (CNS) h Specifications ⑵Q χ tear Kimiyoshi) please first read the note on the back of the entry read again fill this page Ministry of Economic Affairs Intellectual Property Office employees consumer cooperatives printed 1235418 A7

五、發明說明（2〇 ) 經濟部智慧財產局員工消費合作社印製 308 nm，脈衝寬度爲40 nsec)做爲雷射光。雷射光照射條件 如下：照射時基體被加熱至200_450°C (本例中爲400°C )然 後以200-450 mJ/cm2(本例中爲350 mJ/cm2)之能量密度照 射。雷射之設計是使其在基體1〇1表面上光束之大小爲 150 mm X 1 mm之伸長形狀。在與雷射光束縱向垂直之方 向以0.05 mm之步進寬度進行掃描。亦即矽膜1〇3上之一 個選擇點總共被雷射光照射2 0次。藉雷射之照射，尚留存 在矽膜中之無定形區被優先熔融並結晶且僅反映已結晶區 中之良好晶體成分，於是整個矽膜即被晶化。 如圖2 C所示在結晶矽膜l〇3a上澱積一層氧化矽或氮化砍 之絕緣薄膜，然後以圖案形成蔽罩1 〇 6。在第一實例中是 以氧化矽做爲蔽罩1 〇 6。同時以TEOS做爲來源氣體。以氧 將TEOS分解並以射頻電漿化學汽相澱積法予以殿積。蔽 罩106之厚度最好爲100-400 nm。在本例中氧化珍膜之厚 度是定爲150 nm。從上面可看出此時基體之狀態是結晶石夕 膜103a之一些部分被島狀蔽罩圖案1〇6所掩蓋。 在圖2C所tf狀下’在基體101之整個表面上從上面進 行磷1 0 7離子之摻雜。磷1 〇 7之摻雜條件如下·· 5-10 kV之 加速電壓與5X1015 - lx l〇16cm-2之劑量。藉此一步驟將磷 植入結晶碎膜103a之曝露區域，於是即形成摻有鱗之結晶 矽區域103b。另一方面，被蔽罩1〇6掩蓋之區域則未換入 磷。從上面可看出此時之基體即爲圖1 A示之狀態。圖i B 顯示出下一步驟，未來之薄膜電晶體作用區是以虛線表示 以便清將來各種薄膜電晶體作用區、被蔽罩1 〇 6所掩蓋區 -23- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------訂---------^ — (請先閱讀背面之注意事項再填寫本頁) 1235418V. Description of the invention (20) The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed 308 nm (with a pulse width of 40 nsec) as the laser light. The laser light irradiation conditions are as follows: the substrate is heated to 200-450 ° C (400 ° C in this example) and then irradiated with an energy density of 200-450 mJ / cm2 (350 mJ / cm2 in this example). The laser is designed so that the size of the beam on the surface of the substrate 101 is an elongated shape of 150 mm X 1 mm. Scan in a step width of 0.05 mm in a direction perpendicular to the longitudinal direction of the laser beam. That is, one selected point on the silicon film 103 is irradiated with laser light 20 times in total. By laser irradiation, the amorphous regions remaining in the silicon film are preferentially melted and crystallized and reflect only the good crystalline components in the crystallized regions, so the entire silicon film is crystallized. As shown in FIG. 2C, an insulating film of silicon oxide or nitride is deposited on the crystalline silicon film 103a, and then a mask 106 is formed in a pattern. In the first example, silicon oxide is used as the mask 106. At the same time, TEOS was used as the source gas. TEOS is decomposed with oxygen and deposited by radio frequency plasma chemical vapor deposition. The thickness of the mask 106 is preferably 100-400 nm. The thickness of the oxide film is set to 150 nm in this example. It can be seen from the above that the state of the substrate at this time is that part of the crystalline stone film 103a is masked by the island-like mask pattern 106. In the state tf shown in FIG. 2C, doping of phosphorus 107 ions is performed from above on the entire surface of the substrate 101. The doping conditions of phosphorus 107 are as follows: an acceleration voltage of 5-10 kV and a dose of 5X1015-lx1016cm-2. In this step, phosphorus is implanted into the exposed area of the crystalline shatter film 103a, and a crystalline silicon area 103b doped with scale is formed. On the other hand, the area covered by the mask 106 was not replaced with phosphorus. It can be seen from the above that the substrate at this time is the state shown in FIG. 1A. Figure IB shows the next step. The future thin film transistor active area is indicated by a dotted line in order to clarify the future of various thin film transistor active areas and the area covered by the mask 106. -23- This paper size applies Chinese national standards ( CNS) A4 specification (210 X 297 mm) -------- Order --------- ^ — (Please read the notes on the back before filling this page) 1235418

五、發明說明（a ) 經濟部智慧財產局員工消費合作社印製 t植入磷之區域103b間之關係位置。以後將要形成薄膜電 曰曰體作用區之結晶矽膜i 0 8部份在此一階段完全被蔽罩 1 0 6所掩盍。在圖i A、i B與2 c中劃斜線之部分即顯示摻 入磷之區域13〇b。 在此狀怨下之矽膜在一種惰性氣壓（例如氮氣）下以58〇_ 650°C之溫度進行數小時至數十小時之熱處理。在第一實 例中 &lt; 熱處理是以600 °C進行十二個小時。在此一熱處理 中’結晶矽膜l〇3b中之磷會吸引擴散在結晶矽膜1〇3&amp;中之 鎳。因此在結晶矽膜103a被掩蓋區内鎳之濃度大爲降低。 結晶石夕膜103a被掩蓋區内實際之鎳濃度是按照二次離子質 量分光法加以測量。測量結果顯示鎳濃度降至大約5 X 1〇6 原子/立方公分。熱處理前結晶矽膜1〇3&amp;中之鎳濃度爲大 約5 X 1〇7 - 1 X 1018原子/立方公分。 接下去以浸蝕法將氧化矽膜製成之蔽罩丨〇 6除去。以對 秒膜1 〇 3有充份選擇性之！ ： 1 〇緩衝氫氟酸做爲浸蝕劑並 以濕浸蝕法進行除去工作。 隨後爲半導體裝置之隔離而除去矽膜1〇3a之不必要部 分。亦即使用至少一部分矽膜1〇3a被掩蔽之區域以圖1 B 所示之方式形成每個均成爲薄膜電晶體作用區（源極/汲極 區及波道區）之島狀結晶膜1〇8。於是即有了圖ic與2D所 示狀態之基體。 接下來如圖2 E所示形成一厚度爲20- 1 50 nm(此處爲 100 nm)之氧化矽膜做爲閘絕緣膜丨〇9而蓋住將成爲作用區 之結晶矽膜1 〇 8。使用TEOS做爲源而與氧分解並在基體溫 -24- 本紐尺度適用中國國家標準（CNS)A4規格（210 X 297公爱) &quot;'— - -1^-------------------^---------^ — ----------------------- (請先閱讀背面之注意事項再填寫本頁) 1235418V. Description of the invention (a) Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the position of the relationship between the regions 103b where the phosphorus is implanted. A portion of the crystalline silicon film i 0 8 that will form a thin film electrical region in the future is completely masked by the mask 106 at this stage. The oblique lines in Figs. I A, i B, and 2 c show the region 13b where phosphorus is doped. Under this condition, the silicon film is heat-treated for several hours to several tens of hours at a temperature of 58-650 ° C under an inert gas pressure (such as nitrogen). In the first example, the heat treatment was performed at 600 ° C for twelve hours. In this heat treatment, phosphorus in the 'crystalline silicon film 103b will attract nickel diffused in the crystalline silicon film 103 &amp;. Therefore, the concentration of nickel in the masked area of the crystalline silicon film 103a is greatly reduced. The actual nickel concentration in the masked area of the crystal stone film 103a is measured according to the secondary ion mass spectrometry. The measurement results showed that the nickel concentration dropped to about 5 X 106 atoms / cm3. The nickel concentration in the crystalline silicon film 103 & before the heat treatment was about 5 X 107-1 X 1018 atoms / cm3. Next, a mask made of a silicon oxide film is removed by an etching method. With full selectivity to the second film 103! : 10 Buffered hydrofluoric acid was used as an etchant and removed by a wet etching method. Unnecessary portions of the silicon film 103a are subsequently removed for isolation of the semiconductor device. That is, at least a part of the area covered by the silicon film 103a is used to form island-shaped crystal films 1 each of which becomes a thin film transistor active region (source / drain region and channel region) in the manner shown in FIG. 1B. 〇8. Then there is the matrix of the state shown in Figure ic and 2D. Next, as shown in FIG. 2E, a silicon oxide film with a thickness of 20 to 1 50 nm (here, 100 nm) is formed as a gate insulating film, and the crystalline silicon film covering the active region is covered. . Use TEOS as a source to decompose with oxygen and at the substrate temperature -24- This standard applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love) &quot; '---1 ^ ------- ------------ ^ --------- ^ — ----------------------- (please first (Read the notes on the back and fill out this page) 1235418

五、發明說明（22 )V. Description of the invention (22)

^爲1 50-600°C時（最好爲300-45(rc )以射頻電漿化學汽相 凝積法加以澱積而形成上述之氧化矽膜。上述之源te〇s 可與臭氧連同使用而在與臭氧分解後以低壓化學汽相澱積 法（亦可用大氣壓力化學汽相澱積法）在基體溫度爲35〇、_ 6〇〇 C (最好是400-550°C )進行澱積而形成上述之氧化矽 膜。爲改善閘絕緣膜109本身之整體特性及結晶矽膜與閘 絕緣膜間之介面特性，在惰性氣壓下以4〇〇_6〇〇Ό之溫度 進行退火一至四小時。 隨後以濺射法澱積一厚度爲400至8〇〇 nm，在此爲6〇〇 nm， 之鋁膜。將鋁膜製成圖案而形成閘電極n〇。進一步將鋁 電極之表面陽極化而形成氧化層U1。此一狀態對應於圖 2E所示之情形。閘電極110與閘滙流排線路係以同一層構 成。圖1D所示爲此一狀態之計劃圖。陽極氧化是在含有^ 5%酒石酸之乙烯乙二醇溶液中進行。首先將電壓升高至 220V而保持電流不變。在陽極氧化結束前基體被置於此一 狀態一個小時。最後所獲氧化層lu之厚度爲2〇〇nm。氧 化層1 1 1之厚度對應於將在後來之離子摻雜步驟中形成之 補償閘區。所以補償閘區之長度可在陽極氧化步驟中確 定。 經濟部智慧財產局員工消費合作社印製 接著以閘電極no與閘電極周圍之氧化層ηι做爲蔽罩 而以離子摻雜法將雜質（磷）摻入作用區。使用磷化氫（PA) 做爲摻雜氣體，加速電壓定在60至90kv(例如8〇kv)，^ 量則足爲 1 X 1〇15 - 8X 1015cm-2(例如 2 x 1〇15cm_2)。在本步 驟中換有雜質之區域U3與114後來將成爲薄膜電晶體之 -25- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚） 經濟部智慧財產局員工消費合作社印製 1235418 A7 ----R7 _ 五、發明說明（23 ) 源極與汲極區。被閘電極丨丨〇與閘電極周圍氧化層i丨丨遮 蔽而未植入雜質之區域1 1 2後來將成爲薄膜電晶體之波道 區。 隨後如圖2 E所示以雷射光丨丨5照射而進行退火俾活化以 離子植入法摻進之雜質並改善摻入雜質步驟中被損壞部分 之晶性。使用XeCl激勵雷射（其波長爲3〇8 nm，脈衝寬度 爲40 nsec)，照射之能量密度爲15〇_4〇〇 mJ/cm2，最好爲 200-250 mJ/cm2。如此所形成N型雜質（磷）區域113、114 之薄膜電阻爲200-800Ω/0。 然後如圖2F所示形成一厚度爲大約6〇〇 nm之氧化矽膜 (或氮化碎膜）做爲層間絕緣膜116。當使用TE〇s做爲源及 氧而以電漿化學汽相澱積法或使用Te〇s及臭氧而以低壓 化學汽相澱積法（或大氣壓力化學汽相澱積法）形成一氧化 矽膜，如此形成之層間絕緣膜丨16將極佳。另一種情形是 使用Sih及ΝΑ做爲源氣體而以電漿化學汀相澱積=形: 一氮化矽膜，氫原子可被饋入作甩區與閘絕緣膜間I介 面。如此可減少降低薄膜電晶體特性之不成對搭接。 ) 接下去在層間絕緣膜116形成接觸孔而以金屬材料（例如 氮化鈥與銘所製之雙層膜）形成薄膜電晶體源極之接 117。氧化鈦膜爲一阻隔膜用以防止鋁擴散入半導體層: 薄膜電晶體1 22爲圖元電極之開關裝置。 恤曰° 吓乂圖兀*電福 11 8疋以透明導電膜製成並連接至汲極電極。在圖1£中— 視頻信號經由源極匯流排線路1 1 7提供而所兩、&quot;；# 叮揚之電荷則县 根據閘匯流排線路1 1 〇上之閘信號而來自 ^ 曰圖兀電極1 1 8。 -26- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---.-----^--------- (請先閲讀背面之注意事項再填寫本頁) 1235418 A7 ----~---___ 五、發明說明（¾ ) 取後在一個大氣壓力下於氫氣壓中以350°C進行退火3〇分 鐘而％成如圖i E至2F所示之薄膜電晶體製造。同時可選 擇座地在薄膜電晶體1 2 2上提供一個氮化石夕膜保護層來保 護薄膜電晶體1 2 2。 按照上述實例中所述方法製造之薄膜電晶體顯示出極高 之性能，例如場效電子移動率約爲22〇 cm2/Vs而臨界電壓 約爲1 ·5V且基體内部之特性變化就場效電子移動率而言約 爲±10%而就臨界電壓而言約爲±0·2ν(曾使用4〇〇&gt;&lt; 320 mm大小之基體對基體上3〇個點加以測量），此一性能 極爲優異。再者，即使反覆作耐用性測試並對溫度之傾向 與應力亦加測量，幾乎未發現有降低特性之情形。因此本 實例足薄膜電晶體有極高之可靠性。同時當關掉薄膜電晶 體時所發生漏洩電流之增加與變化亦無不正常處，但此點 在使用觸媒金屬時常爲一個問題。可以將漏洩電流減至只 有幾個PA而與未使用金屬觸媒有相同之位準。所以輸出 大爲改善。曾以實際照明評估根據本實例所製造用於液晶 顯示裝置之活性矩陣板，結果發現爲高品質液晶面板，甚 少有不均句之顯示且極少有因薄膜電晶體漏電發生之圖元 瑕斑’與以傳統方式製造之薄膜電晶體比較有較高對比 率。雖然本實例製造薄膜電晶體之步驟是針對圖元與活性 矩陣基體而言，但本發明之薄膜電晶體極方便用於薄膜集 體電路等。做此等使用時接觸孔仍在閘電極丨i 〇上但需提 供必要之互接點。 第二實例 -27- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公髮） (請先閱讀背面之注意事項再填寫本頁) % 經濟部智慧財產局員工消費合作社印製 --^-------------------------------- 1235418 A7 五、發明說明（25 ) B7 經濟部智慧財產局員工消費合作社印製 :看圖3與圖4A，對本發明之第二實例加以説明。第二 中之製造方法適用於在—减 金氧丰壤蝴A 央坡璃基組上製造一互補 虱牛導體（CMOS)電路之步 與P型薄膜雷晶髀。t卜竺拔* ，、〒以互補万式形成N型 g 溥膜電晶體將構成活性矩陣型液 曰曰顯'裝置及-般薄膜電晶體電路之週邊驅動電路。 ^3爲et劃圖不出第二實例中薄膜電晶體製造步驟之 圖4A-4F爲沿圖3 IV_IV線所取下之斷面圖，其中顯 不依各圖次序進行之製造步驟。 首先如圖4Α所示在—石英玻璃基體2Q1上以化學汽相搬 積法形成-厚度約爲3〇〇_5⑽nm之氧化♦底膜2〇2。然後 對展膜202之表面加上少量鎳2〇4。添加鎳之方法是在底 膜202上保持一種溶有鎳之浴液並使用一旋轉器將溶液均 勻塗在基體2 0 1上然後使其變乾。在第二實例中是以鎳 酸鹽爲溶質而以水爲溶劑，將溶液中鎳之濃度調整土 10 ppm。因鎳落液是以旋轉法塗在氧化矽所製之底膜2 〇 2 表面上而該表面爲親水性，不必再有特別注意即完成穩 之處理。若鎳溶液如同在第一實例中是塗在無定形矽膜 則必須注意溶劑或無定形矽膜表面之狀態，因爲該表面 恐水性。曾以X光螢光線反射分析法測量加至底膜2 〇 2表面鎳 濃度，發現其大約爲5 X 1〇12原子/平方公分。 接下來如圖4B所示，形成一厚度爲20-60 nm(例如30 nm) 之原質（I型）無定形碎膜2 0 3。此時對基體加熱之溫度最好 勿超過400°C，在第二實例中爲300°C。以平行板電漿化 -28- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 頁 醋 至 定 上 Λ 馬 之 學 經濟部智慧財產局員工消費合作社印製 !235418 A7 ^-------~----B7__—_ 五、發明說明（26 ) 气相嚴積系統做爲化學汽相澱積系統而以 氫（H2)氣做爲來源氣體。㈣功束“玄 个你巩把。射頻功率 &lt; 功率密度定在i 〇 - 100 mw/cm2之較低範圍（例如8〇 mW/cm2)。此時之澱積率 ^約爲5〇 nm/分鐘。如此所獲無定形矽膜203中氫之濃度 馬10·15原子％。 然一種惰性氣壓（例如氮氣）中進行熱處理。在熱處 © /ML度上升中間先進行無定形硬膜之脱水處理，然後 在較高溫度中進行無定形秒膜之晶化。在熱處理之第一步 驟中以450-520 C之溫度進行退火一至二小時而在第二步 驟中以520-570°C之溫度進行退火二至八小時。熱處理先 以500 C進行一小時，再以55〇〇c進行四小時。在熱處理中 底膜202之表面，亦即無定形矽膜2〇3之下面表面。存有 4鎳204發生矽化。無定形矽膜2〇3以矽化鎳做爲晶核而 進行晶化。但因觸媒元素之量並不足以使無定形矽膜2 〇 3 完全晶化，晶體之生成在某一點上即停止。在不超過57(rc 之溫度上碎膜不會有自生晶體之現象，所以在已結晶區内 晶體之生成尚未到達處之矽膜仍保持爲無定形。結果按照 第二實例以550°C進行四小時熱處理後所獲之矽膜爲其中 混有無定形區與已結晶區之狀態。如圖7 b所示之狀態。 此時無定形區與整個矽膜之面積比約爲3 〇 %。個別無定形 區4大小，最大者爲2 μιη。結晶區内個別晶體顆粒之大小 平均約爲1 -1.5 μιη。 如圖4 Β所示藉著以雷射光2 〇 5照射矽膜2 0 3，矽膜2 0 3 進一步晶化而獲得結晶矽膜203a。曾以XeCl激態分子雷射 -29- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---·-----訂---------線！ (請先閱讀背面之注意事項再填寫本頁) 1235418 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（27 ) (其波長爲308 nm，脈衝寬度爲40 nsec)做爲照射之雷射 光运射光照射之條件如下：基體被加熱至2〇〇-450°C (此 處爲400Ό )然後以2〇0_45〇 mJ/cm2(此處爲35〇心⑽2)之能 量密度進行照射。將雷射設計成使其在基體2〇1表面上之 光束大小爲150 mm X丨mm之長形。在與雷射光束縱向垂 直之方向以0.05 mm之步進寬度依序進行掃描。亦即在矽 膜2 0 3之一個選擇點上總共進行2 〇次之雷射照射。因雷射 照射而使矽膜中留存之無定形區熔融且整個膜全部結晶且 僅反映已結晶區中之良好晶體成分 接著如圖4C所示在結晶矽膜2〇3&amp;上澱積一層氧化矽或氮 化矽之絕緣薄膜。然後以圖案形成蔽罩2 〇 6。在第二實例 中是以氧化矽膜做爲蔽罩2〇6。爲形成蔽罩2〇6，以TE〇s 爲源而與氧分解並以射頻電漿化學汽相澱積法加以澱積。 蔽罩206之厚度取好爲100-400 nm。在第二實例中氧化碎 膜之厚度設定爲150 nm。從上面可看出基體之狀態是結晶 碎膜203a之某些部分被蔽罩2〇6以島狀方式所掩蓋，如圖 2C所示之情形。 在此狀態下，如圖4 C所示在整個基體2 〇丨表面自上面以 磷207進行離子摻雜。摻雜磷2〇7之條件如下··加速電壓 爲 5-10 kV ’ 劑量爲 5χΐ〇15- ΐχΐ〇ΐ6 cm-2。在此一步驟 中，磷被植入結晶矽膜2〇3a之曝露區域，因而形成掺有磷 之結晶矽區域203b。另一方面，結晶矽膜2〇3被蔽罩206 掩蓋之區域並未摻入嶙。從上面可看出基體之狀態如圖3 所示。在圖3與圖4C中劃有斜線之部分爲顯示摻有磷之區 30- 木紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） .-----^-------------------------------- (請先閱讀背面之注意事項再填寫本頁) 1235418 A7 _— B7___ 五、發明說明（28 ) 域203b。在圖3中，將來之薄膜電晶體作用區2〇8(2〇8n、 208p)是以虛線標示以便弄清楚將來之薄膜電晶體區、被 蔽罩206所掩蓋矽膜203a區及植入磷之區域2〇3間之關 係。將來成爲薄膜電晶體作用區2〇8之結晶矽膜區在此一 階段全部被蔽罩2 0 6所掩蓋。 在此狀態中基體在一種惰性氣壓（例如氮氣）中以58〇_ 650°C之溫度進行數小時至數十小時之熱處理。在第二實 例中，熱處理是以60(TC進行1 2個小時。在熱處理中在結 晶矽區203b内植入之磷吸引擴散於結晶矽膜刈“中之鎳。 因此結晶矽膜203a被遮蔽區中之鎳濃度大爲降。曾以二次 離子質量分光法測量結晶矽膜203a中實際鎳之濃度，結果 顯示鎳度已降至大約爲5 X 1〇6原子/立方公分。 然後以浸蝕法除去用做蔽罩之氧化矽膜2 〇 6。以對矽膜 2 03有充份選擇性之緩衝氫氟酸i : 1〇做爲浸蝕劑進行濕浸 蚀。 經濟部智慧財產局員工消費合作社印製 隨後爲了半導體裝置之隔離而除去矽膜2〇3a不必要之部 分。亦即在本步驟中使用至少一部分矽膜2〇3a被遮蔽之區 或^/成將要成舄薄膜電晶體作用區（源極/没極區與波道區） 炙島狀結晶膜208η與208p，如圖3所示。因此而獲得圖3與 圖4 D所示狀態之基體。 如圖4 E所示，形成一厚度爲6〇 nm之氧化矽膜做爲閘絕 緣膜2 0 9而掩蓋將成爲薄膜電晶體作用區之結晶矽膜2〇8n 與208p。在第二實例中以TE0S爲源並與氧分解而以射頻 笔滚化學汽相澱積法在基體溫度爲1 50-60CTC，最好是3〇〇_ -31 - 本—:尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) &quot;---- 1235418 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（29 ) 450 C時加以澱積而形成閘絕緣膜2 〇 9。另一種情形是上 做爲源之TEOS可與臭氧分解而在基體溫度爲35(μ6〇〇Ό (取好是400-550°C )時以低壓化學汽相澱積法（或大氣壓力 化學汽相澱積法）予以澱積而形成閘絕緣膜2 〇 9。形成閘 絕緣膜2 0 9後，在一惰性氣壓中以400_600°c之溫度進行一 至四小時之退火來改善閘絕緣膜2 0 9本身之整體特性及結 晶石夕膜與閘絕緣膜間之介面特性。 接著以濺射法澱積一厚度爲4〇〇-8〇〇 nm(;例如5〇〇 鋁膜（含0.1-2%之矽）再將鋁膜製成圖案而形成閘電極21〇n 與21〇p。 下一步以閘電極210η與2 10p做爲蔽罩而以離子摻雜法分 別在作用區208η與208p中植入雜質（磷與硼）。以磷化氫與 硼乙烷做爲掺雜用氣體。加速電壓在前者之情形定爲6〇至 90 kV(例如80 kV)及40至80 kV(例如65 kV)，劑量定爲 1X1015 _ 8X1015 cnT2(例如磷爲 2 X 10i5 cm-2，硼爲 5 χ 10 cm2。在此一掺雜步驟中被閘電極210η與21 Op遮蓋而 其中未植入雜質之區域以後將成爲薄膜電晶體之波道區 212η與212p。在上述之摻雜中有不需要摻雜而以光阻抗蝕 刻遮蓋之區域時則進行選擇性摻雜每種元素（雜質）。結果 即形成N型雜質區213η與214η及P型雜質區213p與214p。 隨後如圖4 E所示以照射雷射光2 1 5進行退火俾活化以離 子植入法而添加之雜質。以XeCl激態分子雷射（其波長爲 308 nm，脈衝寬度爲30 nsec)做爲照射之雷射光。照射是以 250 mJ/cm2之能量密度進行，每一部分照射二十下雷射 -32- 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） ---.-----^--------- (請先閱讀背面之注意事項再填寫本頁) 1235418 A7^ When it is 1 50-600 ° C (preferably 300-45 (rc)), it is deposited by RF plasma chemical vapor deposition method to form the above silicon oxide film. The above source te0s can be combined with ozone together with ozone. It is used after being decomposed with ozone by low pressure chemical vapor deposition method (also atmospheric pressure chemical vapor deposition method) at a substrate temperature of 35 ° C, _600 ° C (preferably 400-550 ° C). It is deposited to form the above-mentioned silicon oxide film. In order to improve the overall characteristics of the gate insulating film 109 itself and the interface characteristics between the crystalline silicon film and the gate insulating film, annealing is performed at a temperature of 400-600000 under inert gas pressure One to four hours. Subsequently, an aluminum film having a thickness of 400 to 800 nm, here 600 nm, is deposited by sputtering. The aluminum film is patterned to form a gate electrode no. Further, the aluminum electrode is deposited. The surface is anodized to form an oxide layer U1. This state corresponds to the situation shown in Figure 2E. The gate electrode 110 and the gate bus line are formed in the same layer. Figure 1D shows a plan for this state. Anodization It is performed in ethylene glycol solution containing 5% tartaric acid. First, the voltage is increased to 220V and The current is unchanged. The substrate is placed in this state for one hour before the end of the anodization. The thickness of the obtained oxide layer lu is 2000 nm. The thickness of the oxide layer 1 1 1 corresponds to the subsequent ion doping The compensation gate area formed in the step. Therefore, the length of the compensation gate area can be determined in the anodizing step. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy Impurities (phosphorus) are doped into the active region by ion doping. Phosphine (PA) is used as the doping gas. The acceleration voltage is set to 60 to 90kv (for example, 80kv), and the amount is 1 X 1 〇15-8X 1015cm-2 (for example, 2 x 1〇15cm_2). The regions with impurities in this step U3 and 114 will later become -25 of thin film transistors.- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 Gongchu) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1235418 A7 ---- R7 _ V. Description of the invention (23) Source and drain regions. Gate electrode 丨 丨 〇 and oxidation around the gate electrode Layer i 丨 丨 shaded area without implanted impurities 1 1 2 later It will become the channel region of the thin film transistor. Then, as shown in FIG. 2E, the laser light is irradiated and then annealed. The impurities doped by the ion implantation method are improved and the crystals damaged in the impurity doping step are improved. Use XeCl to excite the laser (its wavelength is 308 nm and the pulse width is 40 nsec), and the energy density of the irradiation is 15-40 mJ / cm2, preferably 200-250 mJ / cm2. The sheet resistance of the N-type impurity (phosphorus) regions 113 and 114 is 200-800Ω / 0. Then, as shown in FIG. 2F, a silicon oxide film (or a nitride nitride film) having a thickness of about 600 nm is formed as the interlayer insulating film 116. When TE0s is used as the source and oxygen, the plasma chemical vapor deposition method is used, or Te0s and ozone are used to form low-temperature chemical vapor deposition method (or atmospheric pressure chemical vapor deposition method) to form monoxide. The silicon film, the interlayer insulating film 16 thus formed, will be excellent. Another situation is to use Sih and NA as source gases and deposit plasma plasma ions in the shape: a silicon nitride film, hydrogen atoms can be fed into the I interface between the rejection zone and the gate insulation film. This can reduce unpaired overlaps that reduce the characteristics of the thin film transistor. ) Next, a contact hole is formed in the interlayer insulating film 116 to form a thin-film transistor source connection 117 with a metal material (for example, a double-layer film made of nitrided and made by Ming). The titanium oxide film is a barrier film to prevent aluminum from diffusing into the semiconductor layer: The thin film transistor 1 22 is a switching device of the picture element electrode. Shirt is scared. Figure 8: Electricity is made of transparent conductive film and connected to the drain electrode. In Figure 1 — the video signal is provided via the source bus line 1 1 7 &quot;## The sound of the Dingyang County is derived from the gate signal based on the gate signal on the bus line 1 1 0 Electrode 1 1 8. -26- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ---.----- ^ --------- (Please read the precautions on the back before (Fill in this page) 1235418 A7 ---- ~ ---___ V. Description of the invention (¾) After taking it, it is annealed at 350 ° C for 30 minutes under an atmospheric pressure in hydrogen pressure and the percentage is as shown in Figures I E to Manufacture of thin film transistor shown in 2F. At the same time, a thin film transistor protective layer can optionally be provided on the thin film transistor 1 2 2 to protect the thin film transistor 1 2 2. The thin film transistor manufactured according to the method described in the above example shows extremely high performance. For example, the field-effect electron mobility is about 22 cm2 / Vs and the critical voltage is about 1.5 V, and the characteristics inside the substrate change as field-effect electrons. The mobility is about ± 10% and the critical voltage is about ± 0.2v. (The size of a substrate of 400 &gt; 320 mm was used to measure 30 points on the substrate.) This performance Excellent. Furthermore, even if repeated durability tests are performed and the temperature tendency and stress are measured, it is hardly found that the characteristics are degraded. Therefore, this example shows that the thin film transistor has extremely high reliability. At the same time, there is no abnormality in the increase and change of leakage current that occurs when the thin-film electrical crystal is turned off, but this is often a problem when using catalyst metals. Leakage current can be reduced to only a few PAs and at the same level as unused metal catalysts. So the output is greatly improved. The active matrix panel used in the liquid crystal display device manufactured according to this example was evaluated with actual lighting. As a result, it was found to be a high-quality liquid crystal panel with few uneven display and few pixel defects due to thin film transistor leakage. 'Compared with thin-film transistors manufactured in a conventional manner. Although the step of manufacturing the thin film transistor in this example is for the picture element and the active matrix substrate, the thin film transistor of the present invention is very convenient for thin film integrated circuits and the like. For these applications, the contact hole is still on the gate electrode 丨 i 〇 but necessary interconnection points must be provided. Second example-27- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297) (Please read the precautions on the back before filling out this page)% Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs- -^ -------------------------------- 1235418 A7 V. Description of Invention (25) B7 Employees of Intellectual Property Bureau, Ministry of Economic Affairs Printed by a consumer cooperative: See FIG. 3 and FIG. 4A to explain a second example of the present invention. The manufacturing method in the second step is applicable to the step of manufacturing a complementary CMOS circuit on a -Golden Oxygen-rich Yang A glass substrate and a P-type thin film thunder crystal. Thu Zhubiao *, N, g, and N form g-type membrane transistors in complementary modes will form an active matrix type liquid crystal display device and a peripheral driving circuit of a thin-film transistor circuit. ^ 3 is a schematic drawing of the manufacturing process of the thin film transistor in the second example. Figures 4A-4F are cross-sectional views taken along line IV_IV in Figure 3, and the manufacturing steps are not shown in the order of the drawings. Firstly, as shown in FIG. 4A, a chemical vapor phase transfer method is formed on a quartz glass substrate 2Q1-an oxide base film with a thickness of about 300-5 nm. Then, a small amount of nickel 204 was added to the surface of the spreading film 202. The method of adding nickel is to keep a bath solution in which nickel is dissolved on the base film 202 and use a spinner to uniformly coat the solution on the substrate 201 and then dry it. In the second example, nickelate was used as the solute and water was used as the solvent, and the concentration of nickel in the solution was adjusted to 10 ppm. Since the nickel falling liquid is coated on the surface of the base film 2 made of silicon oxide by a spin method and the surface is hydrophilic, no special attention is required to complete the stable treatment. If the nickel solution is applied to the amorphous silicon film as in the first example, attention must be paid to the state of the solvent or the surface of the amorphous silicon film because the surface is water-repellent. The concentration of nickel added to the surface of the base film 2O2 was measured by X-ray fluorescence reflection analysis and found to be about 5 X 1012 atoms / cm2. Next, as shown in FIG. 4B, a primary (type I) amorphous broken film 2 0 3 having a thickness of 20-60 nm (for example, 30 nm) is formed. The temperature for heating the substrate at this time is preferably not more than 400 ° C, and 300 ° C in the second example. Plasmaization with parallel plates-28- This paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm). Page vinegar is set to ^ Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economics and Economics! 235418 A7 ^ ------- ~ ---- B7 __--_ V. Description of the invention (26) The gas phase strict deposition system is used as the chemical vapor deposition system and hydrogen (H2) gas is used as the source gas. The power of the beam is very high. The RF power &lt; power density is set to a lower range of i 0-100 mw / cm2 (for example, 80 mW / cm2). The deposition rate at this time is about 50 nm The concentration of hydrogen in the amorphous silicon film 203 thus obtained is 10 · 15 atomic%. However, the heat treatment is performed in an inert gas pressure (such as nitrogen). The amorphous hard film is first subjected to heat treatment in the middle of the increase in temperature. Dehydration treatment, and then crystallizing the amorphous second film at a higher temperature. In the first step of heat treatment, annealing is performed at a temperature of 450-520 C for one to two hours and in the second step at 520-570 ° C. The annealing is performed at a temperature of two to eight hours. The heat treatment is first performed at 500 C for one hour, and then 5500 c for four hours. In the heat treatment, the surface of the base film 202, that is, the lower surface of the amorphous silicon film 203. 4 Ni 204 was silicified. The amorphous silicon film 203 was crystallized with nickel silicide as the nucleus. However, the amount of the catalyst element was not sufficient to completely crystallize the amorphous silicon film 203. Formation stops at a certain point. There will be no spontaneous crystals in the broken film at a temperature not exceeding 57 (rc) As a result, the silicon film in the crystallized area that has not yet reached the formation of the silicon film remains amorphous. As a result, the silicon film obtained after the heat treatment at 550 ° C for four hours according to the second example is mixed with the amorphous region and The state of the crystalline region. The state shown in Figure 7b. At this time, the area ratio of the amorphous region to the entire silicon film is about 30%. The size of the individual amorphous regions is 4 and the largest is 2 μm. The average size of the crystal particles is about 1 to 1.5 μm. As shown in FIG. 4B, the silicon film 203 is irradiated with laser light 205, and the silicon film 203 is further crystallized to obtain a crystalline silicon film 203a. XeCl excimer laser -29- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) --- · ----- Order --------- Line! Please read the precautions on the back before filling this page) 1235418 Printed A7 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (27) (its wavelength is 308 nm and pulse width is 40 nsec) as the laser light for irradiation The conditions of the irradiation light are as follows: the substrate is heated to 2000-450 ° C (here 400 °) and then heated at 2 ° C. The energy density of 〇0_45〇mJ / cm2 (here: 35〇cardiac 2) is irradiated. The laser is designed so that the beam size on the surface of the substrate 201 is 150 mm X 1 mm long. The laser beam is scanned sequentially in the vertical direction with a step width of 0.05 mm. That is, a total of 20 laser irradiations are performed at a selected point on the silicon film. The silicon film is caused by the laser irradiation. The amorphous region remaining in the substrate melts and the entire film crystallizes and reflects only the good crystalline components in the crystallized region. Then, as shown in FIG. 4C, a layer of silicon oxide or silicon nitride insulating film is deposited on the crystalline silicon film 203 &amp; . A mask 206 is then formed in a pattern. In the second example, a silicon oxide film is used as the mask 206. To form the mask 20, TE0s was used as the source to decompose with oxygen and deposited by RF plasma chemical vapor deposition. The thickness of the mask 206 is preferably 100-400 nm. The thickness of the oxidized film in the second example is set to 150 nm. It can be seen from the above that the state of the substrate is that some parts of the broken film 203a are covered by the mask 206 in an island-like manner, as shown in FIG. 2C. In this state, as shown in FIG. 4C, the entire surface of the substrate 2 is ion-doped with phosphorus 207 from above. The conditions for doping phosphorus 207 are as follows: The acceleration voltage is 5-10 kV, and the dose is 5 × ΐ15-ΐχΐ〇6cm-2. In this step, phosphorus is implanted into the exposed area of the crystalline silicon film 203a, thereby forming a crystalline silicon region 203b doped with phosphorus. On the other hand, the area covered by the crystalline silicon film 20 by the mask 206 is not doped with gadolinium. It can be seen from the above that the state of the substrate is shown in Figure 3. The hatched part in Figure 3 and Figure 4C shows the area doped with phosphorus. 30- Wood paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love). ----- ^ --- ----------------------------- (Please read the notes on the back before filling this page) 1235418 A7 _— B7___ V. Invention (28) Field 203b. In FIG. 3, the future thin film transistor active area 208 (208n, 208p) is indicated by a dashed line in order to clarify the future thin film transistor area, the silicon film 203a area covered by the mask 206, and the implanted phosphorus The relationship between areas 203. The crystalline silicon film area which will become the thin film transistor active area 208 in the future is completely covered by the mask 206 at this stage. In this state, the substrate is heat-treated for several hours to several tens of hours at a temperature of 58-650 ° C in an inert gas pressure (such as nitrogen). In the second example, the heat treatment is performed at 60 ° C for 12 hours. During the heat treatment, the phosphorus implanted in the crystalline silicon region 203b attracts and diffuses the nickel in the crystalline silicon film 刈. Therefore, the crystalline silicon film 203a is shielded. The concentration of nickel in the region was greatly reduced. The actual nickel concentration in the crystalline silicon film 203a was measured by secondary ion mass spectrometry, and the results showed that the degree of nickel had decreased to about 5 X 106 atoms / cm3. Then, it was etched. The silicon oxide film 2 0 6 used as a mask can be removed. Wet etching with buffered hydrofluoric acid i: 10 which is sufficiently selective for the silicon film 2 03 as an etchant. Consumption by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs The cooperative prints and then removes unnecessary portions of the silicon film 203a for the isolation of the semiconductor device. That is, in this step, at least a part of the area covered by the silicon film 203a is used or a thin film transistor is formed. Region (source / non-polar region and channel region), as shown in FIG. 3, and the island-shaped crystal films 208η and 208p are obtained. As a result, a matrix in a state shown in FIGS. 3 and 4D is obtained. As shown in FIG. 4E, Forming a silicon oxide film with a thickness of 60 nm as the gate insulating film 209 to mask The crystalline silicon films 208n and 208p which will be the active region of the thin film transistor. In the second example, TE0S is used as the source and decomposed with oxygen, and the RF pencil rolling chemical vapor deposition method is used at a substrate temperature of 1 50-60CTC. The best is 3〇〇_ -31-This —: The scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) &quot; ---- 1235418 Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 Five 2. Description of the invention (29) It is deposited at 450 C to form a gate insulating film 2 0. Another situation is that TEOS, which is used as a source, can be decomposed with ozone and the substrate temperature is 35 (μ6〇〇Ό (which is good is 400-550 ° C) by low pressure chemical vapor deposition method (or atmospheric pressure chemical vapor deposition method) to form a gate insulating film 2 09. After forming the gate insulating film 2 0 9 Annealing is performed at a temperature of 400_600 ° c for one to four hours in the air pressure to improve the overall characteristics of the gate insulating film 209 itself and the interface characteristics between the crystalline stone film and the gate insulating film. Next, a thickness of 400-800 nm (for example, 500 aluminum film (containing 0.1-2% silicon) and then forming the aluminum film into a pattern and shape Gate electrodes 21〇n and 21〇p. The next step is to use gate electrodes 210η and 2 10p as shields and implant the impurities (phosphorus and boron) in the active regions 208η and 208p by ion doping. Phosphine It is used as doping gas with boroethane. In the former case, the acceleration voltage is set to 60 to 90 kV (for example, 80 kV) and 40 to 80 kV (for example, 65 kV), and the dose is set to 1X1015 _ 8X1015 cnT2 (for example, phosphorus 2 x 10i5 cm-2, and boron is 5 x 10 cm2. In this doping step, the regions covered by the gate electrodes 210η and 21 Op and the regions where no impurities are implanted will later become the channel regions 212η and 212p of the thin film transistor. In the above-mentioned doping, each element (impurity) is selectively doped when there is an area covered by photoresist etching without the need for doping. As a result, N-type impurity regions 213η and 214η and P-type impurity regions 213p and 214p are formed. Then, as shown in FIG. 4E, the laser is irradiated with laser light 2 1 5 and annealed, and the impurity added by the ion implantation method is activated. XeCl excimer molecular laser (with a wavelength of 308 nm and a pulse width of 30 nsec) was used as the irradiated laser light. Irradiation is performed at an energy density of 250 mJ / cm2, and each part is irradiated twenty times with laser -32- This paper size applies to China National Standard (CNS) A4 (210 χ 297 mm) ---. -^ --------- (Please read the notes on the back before filling this page) 1235418 A7

1235418 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（31 ) 可使用各種其他加入鎳之方法。例如下述之各種方法：一 種方法是使用在玻璃上旋轉（Spin 〇n Glass)材料做溶劑而 從二氧化矽膜擴散鎳；一種方法是以離子摻雜技術直接加 入鎳；一種方法是以蒸汽澱積或金屬噴鍍技術形成一極薄 之鎳膜（雖然控制困難）等方法。再者，除鎳以，姑、鈀、 白金、銅、銀、金、銦、錫、鋁與/或銻均可用做促使晶 化之雜質金屬元素。使用任何此等元素均可獲得同樣結 果。 θ 另外，使用波長爲308 nm之XeCl激態分子雷射光做爲以 強光照射部分結晶矽膜使之進一步晶化之工具。此外波長 爲248 nm之KrF激態分子雷射光或波長爲198 nmiArF激態 分子雷射光亦有類似效果。除這些脈衝雷射外，連續振盪 Ar雷射等亦適用。再者，所謂之快速熱力退火（rta)亦稱 爲快速熱處理（RTP)，其中之溫度在短時間内升至1〇〇〇_ 1200 C (矽監測器顯不之溫度）是使用其強度等於雷射光強 度之、、’X外、，泉光、閃光燈或其他強光取代雷射光來對樣本加 熱。 再者，本發明之應用除用於液晶顯示裝置之活性矩陣型 基體外，例如接觸圖像感測器、驅動器内裝型熱頭、使用 有機％效發光（EL)等做爲發光元件之驅動器内裝型光學記 錄或顯示裝置、立體積體電路等均爲可以想得出之應用。 利用本發明即可有南速與高解析度等之高性能裝置。此外 本發明可廣泛適用於半導體裝置之一般半導體加工，包括 雙極電晶體及使用半導體做爲裝置材料之靜電感應電晶 ---.-----訂---------線— (請先閱讀背面之注意事項再填寫本頁} -34-1235418 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (31) Various other methods for adding nickel can be used. For example, the following methods: one method is to use a spin on glass material as a solvent to diffuse nickel from the silicon dioxide film; one method is to directly add nickel by ion doping technology; one method is to use steam Deposition or metallization techniques form a very thin nickel film (though difficult to control). Furthermore, in addition to nickel, palladium, palladium, platinum, copper, silver, gold, indium, tin, aluminum, and / or antimony can be used as impurity metallic elements that promote crystallization. The same results can be obtained using any of these elements. θ In addition, XeCl excimer molecular laser light with a wavelength of 308 nm was used as a tool for irradiating a part of the crystalline silicon film with strong light to further crystallize it. In addition, KrF excimer molecular laser with a wavelength of 248 nm or iArF excimer molecular laser with a wavelength of 198 nm has a similar effect. In addition to these pulsed lasers, continuous oscillation Ar lasers are also applicable. In addition, the so-called rapid thermal annealing (rta) is also known as rapid thermal processing (RTP), where the temperature rises to 1000-1200 C (the temperature at which the silicon monitor is used) in a short period of time. Intensity of laser light, X, X, spring, flash or other strong light instead of laser light to heat the sample. In addition, the application of the present invention is not only used for active matrix substrates of liquid crystal display devices, such as contact image sensors, built-in thermal heads for drivers, or the use of organic% efficiency (EL) as driver of light-emitting elements. Built-in optical recording or display devices, bulk volume circuits, etc. are all conceivable applications. With the present invention, high-performance devices such as South Speed and high resolution can be provided. In addition, the invention can be widely applied to general semiconductor processing of semiconductor devices, including bipolar transistors and electrostatic induction transistors using semiconductors as device materials. — (Please read the notes on the back before filling out this page} -34-

1235418 A7 B7 五、發明說明（32 ) 體。 一 /上面〃兑月中了知使用本發明即可有特性變化少之移定 :性能半導體元件。同時以簡單之製造過程可獲具有：度 上體性之高性能半導體裝置。此外在製造步驟中可大爲提 高裝置之無瑕料，因此可減少產品成本。尤其是在液晶 同時改善了活性矩陣板所需圖元轉換薄膜電晶 ^轉換特性並滿足了構成週邊驅動電路薄膜電晶體所需 “性能與南積體度。因此可有單片驅動器型活性矩陣板 而其中之活性矩陣部分與週邊驅動電路部分是在相同基體 上。所以可達到小型、高性能與低成本之模組。 本發明之説明如上，顯然仍可有很多 /々八之變化，此等 變化不得視爲脱離本發明神之範圍，—切修改料於此項 技術者均甚明顯而且均包括在下述申請專、 ..... ρ寻刊之範圍内。 請 先 閱 讀 背 面 之 注 意 事 項 再 填 寫 本 頁 % I 訂 經濟部智慧財產局員工消費合作社印製 -35- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ^----1235418 A7 B7 V. Description of the invention (32) body. First, I learned that the use of the present invention can achieve a small change in characteristics: performance semiconductor devices. At the same time, a simple manufacturing process can obtain a high-performance semiconductor device with: In addition, the flawless material of the device can be greatly improved in the manufacturing step, thereby reducing the product cost. Especially in the liquid crystal, the element conversion thin film transistor required for the active matrix plate is improved at the same time, and the conversion characteristics of the thin film transistor required to form the peripheral driving circuit are satisfied. Therefore, a monolithic driver type active matrix can be provided. The active matrix part of the board and the peripheral drive circuit part are on the same substrate. Therefore, a small, high-performance and low-cost module can be achieved. The description of the present invention is as above, and obviously there can still be many / 28 changes. Such changes shall not be deemed to depart from the scope of the god of the present invention. All modifications are obvious to those skilled in the art and are all included in the scope of the following application, ..... ρ search. Please read the back Note: Please fill in this page again.% I Order Printed by the Intellectual Property Bureau Employee Consumer Cooperatives of the Ministry of Economic Affairs-35- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ^ ----

Claims (1)

中文申請專利範圍替換本（92年10月） A8 B8 C8 D8 92. ίο. ^ 年月 :修正補充I 六、申請專利範圍 1. 一種製造半導體裝置之方法，包括下述步.驟： 添加元素步驟，亦即對一無定形矽膜添加一種或多 種觸媒元素以促進無定形矽膜之晶化，該無定形矽膜 是形成在一個具有絕緣表面之基體上；及 晶化無定形矽膜之步驟；其特徵在於：上述晶化無 定形矽膜之步驟包括： 第一次晶化步驟，亦即對該無定形矽膜加以熱處理 而使之生成晶體，晶體之生成在尚有剩餘微小無定形 區域之狀態中停止；及 第二次晶化步驟，亦即對在尚有剩餘微小無定形區 域狀態中已停止生成晶體之無定形矽膜以強光照射而 使之進一步晶化； 在第一次晶化步驟後所獲微小無定形區域與整個矽 膜之平面面積比為1〇%_50%。 2. —種製造半導體裝置之方法，其利用促進無定形膜之 晶化的觸媒元素令無定形膜晶化；其特徵在於：包括 下述步驟： 添加元素步驟，亦即對一個具有絕緣表面之基體添 加一種或多種觸媒元素而促進一無定形矽膜之晶化； 矽膜形成步驟，亦即在已添加觸媒元素之基體上形 成一無定形矽膜； 第一次晶化步驟，亦即對該無定形矽膜加以熱處理 促使其生成晶體，而晶體之生成在尚剩餘有微小無定 形區域之狀態下停止；及 本紙張尺度適用中國國家標準(CMS) A4規格(210X 297公釐) 1235418 A8 B8 C8 ~T^ 、申請專利範圍 〜- 、第二次晶化步驟，亦即對在尚剩餘有微小無定形區 域狀怨下已停止生成晶體之無定形矽膜以強光照射而 使之進一步晶化； 在第一次晶化步驟後所獲微小無定形區域與整個矽 膜之平面面積比為10%-50%。 3·根據申請專利範圍第丨或2項之製造半導體裝置方法， 在第一次晶化步驟中晶體之生成是由添加至無定形矽 膜表面或具有絕緣表面之基體上之觸媒元素之量來控 制。 4·根據申請專利範圍第3項之製造半導體裝置方法，其中 添加至無定形矽膜表面或具有絕緣表面之基體上的觸 媒元素之量，就表面濃度而言為lXl〇12 · 1χι〇Π原子/ 平方公分。 ♦ 5·根據申請專利範圍第丨或2項之製造半導體裝置方法， 其中在弟一次晶化步驟後所獲微小無定形區域與整個 矽膜之平面面積比為20%-40%。 6. 根據申凊專利範圍第1或2項之製造半導體裝置方法， 其中在第一次晶化步驟後所獲矽膜中具有與已結晶區 域摻雜在一起之微小無定形區域且個別無定形區域之 平面大小為5 μπι或更小。 7. 根據申請專利範圍第1或2項之製造半導體裝置方法， 其中在第一次晶化步驟後所獲矽膜之已結晶區域是由 母個晶粒大小為5 μιη或更小之多晶碎所組成。 8. 根據申請專利範圍第1或2項之製造半導體裝置方法， -2-Chinese Patent Application Replacement (October 1992) A8 B8 C8 D8 92. ίο. ^ Year: Amendment Supplement I. Scope of Patent Application 1. A method for manufacturing a semiconductor device, including the following steps. Steps: Adding elements Step, that is, adding one or more catalyst elements to an amorphous silicon film to promote the crystallization of the amorphous silicon film, which is formed on a substrate having an insulating surface; and crystallizing the amorphous silicon film The method is characterized in that the above-mentioned step of crystallizing the amorphous silicon film includes: the first crystallization step, that is, the amorphous silicon film is heat-treated to form crystals, and there is still little remaining in the crystal formation. Stop in the state of the shaped region; and the second crystallization step, that is, to further crystallize the amorphous silicon film that has stopped generating crystals in the state of the remaining tiny amorphous region with strong light; The planar area ratio of the micro-amorphous region obtained to the entire silicon film after a single crystallization step is 10% -50%. 2. A method for manufacturing a semiconductor device, which crystallizes an amorphous film by using a catalyst element that promotes the crystallization of the amorphous film, and is characterized by including the following steps: an element adding step, that is, an insulating surface One or more catalyst elements are added to the substrate to promote the crystallization of an amorphous silicon film; the silicon film forming step is to form an amorphous silicon film on the substrate to which the catalyst element has been added; the first crystallization step, That is, the amorphous silicon film is heat-treated to cause it to generate crystals, and the generation of crystals is stopped with a small amorphous area remaining; and this paper size applies the Chinese National Standard (CMS) A4 specification (210X 297 mm) ) 1235418 A8 B8 C8 ~ T ^, the scope of patent application ~-, the second crystallization step, that is, the amorphous silicon film that has stopped generating crystals in the presence of tiny amorphous areas remaining complained by strong light and Further crystallize it; the planar area ratio of the micro-amorphous region obtained after the first crystallization step to the entire silicon film is 10% -50%. 3. According to the method for manufacturing a semiconductor device according to item 1 or 2 of the scope of the patent application, in the first crystallization step, the crystal is generated by the amount of the catalyst element added to the surface of the amorphous silicon film or the substrate having an insulating surface. To control. 4. The method for manufacturing a semiconductor device according to item 3 of the scope of patent application, wherein the amount of the catalyst element added to the surface of the amorphous silicon film or the substrate having an insulating surface is 1 × 1012 · 1 × ι〇Π in terms of surface concentration Atom / cm2. ♦ 5. According to the method of manufacturing a semiconductor device according to item 1 or 2 of the patent application scope, the planar area ratio of the micro-amorphous area obtained after the primary crystallization step to the entire silicon film is 20% -40%. 6. The method for manufacturing a semiconductor device according to claim 1 or claim 2, wherein the silicon film obtained after the first crystallization step has minute amorphous regions doped with the crystallized regions and is individually amorphous. The plane size of the area is 5 μm or less. 7. The method for manufacturing a semiconductor device according to item 1 or 2 of the scope of patent application, wherein the crystallized area of the silicon film obtained after the first crystallization step is a polycrystalline silicon with a crystal grain size of 5 μm or less Composed of pieces. 8. A method for manufacturing a semiconductor device according to item 1 or 2 of the scope of patent application, -2- 8 8 8 8 A B c D 1235418 、申請專利範圍 · 其中之無定形矽膜含有氫，且此膜中氫濃度為3-25原子 % 〇 9. 根據申請專利範圍第8項之製造半導體裝置方法，其中 含氫之無定形矽膜是使用400°C或較低之加熱溫度以電 漿化學汽相沈積法來形成。 10. 根據申請專利範圍第1或2項之製造半導體裝置方法， 其中在第一次晶化步驟中熱處理之溫度是使得自無定 形碎膜本身不會產生自晶核而僅藉觸媒元素生成晶 核’且在該溫度上晶體僅藉觸媒元素之助而生成。 11·根據申請專利範圍第1 〇項之製造半導體裝置方法，其 中在第一次晶化步驟中熱處理之溫度是定在52〇-57〇。〇 之範圍内。 12. 根據申請專利範圍第1或2項之製造半導體裝置方法， 在其中第二次晶化步驟中強光照射之強度範圍是讓無 定形區域之晶化能反映已結晶區域之晶性但不讓已結 晶區域之原有晶性失去。 13. 根據申請專利範圍第1 2項之製造半導體裝置方法，其 中之第二次晶化步驟包括使用一波長為4〇〇 nm或較小 之激態分子雷射光做為照射用之強光而使矽膜表面上 之能量密度為200-450 mJ/cm2。 14. 根據申請專利範圍第1或2項之製造半導體裝置方法， 其中至少使用鎳做為觸媒元素來促進無定形矽膜之晶 化。 曰9 15·根據申請專利範圍第1或2項之製造半導體裝置方法， 本紙張尺度適用中國國家揉準(CNS) A4規格(210X297公釐) 8 8 8 8 Α β CD 1235418 六、申請專利範圍 其中更包括在第二次晶化步驟後進行觸媒元素遷移步 驟使得存留在矽膜中觸媒元素之大多數原子移至半導 體裝置活性區以外之區域。 -4- 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐)8 8 8 8 AB c D 1235418, patent application scope · Among them, the amorphous silicon film contains hydrogen, and the hydrogen concentration in this film is 3-25 atomic% 〇9. According to the method of manufacturing a semiconductor device according to item 8 of the patent application scope, The amorphous silicon film containing hydrogen is formed by plasma chemical vapor deposition using a heating temperature of 400 ° C or lower. 10. The method for manufacturing a semiconductor device according to item 1 or 2 of the scope of patent application, wherein the temperature of the heat treatment in the first crystallization step is such that the self-amorphous broken film itself does not generate from the crystal nuclei and is generated only by the catalyst element Crystal nuclei 'and at this temperature crystals are generated only with the aid of catalyst elements. 11. The method for manufacturing a semiconductor device according to item 10 of the scope of patent application, wherein the temperature of the heat treatment in the first crystallization step is set to 52-57 °. Within the range of 〇. 12. The method for manufacturing a semiconductor device according to item 1 or 2 of the scope of patent application, wherein the intensity range of the strong light irradiation in the second crystallization step is to allow the crystallization of the amorphous region to reflect the crystallinity of the crystalline region but not The original crystallinity of the crystallized area is lost. 13. The method for manufacturing a semiconductor device according to item 12 of the scope of patent application, wherein the second crystallization step includes using an excimer molecular laser light having a wavelength of 400 nm or less as the strong light for irradiation. The energy density on the surface of the silicon film is 200-450 mJ / cm2. 14. The method for manufacturing a semiconductor device according to item 1 or 2 of the scope of patent application, wherein at least nickel is used as a catalyst element to promote the crystallization of the amorphous silicon film. 9 15 · According to the method of manufacturing semiconductor devices according to item 1 or 2 of the scope of patent application, this paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) 8 8 8 8 Α β CD 1235418 6. Scope of patent application It further includes performing a catalyst element migration step after the second crystallization step, so that most of the atoms of the catalyst element remaining in the silicon film are moved to a region outside the active region of the semiconductor device. -4- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)
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