KR100439347B1 - Method of crystallizing a silicon layer and method of fabricating a semiconductor device using the same - Google Patents

Abstract

In the present invention, in the process of crystallizing the silicon thin film used in the active layer of the thin film transistor using MIC or MILC, boron is implanted into the amorphous silicon thin film to increase the size of the crystal of the amorphous silicon thin film and to uniform the direction of the crystal to move electrons. It provides a method of improving the crystallization rate while improving the electrical properties, such as FIG. The silicon crystallization method of the present invention can be effectively used to fabricate thin film transistors of N type, P type or CMOS type.

Description

Crystallization method of silicon thin film and method of manufacturing semiconductor device using same {METHOD OF CRYSTALLIZING A SILICON LAYER AND METHOD OF FABRICATING A SEMICONDUCTOR DEVICE USING THE SAME}

The present invention relates to a method for crystallizing a silicon thin film and a method for manufacturing a semiconductor device using a crystalline silicon thin film. In particular, the present invention relates to a thin film transistor (TFT) used in a display device such as a liquid crystal display (LCD), an organic light emitting diode (OLED), and the like. A thin film transistor having an active layer forming a source, a drain, and a channel formed of crystalline silicon, and a method of manufacturing the same.

Thin film transistors used in display devices such as LCDs and OLEDs typically deposit silicon on transparent substrates such as glass and quartz, form gate and gate electrodes, inject dopants into sources and drains, and then anneal to activate dopants. After forming, an insulating layer is formed thereon. The active layer constituting the source, drain and channel of the thin film transistor is usually formed by depositing a silicon layer on a transparent substrate such as glass by using a chemical vapor deposition (CVD) method. However, the silicon layer deposited directly on the substrate by a method such as CVD has a low electron mobility as an amorphous silicon film. As display devices using thin film transistors require high operating speeds and are miniaturized, the degree of integration of the driving IC is increased and the aperture ratio of the pixel area is reduced. Therefore, the driving circuit is formed simultaneously with the pixel TFT by increasing the electron mobility of the silicon thin film. The need to increase the pixel aperture ratio is increasing. For this purpose, a technique of fabricating a thin film transistor using the amorphous silicon layer by heat treatment to crystallize a silicon layer having a crystalline structure having high electron mobility and using the same has been used.

Various techniques for crystallizing the amorphous silicon layer constituting the active layer of the thin film transistor into a crystalline silicon layer have been proposed. Solid Phase Crystallization (SPC) is characterized by annealing an amorphous silicon layer over several hours to several tens of hours at a temperature of about 700 ° C. or less, which is the deformation temperature of glass, a material that forms the substrate of a display device using a thin film transistor. Way. Since the SPC method requires a long time for heat treatment, when the productivity is low and the area of the substrate is large, there is a problem that deformation of the substrate may occur during a long time heat treatment even at a temperature of 600 ° C. or less. Excimer Laser Crystallization (ELC) is a method of scanning an excimer laser into a silicon layer to instantaneously crystallize the silicon layer by generating a locally high temperature for a very short time. The ELC method has a technical difficulty in precisely controlling the scanning of the laser light, and since only one substrate can be processed at a time, there is a problem that productivity is lowered than when batch processing of several substrates at the same time in a blast furnace.

In order to overcome the disadvantages of the conventional method of crystallizing amorphous silicon, when silicon, such as nickel, palladium, gold, aluminum, is brought into contact with amorphous silicon or injected into the silicon, amorphous silicon is polysilicon even at a low temperature of about 200 ° C. The phenomenon of inducing phase change is used. As such, a phenomenon in which low-temperature crystallization of amorphous silicon is induced by a metal is commonly referred to as metal induced crystallization (MIC). However, in the case of manufacturing a thin film transistor using the MIC phenomenon, a metal component used to induce crystallization of amorphous silicon remains in the crystalline silicon constituting the active layer of the thin film transistor, so that current leakage occurs in the channel portion of the thin film transistor. A problem arises. Recently, instead of the method of inducing the crystallization of silicon by the metal directly contacted or implanted into the silicon, such as MIC, the silicide generated by the reaction of the metal and silicon continues to propagate to the side to induce the crystallization of silicon sequentially. A method of crystallizing a silicon layer using a metal induced lateral crystallization (MILC) phenomenon has been proposed (SW Lee SK Joo, IEEE Electron Device Letter, 17 (4), p. 160, (1996)). As a metal causing such a MILC phenomenon, nickel and palladium, in particular, are known. When the silicon layer is crystallized using the MILC phenomenon, the silicide interface including the metal moves to the side as the crystallization of the silicon layer propagates and the MILC phenomenon is observed. In the silicon layer crystallized using, almost no metal is used to induce crystallization. Flow has the advantage that does not affect the leakage current and other operating characteristics of the transistor to the active layer. In addition, using the MILC phenomenon can induce the crystallization of silicon at a relatively low temperature of 300 ℃ to 500 ℃ has the advantage of simultaneously crystallizing a number of substrates without damaging the substrate (furnace).

However, this method solves many of the problems of crystallization uniformity, yield, etc., which are disadvantages of the crystallization method using a laser.However, in order to fabricate a thin film transistor including a crystalline silicon active layer using this method, it is possible A heat treatment process of several hours at temperature is required. Therefore, the silicon crystallization method using MILC requires a method for effectively reducing the crystallization heat treatment time. In addition, in the case of crystallizing amorphous silicon using MILC, a plurality of needle-like crystal grains of relatively small size grow in an irregular direction to form polycrystalline silicon. Such polycrystalline silicon has a problem in that electrical properties such as electron mobility are inferior to single crystal silicon because it includes many grain boundaries and electron scattering occurs mainly at grain boundaries. Therefore, there is also a need for a method of increasing the size of the grains of the crystalline silicon crystallized using MILC and making the crystallization direction uniform.

In order to solve the problem that the silicon crystallization method by MILC requires a long heat treatment, the present invention focuses on the fact that the silicon crystallization rate by MIC or MILC is influenced by the type and concentration of impurities injected into the silicon. An object of the present invention is to provide a method of accelerating the crystallization rate of silicon by controlling the type of dopant and doping concentration. In addition, an object of the present invention is to provide a method of increasing the size of crystal grains of crystalline silicon formed by MILC and making the crystallization direction uniform by controlling the type and concentration of impurities implanted to crystallize amorphous silicon by MILC. It is done.

1 is a graph showing the MILC rate according to the heat treatment temperature when phosphorus (phosphorous) is injected into the silicon.

Figure 2 is a graph showing the MILC rate according to the heat treatment temperature when boron (Boron) is injected into the silicon.

3a and 3b is a table comparing the crystallization rate when the phosphorus and boron at different concentrations in the silicon.

4A and 4B are electron micrographs showing comparisons between a crystalline state obtained by MILC treatment in a state in which boron is not injected into amorphous silicon and a crystalline state obtained by MILC treatment in a state in which boron is injected;

5A to 5F are cross-sectional views illustrating a thin film transistor manufacturing process according to an embodiment of the present invention.

6A-6D are schematic cross-sectional views showing a method of forming a MILC induction metal layer used in the present invention.

7A to 7D are cross-sectional views illustrating a thin film transistor manufacturing process according to another embodiment of the present invention.

8A to 8D are cross-sectional views illustrating a thin film transistor manufacturing process according to still another embodiment of the present invention.

9A to 9D are cross-sectional views illustrating a process of manufacturing a CMOS transistor according to still another embodiment of the present invention.

♠ Explanation of symbols on the main parts of the drawing ♠

50: substrate

51: amorphous silicon thin film, active layer

52: gate insulating layer

53: gate electrode

According to a first aspect of the present invention for achieving this object, forming a crystallization inducing metal in at least a portion of the amorphous silicon thin film, adding boron to at least a portion of the amorphous silicon thin film; Applying crystallization energy to the boron-doped amorphous silicon thin film to promote the crystallization rate of the amorphous silicon thin film, to enlarge the crystal size of the crystallized silicon, and to increase the uniformity of the crystal direction to increase the electron mobility of the crystalline silicon. A height is provided for the amorphous silicon thin film crystallization method.

According to a second aspect of the invention, forming a crystallization inducing metal in at least a portion of the amorphous silicon thin film, adding boron to at least a portion of the amorphous silicon thin film before or after implanting the N-type dopant into the amorphous silicon thin film And applying crystallization energy to the amorphous silicon thin film implanted with boron, wherein boron implanted into amorphous silicon promotes the crystallization rate of the amorphous silicon thin film, enlarges the crystal size of the crystalline silicon, and crystallographic direction. Provided is an N-type thin film transistor manufacturing method characterized by increasing the electron mobility of the crystalline silicon by making it uniform.

According to a third aspect of the invention, forming a crystallization induction metal in at least a portion of the amorphous silicon thin film, adding boron to at least a portion of the amorphous silicon thin film before or after implanting the P-type dopant into the amorphous silicon thin film And applying the crystallization energy to the boron-doped amorphous silicon thin film, wherein boron implanted into the amorphous silicon promotes the crystallization rate of the amorphous silicon thin film, enlarges the crystal size of the crystalline silicon, and makes the crystal direction uniform. By providing a P-type thin film transistor, characterized in that to increase the electron mobility of the crystalline silicon.

According to a fourth aspect of the present invention, forming a crystallization inducing metal in at least a portion of the amorphous silicon thin film, injecting a P-type dopant containing boron or boron in the amorphous silicon thin film of the N-type and P-type thin film transistor Forming a mask on an amorphous silicon thin film of the P-type thin film transistor, implanting an N-type dopant into the amorphous silicon thin film of the N-type transistor, and applying crystallization energy to the amorphous silicon thin films of the N-type and P-type thin film transistors And the boron implanted into the amorphous silicon promotes the crystallization rate of the amorphous silicon thin film, increases the crystal size of the crystalline silicon, and makes the crystal direction uniform, thereby increasing the electron mobility of the crystalline silicon. A method is provided.

According to a fifth aspect of the present invention, a crystalline silicon active layer is formed by forming a crystallization inducing metal in at least a portion of an amorphous silicon thin film, adding boron to at least a portion of the amorphous silicon thin film, and then applying crystallization energy to the amorphous silicon thin film. The crystalline silicon is provided with an N-type or P-type thin film transistor having a larger crystal size, a uniform crystal direction, and a higher electron mobility than crystalline silicon obtained by applying crystallization energy in a state where boron is not added.

According to a sixth aspect of the present invention, all of the crystalline silicon constituting the N-type and P-type thin film transistor active layers form a crystallization induction metal in at least a portion of the amorphous silicon thin film and boron is added to at least a portion of the amorphous silicon thin film. After the crystallization by applying the crystallization energy to the amorphous silicon thin film, the crystal size is larger than the crystalline silicon obtained by applying the crystallization energy in the absence of boron is characterized in that the crystal direction is uniform and the electron mobility is high A CMOS thin film transistor is provided.

1 is a graph showing a change in the MILC rate according to the heat treatment temperature when phosphorous (phosphorous) is injected into the silicon. In FIG. 1, the injection concentration of phosphorus is about 1 × 10 ¹⁵ / cm ² . As shown in FIG. 1, when the phosphorus is injected into the silicon when the annealing temperature is 500 ° C., the crystallization rate is slightly reduced as compared with the case where the phosphorus is not injected. Although not shown in FIG. 1, it was observed that the effect of reducing the crystallization rate by the injection of phosphorus increased as the concentration of the phosphorus injected increased. However, when the annealing temperature is 550 ° C, the rate of MILC is hardly affected even when phosphorus is injected into silicon. Therefore, the effect of phosphorus injection on the MILC crystallization rate from FIG. 1 depends on the temperature, but generally acts to reduce the MILC crystallization rate, and as the annealing temperature increases, the effect of phosphorus injection on the crystallization rate is relatively small. It can be seen. However, in general, it can be seen that phosphorus injection does not significantly affect the rate of MILC. Although not shown, this phenomenon is also observed when crystallizing silicon by MIC, and the effect of annealing temperature on the crystallization rate is similar to that when using MILC.

2 is a graph showing a change in the MILC rate according to the heat treatment temperature when boron (Boron) is injected into the silicon. In FIG. 2, the implanted concentration of boron is about 1 × 10 ¹⁵ / cm ² . Unlike the case of injecting the phosphorus into the silicon shown in Figure 1 when the boron is injected into the silicon as shown in Figure 2 it can be seen that the crystallization rate by the MILC is significantly increased compared to the case where the boron is not injected. Although not shown, an increase in the concentration of boron injecting boron is observed to increase the MILC crystallization rate more significantly than in the case of not injecting boron. In addition, unlike the case of the injection of phosphorus, the effect of the crystallization rate is increased by the boron injection can be seen that the continuous appearance even if the annealing temperature increases. The effect of increasing the crystallization rate by boron implantation shows a similar tendency even when crystallizing silicon by MIC.

3A and 3B are tables comparing silicon crystallization rates at crystallization heat treatment temperatures of 500 ° C. and 550 ° C. when phosphorus and boron are injected into silicon at a predetermined concentration. 3a and 3b it can be seen that the effect of the mixed impurities on the MILC rate is mainly determined by the injection of boron. In other words, regardless of the heat treatment temperature, and whether or not the phosphorus (Phosphorous) is injected, when the boron is injected into the silicon it can be seen that the MILC rate is greatly increased.

When using a heat treatment temperature of 500 ℃ as shown in Figure 3a the MILC rate of intrinsic silicon is 1.4 ㎛ / hr, when injected with phosphorus was reduced to 1.0 ㎛ / hr, and when boron is injected Irrespective of the concentration, it increased greatly from 2.7 to 2.8 μm / hr. The boron (MIC) speed-up effect of boron is large even when phosphorus is injected at a higher concentration than that of boron, and even when phosphorus is injected at a concentration of 5 x 10 ¹⁵ / cm ^2, the concentration of boron is 1 x 10 ¹⁵ / cm ² When injected into, it shows a MILC rate of 2.0 μm / hr, which is significantly faster than intrinsic silicon.

Even when the crystallization heat treatment at a temperature of 550 ℃ as shown in Figure 3b it can be seen that when boron (Boron) is injected, the MILC rate is greatly increased regardless of the concentration of phosphorus. In particular, when the heat treatment temperature is increased to 550 ℃, the effect of phosphorus on the crystallization rate is reduced, it can be seen that the effect of increasing the MILC rate by boron becomes more remarkable. For example, even when phosphorus is injected into silicon at a high concentration of 5 x 10 ¹⁵ / cm ² , when boron is injected at a relatively low concentration of 1 x 10 ¹⁵ / cm ² , the MILC rate is about twice the MILC rate of intrinsic silicon. You can see that faster. 3A and 3B, when boron is injected at a concentration of 1 × 10 ¹⁵ / cm ² , a MILC speed increase effect similar to that when boron is injected at a concentration of 5 × 10 ¹⁵ / cm ² may be obtained. It can be seen. In summary, boron has a significant effect on silicon's MILC rate regardless of the implant concentration. In addition, the effect of phosphorus on the MILC rate is minimal compared to boron and its effect is further reduced as the heat treatment temperature increases. The effect of improving the crystallization rate by the boron implantation is similar when crystallization of silicon using MIC.

As described above, the crystallization rate of silicon by MILC can be effectively controlled by the type and concentration of impurities implanted in the silicon, and the heat treatment temperature, which can greatly reduce the time required to crystallize the active layer of the thin film silicon. This can greatly increase the productivity of the semiconductor device.

4A and 4B are electron micrographs showing comparisons between a crystalline state obtained by MILC treatment in a state in which boron is not injected to amorphous silicon and a crystalline state obtained in MILC treatment in a state in which boron is injected. FIG. 4A is an electron micrograph showing a crystal state obtained by crystallizing amorphous silicon without impurity implantation at an annealing temperature of 500 ° C. using nickel as a MILC source metal. As shown in FIG. 4A, non-implanted amorphous silicon forms polycrystalline silicon having irregular crystal structures by growing small needle-shaped grains cross each other in approximately two directions by MILC. In such a crystal structure, the boundary of a plurality of grains crossing each other causes scattering of electrons passing through silicon, thereby reducing electron mobility. Accordingly, polycrystalline silicon having a crystal structure as shown in FIG. 4A has poor electron mobility compared to single crystal silicon, thereby limiting the operating speed of a semiconductor device fabricated using the same.

FIG. 4B illustrates a crystallization state by MILC obtained by injecting boron into amorphous silicon at a concentration of 1 × 10 ¹⁵ / cm ² before annealing the amorphous silicon and then annealing under the same conditions as those used to obtain the crystal state of FIG. 4A. It is an electron micrograph showing. As shown in FIG. 4B, when boron is injected into the amorphous silicon before the MILC induction heat treatment, the grain size formed by the MILC is significantly increased as compared with the case of FIG. 4A, and the direction of crystal growth is markedly uniform. have. Although the specific reason for the occurrence of this phenomenon is not yet clear, the results of FIG. 4B show that the crystal is remarkably better than the crystal structure obtained by MILC without boron in the case of injecting boron into amorphous silicon. It can be seen that the structure can be obtained. Summarizing the above description with reference to FIGS. 2 to 4, when boron is injected into amorphous silicon at an appropriate concentration before MILC induction heat treatment, the growth rate of crystals increases and crystal structures such as grain size and crystal growth direction are remarkably increased. It can be seen that the improvement. By using this phenomenon, the characteristics of semiconductor devices such as thin film transistors including a crystalline active layer formed using MILC can be greatly improved. Hereinafter, with reference to the accompanying drawings will be described a specific embodiment of manufacturing a thin film transistor having improved characteristics by using the above phenomenon.

5A to 5F are cross-sectional views illustrating a process of manufacturing an N-type or P-type thin film transistor according to an embodiment of the present invention. 5A is a cross-sectional view of an amorphous silicon layer 51 constituting an active layer of a thin film transistor formed on an insulating substrate 50 and patterned. The substrate 50 is made of an insulating material such as Corning 1737 glass, quartz or silicon oxide. Optionally, a lower insulating layer (not shown) may be formed over the substrate to prevent diffusion of contaminants from the substrate into the active layer. The lower insulating layer may be formed of silicon oxide (SiO ₂ ), silicon nitride (SiNx), silicon oxynitride (SiOxNy), or a composite layer thereof by plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or APCVD. (Atmosphere pressure chemical vapor deposition), ECR CVD (Electron Cyclotron Resonance CVD) using a deposition method such as deposition is formed by a thickness of 300 ~ 10,000 ~ preferably 500 ~ 3,000 at a temperature of 600 ℃ or less. The active layer 51 is formed by depositing amorphous silicon in a thickness of 100 to 3,000 Å, preferably 500 to 1,000 Å, using PECVD, LPCVD, or sputtering. The active layer may include a source, a drain, and a channel region, and then include a region where other elements / electrodes will be formed. The active layer formed on the substrate is patterned to meet the specifications of the TFT to be manufactured. The active layer is patterned by dry etching with a plasma of etching gas using a pattern made by photolithography.

5B is a cross-sectional view of a structure in which a gate insulating layer 52 and a gate electrode 53 are formed on an active layer 51 that is panned with the substrate 50. The gate insulating layer 52 may be formed using a deposition method such as PECVD, LPCVD, APCVD, ECR CVD, and the like to form silicon oxide, silicon nitride (SiNx), silicon oxynitride (SiOxNy) or a composite layer thereof in a range of 300 to 3,000 Å. It is formed by depositing a thickness of ~ 1,000Å. A conductive material such as a metal material or doped polysilicon is deposited on the gate insulating layer by a method such as sputtering, heat evaporation, PECVD, LPCVD, APCVD, ECR CVD, and preferably 2,000 to 4,000 Å thick. The raw gate electrode layer is deposited and patterned to form the gate electrode 53. The gate electrode is patterned by wet or dry etching using a pattern made by photolithography.

5C and 5D illustrate a process of doping the source 51S and the drain region 51D of the active layer using the gate electrode as a mask. In case of manufacturing N-type TFT, dopants such as PH ₃ , P, As, etc. are converted to 1E11-1E22 / cm ³ (preferably 30-100KeV) by using ion shower doping or ion implantation. Is doped with a dose of 1E15 to 1E21 / cm ³ ) (FIG. 5C) A separate doping process may be applied when forming a junction with, for example, a lightly doped region or an offset region in the drain region. Subsequently, boron is implanted at a concentration lower than the concentration at which dopants such as PH ₃ , P, and As are injected. (FIG. 5D) In the case of manufacturing a P-type TFT, dopants such as PH ₃ , P, and As are manufactured in the process of FIG. 5C. Instead, dopants such as B ₂ H ₆ , B, and BH ₃ are doped with a dose of 1E11 to 1E22 / cm ³ (preferably 1E14 to 1E21 / cm ³ ) at a energy of 10 to 200 KeV and injecting boron separately. The implantation process of 5d can be omitted.

5E is a cross-sectional view of the source region 51S and the drain region 51D in which a metal layer 54 for inducing MILC of amorphous silicon constituting the active layer is applied. Nickel (Ni) or palladium (Pd) is preferably used as a metal to induce MILC in amorphous silicon, but in addition to Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru , Rh, Cd, Pt and the like metal may be used. MILC derived metals such as nickel or palladium can be applied to the active layer by sputtering, heat evaporation, PECVD or ion implantation, but sputtering is generally used. The thickness of the applied metal layer can be appropriately selected within the range necessary to induce the MILC of the active layer and is formed to a thickness of about 1 to 10,000 mW, preferably 10 to 200 mW.

5F illustrates a process of forming a MILC source metal layer 54 and then performing heat treatment to induce crystallization of the active layer while activating dopants implanted in the source and drain regions of the active layer. In this process, a tungsten-halogen or xenon arc heating lamp is used for heating for a short time within a few minutes at a temperature of about 700 or 800 ° C. or an ELC method for heating for a very short time using an excimer laser. Etc. can be used. Microwave heating can also be used. In a preferred embodiment of the present invention, it is effective to use a method of crystallizing the active layer using MILC which can crystallize amorphous silicon at a temperature of 300 to 600 ° C. lower than RTA. Crystallization of the active layer is preferably carried out in a furnace at a temperature of 300 to 700 ° C. for 0.1 to 50 hours, preferably 0.5 to 20 hours. During the heat treatment process, in the case of the P-type TFT, the crystallization rate of the amorphous silicon is accelerated by the implanted boron as described with reference to FIGS. 3A and 3B, and in the case of manufacturing the N-type TFT, separately from the N-type impurity, FIG. 5D. Crystallization is accelerated by the boron further injected in the step of, thus greatly reducing the crystallization time compared with the case where no boron is injected. As described with reference to FIGS. 3A and 3B, dopants such as phosphorus or arsenic implanted to manufacture the N-type TFT do not significantly affect the crystallization promoting effect of boron.

Another main feature of the present invention is as shown in FIG. 4B due to boron implanted in amorphous silicon in the process of FIG. 5C when fabricating the P-type TFT and in the process of FIG. 5D when fabricating the N-type TFT. Silicon grains formed by MILC have an effect of increasing size and remarkably uniform direction of crystals. Polycrystalline silicon having a large grain and a uniform crystal direction has a very small scattering of electrons generated at the crystal interface, and thus can have a good electron mobility close to single crystal silicon. Therefore, when boron is implanted into amorphous silicon and crystallization is performed by MILC, crystallization speed is greatly increased, and crystalline silicon having improved crystal structure and electrical properties can be obtained.

Thereafter, a contact insulating layer is formed and patterned to form contact holes. The contact insulating layer is formed by depositing silicon oxide, silicon nitride, silicon oxynitride, or a composite layer thereof in a thickness of 1,000 to 15,000 Å, preferably 3,000 to 7,000 Å, using a deposition method such as PECVD, LPCVD, APCVD, ECR CVD, and the like. . The contact insulating layer is wet or dry etched using a pattern formed by photolithography as a mask to form a contact hole that provides a path through which the contact electrode is connected to the source and drain regions of the active layer. After forming the contact insulating layer and the contact hole, a transistor is manufactured by a conventional method.

According to the method of the present invention, in the case of manufacturing an N-type TFT, boron is separately injected into amorphous silicon, and in the case of manufacturing a P-type TFT, the concentration of boron to be injected is properly controlled to improve the MILC crystallization rate and a good crystal structure. It is possible to form crystalline silicon having electrical properties with. In the process sequence described with reference to FIGS. 5A to 5F, a process of doping phosphorus and a process of doping boron may be reversed, or a process of forming a metal layer inducing MILC and an impurity implantation process may be reversed. have.

6A-6D illustrate various forms of MILC source metal formed in the process of FIG. 5E. The MILC source metal 64 is formed in an offset structure formed to be separated from the gate insulating layer 62 and the gate electrode 53 as shown in FIG. 6A, or formed in an asymmetrical position with respect to the gate insulating layer and the gate electrode as shown in FIG. 6B. It may have an asymmetry structure. The offset structure of FIG. 6A prevents the source metal component from penetrating into the channel region, and the asymmetric structure of FIG. 6B allows the boundary of the crystallization region propagated from the MILC source metal on both sides of the channel region to be located outside the channel region. There is an advantage. In addition, the MILC source metal is formed on the active layer through the contact hole as shown in FIG. 6C or under the gate electrode 63 using the gate insulating layer 62 patterned wider than the gate electrode 63 as shown in FIG. 6D. It may be formed to be offset from the channel region. As shown in FIG. 6C, the method of causing the MILC source metal to the active layer through the contact hole has an advantage of forming the MILC source metal at a desired position without using a separate mask.

7A to 7D are cross-sectional views illustrating a process of manufacturing a thin film transistor according to another exemplary embodiment of the present invention. FIG. 7A is a cross-sectional view in which an amorphous silicon layer 71 constituting an active layer of a thin film transistor is formed on an insulating substrate 70. Here, as shown in FIG. 7b, boron is injected at a low concentration of about 1 × 10 ¹³ / cm ² . Alternatively, the amorphous silicon may be formed so that the amorphous silicon contains boron at such a concentration, and in this case, the process of FIG. 7B may be omitted. Thereafter, a MILC source metal 72 is deposited over the active layer as shown in FIG. 7C. Thereafter, heat treatment for crystallization of the active layer is performed in the same manner as described with reference to FIG. 5F. At this time, the crystallization rate of the active layer induced by the MILC source metal 72 deposited on the active layer is accelerated by the boron component injected or contained in the active layer 71, so that the heat treatment time compared to the case where boron is not injected into the active layer Can be greatly reduced and the crystal structure and orientation formed can be improved. After the active layer is crystallized, the crystallized active layer 71 is patterned as shown in FIG. 7D, the gate insulating layer 73, the gate electrode 74, and the like are formed, and a thin film transistor is manufactured by a conventional method.

8A to 8D are cross-sectional views illustrating a process of manufacturing a thin film transistor according to another embodiment of the present invention. 8A is a cross-sectional view in which an amorphous silicon layer 81 constituting an active layer of a thin film transistor is formed on an insulating substrate 80. As described with reference to FIG. 7B, boron is injected at a low concentration of about 1 × 10 ¹³ / cm ² . Alternatively, the amorphous silicon may be formed so that the amorphous silicon contains boron at such a concentration. In this case, the process of FIG. 8B may be omitted. Thereafter, a MILC source metal 82 is deposited on a portion of amorphous silicon as shown in FIG. 8C. Thereafter, heat treatment for crystallization of the active layer is performed in the same manner as described with reference to FIG. 5F. At this time, crystallization by MIC is performed in the active layer region where the MILC source metal 82 is deposited, and crystallization is performed by MILC propagating from the region where the MILC source metal is deposited in the active layer region where the MILC source metal is not deposited. The crystallization rate by MIC or MILC due to the boron component injected or contained in the active layer is faster than when boron is not injected into the active layer, which shortens the heat treatment time and also forms the crystal structure and electrons of the crystalline silicon formed by the heat treatment. Electrical properties such as mobility are significantly improved. After crystallizing the active layer, as shown in FIG. 8D, the crystallized active layer is patterned, a gate insulating film 83, a gate electrode 84, and the like are formed thereon, and a thin film transistor is fabricated by a conventional method.

As described with reference to FIGS. 7A to 8D, the TFT fabricated when boron is implanted into the entire surface of the amorphous silicon has no problem in the case of the N-type, but when fabricating the P-type TFT, the TFT is implanted into an active layer other than the channel region. Boron may increase the leakage current. However, this problem is generally not a big problem because the concentration of boron doped to increase the crystallization rate is very low, and there is no problem at all when the TFT is used in a driving circuit in which leakage current is not a big problem.

9A to 9D are cross-sectional views illustrating a process of fabricating a CMOS transistor according to still another embodiment of the present invention. In order to form a CMOS as shown in FIG. 9A, amorphous silicon 91 is formed on an insulating substrate 90 and patterned into a predetermined shape. Thereafter, the gate insulating film 92 and the gate electrode 93 are formed on the amorphous silicon 91 by a conventional method. Thereafter, as shown in FIG. 9B, boron is implanted into the amorphous silicon 91 at a concentration of about 3 × 10 ¹⁵ / cm ² using the gate electrode as a mask. Next, as shown in FIG. 9C, the portion where the P-type TFT is to be formed is masked using a thin film such as a photoresist 94 or a metal thin film and phosphorus is injected at a high concentration of about 5 x 10 ¹⁵ / cm ² . Thereafter, the mask is removed as shown in FIG. 9D and the MILC source metal 95 is formed on the entire surface of the substrate. Thereafter, heat treatment is performed in the same manner as described with reference to FIG. 5F to crystallize the active layers of the N-type and P-type TFTs. At this time, the crystallization rate of the active layers of the N-type and P-type TFTs is accelerated by the boron component injected into the active layers of these TFTs for the same reason as described above, thereby shortening the heat treatment time and the crystal size and orientation of the crystalline silicon obtained by MILC. And electrical characteristics such as electron mobility can be greatly improved. From this, it can be seen that the principles of the present invention can be applied as it is in the manufacture of CMOS transistors.

The present invention crystallizes amorphous silicon irrespective of whether or not other impurities are injected when relatively low concentration of boron is injected into amorphous silicon when crystallizing the amorphous silicon constituting the active layer of the thin film transistor by MIC or MILC. It is possible to rapidly manufacture a thin film transistor including an active layer having excellent electrical properties by using the phenomenon that the speed is increased and the electrical properties such as crystal size, orientation and electron mobility of crystalline silicon obtained by MIC or MILC are greatly improved. It works. The present invention can be used in the manufacture of all types of thin film transistors such as N-type, P-type or CMOS, and even when manufacturing all types of thin film transistors, the effects of the present invention as described above can be exhibited equally.

Although the contents of the present invention have been described with reference to specific embodiments, the embodiments of the present invention are merely illustrative of the present invention and should not be construed as limiting the scope of the present invention. The scope of the present invention covers the scope of the claims of the present application, and those skilled in the art to which the present invention pertains can variously change or change the present invention within the principles and scope of the invention set forth in the claims of the present application. It can be modified.

Claims (19)

In the method of crystallizing an amorphous silicon thin film, Forming an amorphous silicon thin film on the substrate; Implanting impurities into the amorphous silicon thin film using a mask to form a channel region, a source region and a drain region; Forming a crystallization inducing metal in at least a portion of the amorphous silicon thin film; And Applying crystallization energy to the amorphous silicon thin film to which boron is added, Boron is injected into the amorphous silicon thin film before the crystallization energy is applied to the amorphous silicon thin film, thereby increasing the crystal size of the crystallized silicon and increasing the uniformity of the crystal direction, thereby increasing the electron mobility of the crystalline silicon. Amorphous silicon thin film crystallization method. The method of claim 1, wherein the crystallization induction metal comprises at least one of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd, Pt Amorphous silicon thin film crystallization method. The method of claim 1, wherein the method of applying the crystallization energy is a heating method using a blast furnace, a heating method using a laser, a rapid thermal annealing method, a RTA method, or a heating method using microwaves. Amorphous silicon thin film crystallization method. The method of claim 1, wherein the boron is implanted at a concentration of 1 × 10 ¹² / cm ² or more. In the method for manufacturing an N-type thin film transistor comprising a crystalline silicon active layer, Forming a crystallization inducing metal in at least a portion of the amorphous silicon thin film; Adding boron to at least a portion of the amorphous silicon thin film before or after implanting an N-type dopant into the amorphous silicon thin film; And Applying crystallization energy to the amorphous silicon thin film implanted with boron, Boron implanted in the amorphous silicon to promote the crystallization rate of the amorphous silicon thin film, to increase the crystal size of the crystalline silicon and to make the crystal direction uniform to increase the electron mobility of the crystalline silicon, characterized in that . The method of claim 5, wherein the crystallization induction metal comprises at least one of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd, Pt Thin film transistor manufacturing method. The method of claim 5, wherein the method for applying the crystallization energy is a heating method using a blast furnace, a heating method using a laser, a rapid thermal annealing method, a RTA method, or a heating method using microwaves. Thin film transistor manufacturing method. The method of claim 5, wherein the doping concentration of boron is lower than the concentration of the N-type dopant implanted in the amorphous silicon thin film. In the method for manufacturing a P-type thin film transistor comprising a crystalline silicon active layer, Forming a crystallization inducing metal in at least a portion of the amorphous silicon thin film; Adding boron to at least a portion of the amorphous silicon thin film before or after implanting a P-type dopant into the amorphous silicon thin film; And Applying the crystallization energy to the amorphous silicon thin film to which boron is added, Boron implanted in the amorphous silicon to promote the crystallization rate of the amorphous silicon thin film, to increase the crystal size of the crystalline silicon and to make the crystal direction uniform to increase the electron mobility of the crystalline silicon, characterized in that . delete The method of claim 9, wherein the crystallization promoting material comprises at least one of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd, Pt Thin film transistor manufacturing method. The method of claim 9, wherein the method of applying the crystallization energy is a heating method using a blast furnace, a heating method using a laser, a rapid thermal annealing method, a RTA method, or a heating method using microwaves. Thin film transistor manufacturing method. In the method for manufacturing a CMOS thin film transistor composed of N-type and P-type thin film transistor, Forming a crystallization inducing metal in at least a portion of the amorphous silicon thin film; Injecting a P-type dopant containing boron or boron into the amorphous silicon thin film of the N-type and P-type thin film transistors; Forming a mask on the amorphous silicon thin film of the P-type thin film transistor and injecting an N-type dopant into the amorphous silicon thin film of the N-type transistor; And Applying the crystallization energy to the amorphous silicon thin films of the N-type and P-type thin film transistors, Manufacture of CMOS thin film transistors, wherein the boron implanted in the amorphous silicon promotes the crystallization rate of the amorphous silicon thin film, enlarges the crystal size of the crystalline silicon and makes the crystal direction uniform, thereby increasing the electron mobility of the crystalline silicon. Way. The method of claim 13, wherein the crystallization inducing metal comprises at least one of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd, Pt. Thin film transistor manufacturing method. 15. The method of claim 14, wherein the method of applying the crystallization energy is a heating method using a blast furnace, a heating method using a laser, a rapid thermal annealing method, a RTA method, or a heating method using microwaves. Thin film transistor manufacturing method. In the N-type or P-type thin film transistor comprising a crystalline silicon active layer, The crystalline silicon is crystallized by forming a crystallization inducing metal in at least a portion of the amorphous silicon thin film, adding boron to at least a portion of the amorphous silicon thin film and then applying crystallization energy to the amorphous silicon thin film, thereby not adding boron. A thin film transistor, characterized in that the crystal size is larger than the crystalline silicon obtained by applying the crystallization energy in the state, the crystal direction is uniform, and the electron mobility is high. The method of claim 16, wherein the crystallization promoting material comprises at least one of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd, Pt Thin film transistor. 17. The thin film transistor according to claim 16, wherein the crystallization energy is applied using a heating method using a furnace, a heating method using a laser, a rapid thermal annealing method, a RTA method, or a heating method using microwaves. . In the CMOS thin film transistor comprising an N-type thin film transistor and a P-type thin film transistor including a crystalline silicon active layer, The crystalline silicon constituting the N-type and P-type thin film transistor active layers all form a crystallization inducing metal in at least a portion of the amorphous silicon thin film, and boron is added to at least a portion of the amorphous silicon thin film, and then crystallized in the amorphous silicon thin film. A CMOS thin film transistor, characterized in that the crystal size is larger, the crystal direction is uniform, and the electron mobility is higher than that of the crystalline silicon obtained by crystallizing by applying energy and applying crystallization energy without adding boron.