TWI232574B - Multi-layer wiring circuit module and the manufacturing method thereof - Google Patents

Multi-layer wiring circuit module and the manufacturing method thereof Download PDF

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Publication number
TWI232574B
TWI232574B TW092118209A TW92118209A TWI232574B TW I232574 B TWI232574 B TW I232574B TW 092118209 A TW092118209 A TW 092118209A TW 92118209 A TW92118209 A TW 92118209A TW I232574 B TWI232574 B TW I232574B
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Taiwan
Prior art keywords
layer
wiring
circuit module
mentioned
insulating layer
Prior art date
Application number
TW092118209A
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Chinese (zh)
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TW200409337A (en
Inventor
Tsuyoshi Ogawa
Original Assignee
Sony Corp
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Publication of TW200409337A publication Critical patent/TW200409337A/en
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Publication of TWI232574B publication Critical patent/TWI232574B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/465—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
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    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/025—Abrading, e.g. grinding or sand blasting
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A multi-layer wiring circuit module is formed by stacking multiple unit wiring layers that are connected through plural via holes. Photolithography treatment is performed to a first insulating layer (22) wherein the respective unit wiring layers (8) to (12) are formed of photosensitive insulating resin material, and a viahole trench (25) is formed. Photo lithography treatment is performed onto a second insulating layer (23) which is formed on the first insulating layer (22) by using photosensitive insulating resin material, and a wiring trench (27) is formed. A conductor metal layer (24) is so formed on the second insulating layer (23) that the viahole trench (25) and the wiring trench (27) are filled with conductor metal. Polishing treatment is performed to the conductor metal layer (24) until a main surface of the second insulating layer (23) is exposed, and a viahole (13) and a wiring pattern (26) are formed by using the conductor metal with which the insides of the viahole trench (25) and the wiring trench (27) are filled.

Description

1232574 玖、發明說明： 【發明所屬之技術領域】 本發明係關於一種謀求薄型化和高密度配線化的多層配 線電路模組及其製造方法。 本申請係在曰本國以2002年7月3曰所申請的曰本專利申 請號碼2002-195018為基礎而主張優先權，此申請藉由參考 引用於本申請。 【先前技術】 例如個人電腦、行動電話、視頻機器、聲頻機器等各種 數位電子機器上設有裝載各種1C元件或LSI元件等半導體 晶片的多晶片電路模組。在各種數位電子機器方面，藉由 電路圖案細微化、1C封裝小型化或積集規模迅速提高、多 插腳化或封裝方法改善等謀求多晶片電路模組的小型化、 回功此化’藉此謀求小型輕量化或薄型化，並且謀求高性 能化、高功能化、多機能化、高速處理化等。 多晶片電路模組中也有構成所謂系統匕^者，其裝載有如 例如邏輯功能和記憶功能或類比功能和數位功能等具備不 同功能的電路。多晶片電路模組中也有將各製程的功能塊 作為個別半導體晶片加以製造，將這些半導體晶片封裝於 同一基板上的構成所謂多晶片電路模組者。 、且說在多晶片電路模組方面，為更加謀求性能提高而要 求微處理器高速化或記憶體晶片間的信號配線高密度化， 需要也謀求對於配線延遲問題的因應。在多晶片電路模組 方面，即使謀求在各元件（晶片）内超過十億赫的時鐘頻率實 85727 493 1232574 現’因在晶片間的配線所造成的信號延遲或反射等問題也 必須以一位數單位降低時鐘頻率。此外，在多晶片電路模 、、且方面’卩远者5某求k號配線的南速化、高密度化，也需要 例如電磁波干擾（EMI: electoromagnetic interference)或電 磁適應性（EMC: electoromagnetic compatibility)的對菜。因 此，在多晶片電路模組方面，不僅晶片形成技術，而且需 要作為包含封t或板等封裝技術的系統技術，全體謀求高 積集化或高性能化。 以往作為多晶片電路模組，有如圖丨所示所構成者。圖i 所不者係覆晶型多晶片電路模組丨〇〇，其係在插入物1 〇 1的 主面l〇la上裝載多數個半導體晶片1〇2A、1〇2B而成。多晶 片電路模組1〇〇在插入物101的正反主面1〇la、1〇lb，雖Z 省略圖示，但分別形成有適當的電路圖案或焊接區、輸出 入端子等。多晶片電路模組100係將各半導體晶片1〇2分別 覆晶連接於預定焊接區1〇3上而裝載於插入物1〇1的主面 l〇la，並用填充料104覆蓋連接部分。多晶片電路模組ι〇〇 係焊踢球1〇5分別裝載於形成於插入物1〇1的主面1〇卜的焊 接區，在載置於例如母基板等㈣態施以回流焊錫處理後 ’藉由將焊錫球1 05熔化、凝固而被封裝。 85727 如上述，習知多晶片電路模組1〇〇係多數個半 1〇2在插入物1〇1的主面101&排列成橫排狀態地被封^阳但 連接各半導體晶片102間的配線卻因形成於插入物ι〇ι側的 電路圖案而受到限制。多晶片t路模組1〇〇隨著裝載此模組 1〇〇的裝置的多功能化、高速化等而設有許多半導體晶片 494 Ϊ232574 2，而要更多的配線數。多晶月雨 月包路杈組1〇〇因形成於以 一般基板製造技術製造的插入物 W荷入物1〇1的配線圖案的間距受 而j;:條件等限制’即使最小也如約〜程度般地大， =數+導體晶心2間進行許多連接時，需要大面積或 被多層化的插入物1 〇 1。 ±在多晶片電路模組100方面’使用被多層化的插入物ΠΗ I係進行透過通道孔的層間連接或各半㈣晶的 連接’但由加工條件’其孔徑即使最小也是約50_程度， 並且焊接區直徑最小為約50_程度，所以需要大型的插入 卜多晶片電路模組1GG此隨著形成於連接各半導體晶 片102間的插入物101的配線圖案變長而形成許多通道孔， 有、c、R成分變大這種問題。 在例如半導體裝置的製程方面也提出—種技術，其係在 石夕基板上形成絕緣層膜後，經過形成通道孔溝和配線溝的 乾式崎程和導體金屬層的成膜形成製程而形成細微配 線圖案。這種配線形成方法係對於絕緣層施以第一乾式姓 刻處理而形成多數個通道孔溝，並且施以第二乾式姓刻處 理而圖案形成配線溝。此配線形成方法係在絕緣層全面用 例如電鑛形成銅膜層後’藉由對此銅膜層施以研磨處理而 形成通道孔和預定的配線圖案。 藉由這種配線形成方法’和-般的配線形成方法比較， 該-般的配線形成方法係、用機械加卫或雷射加工形成通道 孔’並且對銅羯施以1虫刻處理而形成電路圖案，可將細微 且南密度的配線圖案形成於多層。此配線形成方法需要施 495 85727 1232574 以溝深度不同的精穷笙 ,, 理m用^ 刻處理和第二乾式餘刻處 、’ ^ ；般多層配線基板的製程困難。此外，用 此配線形成方法有下述問 田7、在矽基板上將配線 成於多層’所以封穿於丹茸 曰y _ U於母基板等的構造成為複雜，小型化 的貫現困_，並且配線圖案也變長。 【發明内容】1232574 (1) Description of the invention: [Technical field to which the invention belongs] The present invention relates to a multilayer wiring circuit module and a method for manufacturing the same, which are required to be thin and high-density wiring. This application claims priority based on the Japanese patent application number 2002-195018 filed on July 3, 2002 in this country, and this application is incorporated herein by reference. [Prior art] Various digital electronic devices such as personal computers, mobile phones, video equipment, audio equipment, etc. are provided with a multi-chip circuit module containing various 1C elements or semiconductor chips such as LSI elements. With regard to various digital electronic devices, miniaturization of multi-chip circuit modules has been achieved through the miniaturization of circuit patterns, the miniaturization of 1C packages or the rapid increase in the accumulation scale, the multi-pin or the improvement of packaging methods, etc. It is required to be smaller, lighter, and thinner, and to have higher performance, higher functionality, multiple functions, and higher-speed processing. The multi-chip circuit module also constitutes a so-called system controller, which is loaded with circuits having different functions such as a logic function and a memory function or an analog function and a digital function. The multi-chip circuit module also includes so-called multi-chip circuit modules in which functional blocks of each process are manufactured as individual semiconductor wafers, and these semiconductor wafers are packaged on the same substrate. In addition, in terms of multi-chip circuit modules, in order to further improve performance, it is required to increase the speed of a microprocessor or to increase the density of signal wiring between memory chips, and it is also necessary to cope with the problem of wiring delay. In the case of multi-chip circuit modules, even if a clock frequency exceeding one billion hertz is required in each component (chip), 85727 493 1232574, the problem of signal delay or reflection caused by wiring between chips must be addressed by one bit. The number of units decreases the clock frequency. In addition, in the multi-chip circuit mode, and the "distant 5" requires the k-speed wiring to be South-speed and high-density, it also needs, for example, electromagnetic interference (EMI: electoromagnetic interference) or electromagnetic compatibility (EMC: electoromagnetic compatibility). ). Therefore, in terms of multi-chip circuit modules, not only chip formation technology, but also system technology including packaging technology such as package or board, is required to achieve high integration or high performance. Conventionally, as a multi-chip circuit module, there are those constituted as shown in FIG. 丨. All of FIG. I are flip-chip multi-chip circuit modules, which are formed by mounting a plurality of semiconductor wafers 102A and 102B on the main surface 101a of the insert 101. The polycrystalline circuit module 100 is provided with 10a and 10lb on the front and back main surfaces of the insert 101. Although Z is not shown in the figure, appropriate circuit patterns or bonding pads, input / output terminals, and the like are formed respectively. The multi-chip circuit module 100 is a chip-on-chip connection of each semiconductor wafer 102 to a predetermined bonding pad 103, and is loaded on the main surface 101a of the insert 101, and the connection portion is covered with a filler 104. The multi-chip circuit module ιOO series solder kicks 105 are respectively mounted in the soldering areas formed on the main surface 10b of the insert 101, and are subjected to reflow soldering when placed in a state such as a mother substrate. The latter is encapsulated by melting and solidifying the solder balls 105. 85727 As described above, the conventional multi-chip circuit module 100 is mostly half-shaped and is sealed on the main surface 101 of the insert 101 in a horizontal arrangement, but is connected to the wiring between the semiconductor wafers 102. However, it is restricted by the circuit pattern formed on the ιιι side of the insert. The multi-chip t-channel module 100 is provided with many semiconductor chips 494 Ϊ 232 574 2 as the multi-functionalization and high-speed of the device in which this module 100 is mounted, and more wiring is required. The polycrystalline moon rain moon package branch set 100 is subject to the pitch of the wiring pattern formed by the insert W load 101 which is manufactured by a general substrate manufacturing technology. J :: Conditions, etc. It is as large as possible. When many connections are made between the number + conductor cores 2, a large-area or multilayered insert 101 is required. ± In the multi-chip circuit module 100, 'the multilayered interposer ΠΗI system is used to perform interlayer connection of the through-hole or connection of the semi-crystallites', but by processing conditions, the diameter of the aperture is about 50 °, even if it is the smallest. In addition, the diameter of the solder pad is at least about 50 mm. Therefore, a large insertion chip circuit module 1GG is required. As the wiring pattern formed between the inserts 101 connecting the semiconductor wafers 102 becomes longer, many channel holes are formed. , C, and R components become larger. For example, in the manufacturing process of semiconductor devices, a technology is also proposed, which is formed by forming an insulating layer film on a stone substrate and then forming a fine through a dry process of forming a channel hole and a wiring groove and a film forming process of a conductive metal layer. Wiring pattern. This wiring formation method is to form a plurality of channel holes by applying a first dry type engraving treatment to the insulating layer, and pattern forming wiring grooves by applying a second dry type engraving treatment. This wiring formation method is to form a via hole and a predetermined wiring pattern after a copper film layer is formed on the entire surface of the insulating layer, for example, by electric ore. By comparing this wiring formation method with a general wiring formation method, the general wiring formation method is formed by forming a channel hole by mechanical guarding or laser processing, and applying a worming treatment to the copper cymbal. The circuit pattern can form a fine and southern density wiring pattern in multiple layers. This method of wiring formation requires 495 85727 1232574 with different depths of grooves. It is difficult to process the multilayer wiring substrate using the ^ engraving process and the second dry-type engraving process. In addition, this wiring formation method has the following problems. 7. Wiring is formed in multiple layers on a silicon substrate. Therefore, the structure enclosed in tannin y _ U and the mother substrate is complicated, and the miniaturization is difficult. , And the wiring pattern also becomes longer. [Summary of the Invention]

本發明之目的在於租I 在於楗供一種可解決如上述的習知 =模組具有的問題點的新賴多層配線電路模組及其= 本發明之其他目的在於提供一種各單位The purpose of the present invention is to provide a new multi-layer wiring circuit module that can solve the problems as described above. The module has the other purpose of the present invention is to provide a unit.

且高密度的配線圖幸，π H±总、s、， ^ M π ㈡案同日守係通這孔上有通道孔構造，以 表㈣己線長進行層間連接，隨著小型化可實現薄型化，謀 求咼速處理化或可靠性裎古 ’、 、 罪性徒回的夕層配線電路模組及其製造 方法。 /、又口 關於本發明的多層西ρ綠|y Ζ γ々 ” 夕摩配線電路杈組係多數單位配線層透過 夕數個通道孔層間連接声晶 产 按而層$各早位配線層包含第一絕 緣層、第二絕緣層及施以研磨處理的導體金屬I。第― 緣層用感光性絕緣樹脂材料成膜，施以微影處理而形成與巴 各通迢孔對應的多數個通道孔溝。第二絕緣層在第 層上用感光性絕緣樹脂材料成膜，施以微影處理而圖案形 成配線溝，其在一邻八目女41々2 , 一刀具有和各通道孔溝的連通部，與配 線圖案對應。導體金屬層在- - 濁層在弟一、纟巴緣層上，在各通道孔 和配線溝内都填充導體金屬而全面成膜。各單位配 導體金屬形成各通道孔和配線圖案，該導體金屬係填㈣ 85727 496 1232574 施以研磨處理到使第 層的主面構成同一面 配線溝内。 —絕緣層的主面露出而在此第二絕緣 所露出的導體金屬層的各通道孔溝和 藉由關於本發明的多 層配線弘路杈組，由於對用感光性 絕緣樹脂材料成膜的第一 々 罘 '、、巴緣層和弟二絕緣層分別施以由 簡易設備和作業進行的旦/ 、 的彳政衫處理而形成解析度高的通道孔 溝和配線溝，所以可 形成被小的通道孔或細微且高密度的 配、泉圖案糟由多層配線電路模組，將各單位配線層利用 j道孔上有通迢孔構造以最短互相層間連接而層疊形成， 藉此縮短配線長而減低丄 &所傳运“唬的哀減，同時信號延遲 縮減到表小限度日可士y $ T 5某求溥型化，可因應例如大容量、高 速、高密度匯流排。 關於本毛明的多層配線電路模組之製造方法係、製造多數 單位配線層透過多數個通道孔互相層間連接而層疊形成的 夕層配線包路杈組的方法。在此多層配線電路模組之製造 方法’各單位配線層的形成製程包含以下製程··用感光性 絕緣樹脂材料形成第一絕緣層；對於第一絕緣層施以微影 處理而形成與各通道孔對應的多數個通道孔溝；在第一絕 、、彖層上i φ塗佈感光性、絕緣樹脂材料而形成第二絕緣層薄 膜，對於第一、纟巴緣層施以微影處理而形成配線溝，其與在 P刀〃有和各通道孔溝的連通部的配線圖案對應；在第 二絕緣層上，在各通道孔溝和配線溝内都填充導體金屬而 王面幵y成^體孟屬層薄膜；及，研磨導體金屬層到使第二 絕緣層的主面露出。各通道孔和配線圖案用導體金屬形成 85727 -10- 497 1232574 ，5亥導體金屬係填充於施以研磨處理而在第二絕緣層主面 構成同一面所露出的導體金屬層的各通道孔溝和配線溝内 在此衣造方法，第一層的單位配線層係將第_絕緣層成 膜於基底基板上，上層的單位配線層係將各第_絕緣層成 膜於下層的單位配線層的第二絕緣層上所形成。 猎由關於本發明的多層配線電路模組之製造方法，由於 對用感光性絕緣樹脂材料成膜形成的第一絕緣層和第二絕 緣層施以微影處理而形成解析度高的通道孔溝和配線溝， 所以可形成微小的通道孔或細微且高密度的配線圖案。藉 由使用此製造方法，將各單位配線層利用通道孔上有通道 孔構k以取短互相層間連接而層疊形成，藉此縮短配線長 而減低所傳送信號的衰減，㈣信號延遲縮減到最小限度 且可謀求薄型π，可製造可謀求因應例如大容量、高速、 南岔度匯流排的多層配線電路模組。 由在 本發明之另外其他目的，由本發明得到的具體效益 以下參考附圖所說明的實施形態說明當可更加明白Γ 【實施方式】 貫施發明之最佳形態 以下，參考附圖說明適用本發明的多層配線電路模組（ 下只簡稱為電路模組）及其製造方法。 、' 關於本發明的電路模組具有例如資訊通信功 能等’裝載於個人電腦、行動電話或聲頻 ：’ 機器，或是構成作為選件所裝卸的超小型通信功:J電· 的高頻電路部。電路模組雖然省略詳細 ：果組彳 t成馬頻收4 85727 1232574 电路π #利用由收發信號一度變換 方式，或是张# > 、成中間湧率的超外差 飞疋形成南頻收發電路部，其 間頻率而；隹— 進仃遣換成中 、羊而進仃貧訊信號收發的直接變換方式。 關於本發明的電路模組 部2 ••以笛— 所不，包含多層配線電路 主面2a為裝載面，透過封裝 牡、 基板3上·夕垂 、 (4衣載於母And high-density wiring diagram. Fortunately, π H ± total, s ,, ^ M π, the same hole on the same day, there is a channel hole structure on the hole, the connection between the layers with the length of the surface, with the miniaturization can achieve thin In order to achieve rapid processing or reliability, the layer wiring circuit module and its manufacturing method. / 、 About the multi-layered western green of the present invention | y γ γ ″ ximo wiring circuit branch system is the unit wiring layer through a few channel holes to connect the acoustic crystal products between the layers, and each early wiring layer contains The first insulating layer, the second insulating layer, and the conductor metal I that has been subjected to abrasion treatment. The first edge layer is formed of a photosensitive insulating resin material, and is subjected to a lithographic treatment to form a plurality of channels corresponding to the through-holes in Pakistan. Holes and grooves. The second insulating layer is formed on the first layer with a photosensitive insulating resin material, and is patterned to form wiring grooves by lithography. It is adjacent to Hachime female 41々2. The connecting part corresponds to the wiring pattern. The conductive metal layer is on the turbid layer on the first and second edge layers, and each channel hole and wiring trench are filled with conductive metal to form a complete film. Each unit is formed with a conductive metal. Via holes and wiring patterns. The conductor metal system is filled with 85727 496 1232574. The main surface of the first layer is formed into the same wiring groove as the main surface.-The conductor whose main surface is exposed and the second insulation is exposed Channels of the metal layer According to the multi-layer wiring branch road set of the present invention, the first insulation layer, the edge layer, and the second insulation layer formed of a photosensitive insulating resin material are applied by simple equipment and operations. The denim shirt is processed to form high-resolution channel holes and wiring grooves, so small channel holes or fine and high-density distribution and spring patterns can be formed by multi-layer wiring circuit modules. The unit wiring layer is formed by stacking through hole structures on the j channels with the shortest mutual interlayer connection, thereby shortening the wiring length and reducing the transmission loss, and at the same time the signal delay is reduced to the minimum limit. A certain type of y $ T 5 can be used for large-capacity, high-speed, high-density buses. The manufacturing method of the multilayer wiring circuit module of this Maoming is a method of manufacturing a wicker wiring package branch group formed by connecting a plurality of unit wiring layers to each other through a plurality of channel holes. In this multilayer wiring circuit module manufacturing method, the formation process of each unit wiring layer includes the following processes: forming a first insulating layer with a photosensitive insulating resin material; applying a lithographic treatment to the first insulating layer to form the channels A plurality of channel holes and grooves corresponding to the holes; i φ is coated with a photosensitive, insulating resin material on the first insulating layer and the second insulating layer to form a second insulating layer film; A wiring groove is formed, which corresponds to a wiring pattern having a communicating portion with each channel hole in the P blade; on the second insulation layer, each of the channel hole and the wiring groove is filled with a conductive metal, and the king surface is formed. A bulk metal layer film; and polishing the conductive metal layer to expose the main surface of the second insulating layer. Each of the via holes and the wiring pattern is formed of a conductive metal 85727 -10- 497 1232574, and the conductive metal system is filled in each of the via holes and grooves of the conductive metal layer exposed on the same surface on the main surface of the second insulating layer after being polished. In the manufacturing method of the wiring groove, the first unit wiring layer is formed by forming the first insulating layer on the base substrate, and the upper unit wiring layer is formed by forming each of the first insulating layer on the lower unit wiring layer. Formed on the second insulating layer. According to the manufacturing method of the multilayer wiring circuit module of the present invention, a high-resolution channel hole is formed by subjecting the first insulating layer and the second insulating layer formed of a film made of a photosensitive insulating resin material to lithography. And wiring trenches, so that minute via holes or fine and high-density wiring patterns can be formed. By using this manufacturing method, each unit wiring layer is formed by using the channel hole structure k on the channel hole to obtain a short interlayer connection, thereby shortening the length of the wiring and reducing the attenuation of the transmitted signal, and reducing the signal delay to a minimum It is possible to obtain a thin π with a limit, and it is possible to manufacture a multilayer wiring circuit module capable of responding to, for example, a large-capacity, high-speed, and Nancha bus. The specific benefits obtained by the present invention from other objects of the present invention will be more clearly understood from the following description of the embodiments described with reference to the drawings. [Embodiment] The best mode for carrying out the invention is described below with reference to the drawings Multilayer wiring circuit module (hereinafter simply referred to as circuit module) and its manufacturing method. "The circuit module of the present invention has, for example, an information communication function, and is mounted on a personal computer, a mobile phone, or an audio frequency: 'a device, or an ultra-small communication function which is installed as an option: a high-frequency circuit of J Electric · unit. Although the circuit module is omitted in detail: the fruit group will receive 4 85727 1232574 circuit π # using the one-time conversion method of the receiving and receiving signals, or Zhang # >, the superheterodyne flying into the middle surge rate to form the south frequency transceiver The circuit department, during which the frequency and frequency; 隹-directly into the middle and sheep, and into the direct conversion method of poor signal transmission. About the circuit module part 2 of the present invention: • Take the flute—whatever, including the multilayer wiring circuit. The main surface 2a is the mounting surface, which is through the package, on the substrate 3, and on the substrate.

，夕數個（圖2為2個）半導體晶片（LSI)6A、6B 過夕數個半導體封穿：用凸逢 透 第… 封衣用凸起5衣載於此多層配線電路部2的A number of semiconductor chips (LSI) 6A, 6B are shown in the figure (two in FIG. 2), and a number of semiconductors are sealed through: the bumps 5 are provided on the multilayer wiring circuit unit 2

6—B ’·及’密封樹脂層7:密封這些半導體晶片6A ^路核組！係多層配線電路部2起作用作為裝載半導 =片6A、_插入物。又，關於本發明的電路模組⑽ '、、、'未圖不’但適當的電子零件或元件零件也封裝於多層配 線電路部2的第二主面2b上。 #關於本發明的電路模w係多層配線電路部2經過後述的 製程在第一層單位配線層8主面上層疊形成第二層單位配 線層9 ,以下在第二層單位配線層9主面上依次層疊形成第 —層單位配線層1 〇至第五層單位配線層丨2，藉此由五層構 造所構成。此電路模組丨係多層配線電路部2透過貫通第一 層單位配線層8至第五層單位配線層丨2的全層、上下層或多 數層間所形成的通道孔13做層間連接。此外，電路模組厂經 過後述的製程，在多層配線電路部2内形成謀求細微化、微 小化及高密度化的數位電路網。 關於本發明的電路模組1如後述，具備所謂的通道孔上有 通道孔（Vi a-on-Vi a)構造，其在多層配線電路部2的第一層 單位配線層8至第五層單位配線層12，在下層單位配線層側 85727 -12- 1232574 的通運孔上直接形成上層單位配線層側的通道孔。電路模 組1藉由封裝於母基板3，從此母基板3側的電路部對多層配 ’在甩路邰2進行預定信號或電源的供應。因此，關於本發明 的電路模組1透過通道孔13直接連接母基板3和封裝於多層 配線電路部2的第二主面2b上的半導體晶片6八、6B，謀求 配線長的縮短化。此電路模組丨可減低母基板3和半導體晶 片6 A、6B間的傳送信號衰減，並可進行將信號延遲縮減到 最小限度的連接。 關於本發明的電路模組丨如後述，藉由對半導體晶片6 A 、6B和密封樹脂層7施以研磨處理而薄型化，謀求全體的薄 型化。電路模組1如後述，係多層配線電路部2在平坦主面 上設有剝離層21的基底基板20上形成第一層單位配線層8 ，以下在第一層單位配線層8上依次形成第二層單位配線 層9至第五層單位配線層丨2。多層配線電路部2經過預定製 程後，透過剝離層21從基底基板2〇被剝離。又，基底基板 20施以洗淨等處理後被再利用。 關於本發明的電路模組1係多層配線電路部2如後述，在 具有平坦面的基底基板2〇上形成第一層單位配線層8，包含 此第一層單位配線層8的各單位配線層使各主面平坦化，依 次繼續形成上層的單位配線層。因此，電路模組1係第一單 位配線層8至第五層單位配線層丨2高精度且謀求高密度化 形成各配線圖案’並且謀求薄型化。電路模組1藉由使多層 配線電路部2薄型化，使連接和各半導體晶片6a、6B之間 的配線長度更加縮短化。 85727 -13 - 1232574 、、1在夕層配線電路部2内 術成膜形成電容器元件14、暫 戈㈣技 it#16〇 存。。兀件15或螺旋型感應器 兀1干1 6 电谷态凡件14為例如去為中一 σσ二 用的帝0 ^〆 去耦电谷裔或切斷直流成分 用的电夺杰，係由氧化鈕（丁a 。斬在哭-Μ , )胰次虱化鈕（TaN)膜所構成 膜如終端電阻料暫存器，係、由氮化組 =“。此電.路模組1如上述，係第-層單位配線層8至 曰早位配線層12依次層疊於基底基板20或下層單位配 線層的平坦面上般地所形成，所以可形成高精度的電容器 牛9存為凡件15或感應器元件16。f路模組！藉由將 使用習知晶片零件的電容器元件、暫存器元件或感應器元 件專無源兀件形成於多層配線電路部2内，可縮短配線長而 封裝極小型且高性能的無源元件。 關於本發明的電路模組i雖係經過後述的製程所製造，但 第一層單位配線層8至第五層單位配線層12分別包含第一 絕緣層22、第二絕緣層23及導體金屬層24。在此電路模組工 的製程，第一層單位配線層8至第五層單位配線層12的製程 分別具有對於第一絕緣層22形成通道孔13的通道孔溝以形 成製程和用作對於第二絕緣層23形成在一部分具有和通道 孔溝25的連通部的配線圖案26的配線溝27形成製程。在電 路模組1的製程，第一層單位配線層8至第五層單位配線層 1 2的製程分別具有形成對於第二絕緣層23的導體金屬層24 的鍍銅製程和研磨導體金屬層24的化學一機械研磨（CMp • Chemical-Mechanical Polishing)製程。在電路模組 i的製 程’經過上述製程而在第一層單位配線層8至第五層單位配 85727 14 1232574 線層12㈣成配線圖案26和通道孔13。 關於本發明的電路桓 ., 、、，、對於夕層配線電路部2，苴係層 ®形成經過上述製程而 ，、，、曰 上的帛—層單位 弟五層早位配線層12而構成 上封裝半導髅曰Ηαλ ^ ^ 主面2a 衣〜曰曰片6A、6B的半導體晶 樹脂層7密封這些半導 衣％及用在封 ί〇 、且日曰片6Α、6Β的密封樹脂層形成製 程0電路模組1的萝轺1女门士 日/刀乂衣 ^ .+ 4i 、 ”有同4研磨半導體晶片όΑ、6B和 益、树脂層7的研磨製程一 攸弟基底基板20剝離多層配 λ電路部2_離製程，製造電路模組卜 一關於本發明的電路模組1的製程係、對第-'絕緣層22和第 巴、彖層23%以兩解析度的微影製程而形成通道孔溝25和 配線溝27。藉由電路模組1的製程，和習知製程比較，其經 k :通道孔用的孔加工，並對於形成銅箔層的基板使用 開口光罩的圖案形成製程和濕式蝕刻製程或電鍍製程等， 形成可謀求高精声日古金# ' 、 q信度且同袷度、細微化和微小化的具有通道 孔1 3或配線圖案26的電路模組玉。 關於本、明的電路模組丨利用上述製程製造，藉此在第一 層單位配線層8至第五層單位配線層12，將各通道孔U微小 且知么形成到幾μΐΏ程度，並且各配線圖案％也將間距非常 細$形成為幾4以級。電路模組丨藉由在第一層單位配線層8 至第五層單位配線層12形成例如將上下層以接地夾住的微 帶線，可形成被阻抗控制的配線圖案26。 /用關於本發明的製造方法製造的電路模組1相較於採 用白知製造方法製造的電路模組，在面積尺寸可縮小到約 85727 -15 - 1232574 程度，可提高使用極限頻帶到20 GHz。關於本發明的 電路模㈣以例如5，程度的厚度形成構成多層配線電 路部2的第一層單位配線層8至第五層單位配線層12，多層 配線電路部2的全體厚度亦可抑制到幾十μιη程度以内。^ 於本發明的電路模組丨係半導體晶片6Α、6Β也精密且最大 限^地研磨成為H)0_程度的厚度，所以被大幅薄型化。 茲參考圖3至圖12詳細說明關於本發明的電路模組1之製 造方法的各製程。 、 在關於本發明的電路模組丨的製程，首先供應如圖^所示 般地所形成的基底基板20。基底基板2〇係由具有絕緣特性 、耐熱特性或耐藥品特性，可形成高精度平坦面，並且具 有機械剛性的例如矽基板、玻璃基板或石英基板等基板材 料所形成。基底基板20藉由使用這種基板材料，對於後述 _處理時的表面溫度上升抑制熱變化，並且微影處理時 保持焦點深纟’謀求遮蔽的接觸對準特性的提高而可製造 高精度的電路模組丨。又，基底基板2〇並不限於上述基板= 料，也可以使用做過平坦化處理的其他適當的基板材料。 用於本發明製造方法的基底基板2〇係對主面2〇a施以研 磨處理而形成作為咼精度的平坦面，在此主面上形成剝 離層21薄膜。剝離層21包含金屬薄膜層，其係用例如減鑛 法或化學蒸鑛法（CVD : Chemical Vap〇r Dep〇siti〇n)等在^ 底基板20的主面20a上具有1〇 _程度的均勾厚度且遍及： 面形成的銅或紹等；及，樹脂薄膜層，其係在此金屬薄膜 層上用例如旋塗法等全面形成的厚度…〜2 _程度的聚 85727 -16- 1232574 醯亞胺樹脂等。剝離層21在後述剝離製程，以第_層單位 配線層8為剝離面而從基底基板2 〇剝離多層配線電路部2。 關於本發明的電路模組丨的製程，係在剝離層21上形成第 一層單位配線層8。第一層單位配線層8的製程如圖3所示， 以在基底基板20的剝離層21上形成第一絕緣層22薄膜的製 程為第一製程。第一絕緣層22使用例如聚醯亞胺系或環2 系的負型感光性絕緣樹脂材料，用可塗佈均勻特性或厚度 控制特性的例如旋塗法、幕式塗佈法、滾塗法或浸塗法^ 遍及全面成膜於剝離層21上。第一絕緣層22藉由透過平坦 的剝離層21成膜於平坦的基底基板2〇上，可以均勻的厚度 形成。 第一層單位配線層8的製程以施以第一微影處理而在第 一絕緣層22與通道孔13對應形成通道孔溝乃的製程為第二 製程。第一微影處理如圖4所示，具有將第一光罩3〇定位配 置於第一絕緣層22表面的處理、透過第一光罩3〇使第一絕 緣層22預定部位曝光的第一曝光處理及使第一絕緣層22顯 影的第一顯影處理。第一光罩3〇如圖4所示，係由片狀材料 構成，該片狀材料形成有以與通道孔13對應的通道孔溝25 的形成部位為遮光部3〇a，以其他部位為透光部3〇b的遮光 、透光圖案，在定位於第一絕緣層22表面上且密合的狀態 下被配置。 第一曝光處理係採用照射例如在χ-γ方向控制動作的雷 射光的方法或照射來自水銀燈等的出射光的方法等適當方 法，如圖4所示，用從第一光罩30的透光部3〇b透過的處理 584 85727 -17- 1232574 光[，使第-絕緣層22選擇曝光。在第—絕緣層22用此第一 曝光處理如圖种以虛線所示，除了形成通道孔㈣部分之 一、p刀遍及厚度方向的全區被選擇曝光而被潛像化。第 、一顯影處理係藉由將做過例如第-曝光處理的基底基板20 :包在鹼性溶液中，如圖5所示，除去第一絕緣層22的未曝光 邛：’即形成各通道孔13的部分而形成預定的通道孔溝25。 一弟一層單位配線層8的製程以在形成有通道孔溝Μ的第 =邑、緣層22上，如圖6所示，形成第二絕緣層23薄膜的製程 二第製私第一絕緣層23也和第一絕緣層22同樣，使用 例如聚醯亞胺系或環氧系的負型感光性絕緣樹脂材料，用 可盒佈均勾特性或厚度控制特性的例如旋塗法、幕式塗佈 穿i法或，又塗法等遍及全面以均勻膜厚成膜形成於第 一絕緣層22上。絕緣樹脂材料如圖6所示，藉由第一製程也 填充於形成於第一絕緣層22的通道孔溝25内。 第一層單位配線層8的製程以施以第二微影處理而在第 一、纟巴緣層23與配線圖案26對應形成配線溝27的製程為第四 製程。第二微影處理也如圖7所示，具有在第二絕緣層23表 面配置第二光罩31的處理、透過第二光罩31使第二絕緣層 23預定部位曝光的第二曝光處理及使第二絕緣層u顯影的 第二顯影處理。第二光罩3U〇gj 7所示，係由片狀材料構成 ’該片狀材料形成有以形成與配線圖案26對應的配線溝 的部分為遮光部3ia，以其他部位為透光部31b的遮光、透 光圖案，在定位於第二絕緣層23表面上且密合的狀態下被 配置。 585 85727 -18 - 1232574 第二曝光處理也使用和上述第一曝光處理相同的曝光裝 置，用從第二光罩31的透光部31b透過的處理光^使第二絕 緣層23選擇曝光。第二曝光處理如圖7以虛線所示，係在第 、’、巴、、、彖層2 3使除了配線圖案2 6對應部分之外的部分遍及厚 度方向的全區選擇曝光而進行潛像化。第二顯影處理係藉 由將做過例如第二曝光處理的基底基板20泡在鹼性溶液中 ，如圖8所示，除去第二絕緣層23的未曝光部分，即填充於 各通道孔溝25的絕緣樹脂材料和配線圖案％的對應部位而 和預定的通道孔溝25共同圖案形成配線溝27。 第一層單位配線層8的製程以對於形成有通道孔溝25和 配線溝27的第—絕緣層23施以金屬電鍍處理而成膜形成導 體金屬層24的製程為第五製程。金屬電鑛處理也可以是電 解電鍍或無電極電鍍的任何_種，如圖9所示，係和通道孔 溝25共同填充導體金屬到配線溝27内部而在第二絕緣層η 全㈣成具有狀厚度的導體金屬層24。金屬電錢處理具 體而言’係將導體金屬層24為形成導電率佳的銅膜層而施 以鑛銅，利用電解電錢形成導體金屬層24時，將剝離層21 作為施加電壓電極加以利用。 第一層早位配線層8的製程以對於導體金屬層Μ研磨到 :吏第二絕緣層23主面露出的製程為第六製程。研磨處理係 精由和導體金屬層24共同研磨第二絕緣層训一部分，如 圖1 0所示，將第一層單 平仅配線層8的主面8a形成平坦面。研 磨處理係同時研磨材曾X π 材貝不同的第二絕緣層23和導體金屬岸 24，所以用CMP法進行， 曰 仃其CMP法具有增大導體金屬層24 5Θ6 85727 -19- J232574 研磨速率之類的研磨選擇性。 第一層單位配線層8的製程係藉由施以上述研磨處理， 圖10所示，填充於通道孔溝25和配線溝27的導體金处屬’如 銅層和第二絕緣層23構成同一面而露出，製作分別形成^ 通道孔13和配線圖案26的帛一層單位配線層8。第—層單位 配線層8如上述’係在基底基板2〇上以高精度的厚度形成第 二絕緣層22和第二絕緣層23，利用施以高解析度的第 影處理和第二微影處理所形成的通道孔溝2 5和配線溝^形 成通道孔13和配線圖案26而成。 因此，第一層單位配線層8全體被薄型化而構成，配線圖 案26具有和第二絕緣層23厚度同等的厚度，所以可保持充 分的信號傳送特性。第一層單位配線層8係通道孔溝2 5和配 線溝27為高密度且細微化、微小化而形成於第一絕緣層。 和第二絕緣層23，藉此可形成謀求高密度且細微化、微小 化的通道孔13或配線圖案26。第一層單位配線層8上雖然詳 細省略，但形成有用作和配線圖案26共同封裝於母基板^的 連接焊塾或輸出入電極。 又，在上述第一層單位配線層§的製程，雖然用負型感光 性絕緣樹脂材料成膜形成第一絕緣層22和第二絕緣層23， 但也可以用正型感光性絕緣樹脂材料成膜形成。在這種製 私，第一光罩30或第二光罩31以與通道孔溝25或配線溝27 對應的部分為透光部，以其他部分為遮光部。此外，在這 種製程’第一曝光處理之際要曝光到第一絕緣層2 2，所以 需要進行曝光量的控制。 85727 -20- 1232574 電路模組^的製程係在上述第—層單位配線層8被平抽化 的主面上施以第二層單位配線層9的製程。第二層單位配 =層9的製程係、在第—層單位配線層8的主面仏上形成第— ^緣層22薄膜後’施行施以形成上述通道孔溝_第一微 影處理的製程、第二絕緣層23的形成製程、施以形成配線 溝27的第二微影處理的製程、導體金屬層μ的形成製程及 研磨製程。在第二層單位配線層9的製程，雖然省略詳細， 但利用適當的方法也形成電容器元件14、暫存器元件。或 感應器元件16等無源元件。 在電路模組1的製程，係在第二層單位配線層9上施以9 第三層單位配線層的製程，以下依次施以上層單位配線層 的形成製程，藉此如圖丨丨所示，在基底基板2〇上製作多層 配線電路部2。多層配線電路部2係形成於第一層單位配線 層8至第五層單位配線層12的通道孔13如圖u所示，在下層 側的通道孔上直接形成上層側的通道孔而構成通道孔上有 通道孔構造。因此，多層配線電路部2可以最短配線長連接 第一層單位配線層8至第五層單位配線層12間。多層配線電 路部2因在被平坦化的下層單位配線層上依次形成上層單 位配線層，而抑制下層側的配線圖案厚度累積所造成的影 響’並在無翹曲、彎曲或凹凸的狀態形成最上層的第五單 位配線層12。因此，多層配線電路部2在第五單位配線層} 2 上再形成高精度的單位配線層而可高積集化。 在電路模組1的製程’如圖12所示，係在構成多層配線電 路部2的第二主面2 b的第五單位配線層12主面上施以封裝 S0S 85727 1232574 半導體晶片6A、6B的製程。第五單位配線層12上雖然省略 詳細，但和配線圖案26同樣，形成有用作用覆晶封裝法等 適田的封1方法封裝半導體晶片6A、6B的電極焊墊或用作 進订和其他電子零件或其他模組的連接等的連接端子部。 又，對電極焊塾或連接端+部施以例如無電極鍵錦/鋼而進 行端子形成。半導體晶片封裝製程雖然省略詳細，但包含 在半導體晶月6A、6B的電極安裝封裝用凸起5的製程，將 半導體晶片6A、6B定位於第五單位配線層12上而载置的製 程及施以例如回流焊錫處理的製程等。 在電路模組1的製程火，如圖12所示，係施以密封製程， 其用密封樹脂層7密封封裝的半導體晶片6A、6B。密封樹 脂層7係㈣列如如環氧樹脂等熱硬化收縮率小的^脂二 料’以傳送模法或印刷法等形成，抑制硬化後使基底基板 2〇或多層配線電路部2產生翹曲等的應力產生。 _ 土 一在電路模組1的製程，係施以研磨半導體晶片6α、沾和 岔封樹脂層7到預定厚度的製程。研磨製程係利用例如使用 研磨機的機械研磨法、濕式㈣的化學研磨法或併用機械 研磨法和化學研磨法的CMP等進行，藉由和密封樹脂層7共 同將半導體晶片6Α、6Β在對功能無阻礙的最大範圍研磨其 表面’如圖13所示般地薄型化。研磨製程係以基底基板 為支持基板，在用密封樹脂層7密封半導體晶片6A、_ 狀態研磨’藉此不使各半導體晶片6A、6B產生邊緣出缺等 損傷而以最大限度且精密地研磨。 在電路模組1的製程 雖然詳細省略，但將具有剝離層的 85727 -22- 1232574 第二基底基板與做過研磨處理的密封樹脂層7接合後，施r 從基底基板20剝離電路模組丨的製程。第二基底基板為 路模組1封裝於母基板3等而在構成多層配線電路部9的^ -主面2a㈣-單位配線層8形成電極焊墊或構成施以平 坦化處理之際的基底。 基底基板剝離製程係、使經過上述製程而形成電路模組^ 的基底基板20浸泡於例如鹽酸等酸性溶液中。電路模組1係 在酸性溶液中，在剝離層21的金屬薄膜層和樹脂薄膜㈣ 界_進行，在將樹月旨薄膜層留在第一單位配線層8側的 狀態從基底基板20被剝離。又，剝離製程也可以藉由例如 施以雷射消14處理，將電路模組！從基底基板糊離。此外 ，留在第一單位配線層8側的樹脂薄膜層為例如氧電焚的 乾式姓刻法等除去。 對夕層配線電路部2施以電極形成處理，其係在形成於露 =弟一主面2a的第一層單位配線層8的連接焊墊或輸出入 端子表面用無電極電鍍形成金_鎳層。電路模組1在連接焊 墊安裝封裝用凸起4，在定位於母基板3的狀態施以回流焊 錫而破封裝。又，電路模組丨係在母基板3的封裝製程之前 知以第一基底基板的剝離製程。 在上述電路模組丨的製程，雖然說明了在基底基板2〇上製 作1個電路模組！的製程，但也可以使用比較大型的基底基 板20併製作多數個電路模組丨。在電路模組1的製程，這 種情況係在從基底基板20的剝離製程之前，施以分離各電 路模組1的連結部切割處理。此外，在電路模組！的製程， 85727 -23- 1232574 雖然在由矽基板或玻璃基板構成的基底基板20上製作電略 模組1，但也可以使用做過例如平坦化處理的在一般多層基 板的製程所用的各種有機基板。 關於本發明的電路模組1雖然構成如下：多層配線電路部 2也具備作為封裝半導體晶片6A、6B的插入物的功能，作 當然也可以用作單獨的多層配線電路模組。此外，當然電 路模組1也可以在多層配線電路部2的第一主面2a側也封袭 半導體晶片或封裝零件。電路模組1在這種情況，係在第〜 主面2a側也將第二基底基板作為基底而施以平坦化處理。 又，本發明並不限於參考附圖而說明的上述實施例，不 脫離附上的申請節圍及置*匕 5、社"々# μ π τ月乾及具主曰，可進仃各種變更、調換或 其同等者，對熟悉本技藝而言是顯而易見的。 產業上的利用可能性 如上逑，本發明的各單位配線層係對用感光性絕緣樹月; 材料形成的第一絕緣層施以微影處理而形成通道孔溝，^ 在此第絶緣層上對用感光性絕緣樹脂材料形成的第二辞 微影處理而形成配線溝，對在通道孔溝和配㈣ =體金屬般地形成於第二絕緣層上的導體金屬驗 研磨處理到使第—纟g纟矣麻 .κ 七濠層的主面露出而用填充於通道孔请 二二溝内的導體金屬形成通道孔 解析度高的微影處理，^自 所以糟由 配線圖幸而π 度形成微小且細微的通道孔或 缘圖案而可和小型化共同謀 於利用通道孔上右、s… 精由本务明，由 層，所以因配線長纟^孔構造以最短層間連接各單位配線 、m化而減低傳送信號的衰減，同時將 ^>1 1 85727 -24, 1232574 傳运的延遲縮減到最小限度，並且也…/ 此可謀求可靠性的提言，、，^ '-雜訊的影響，藉 度化匯流排的因應。 τ4求大容量、高速化、高密 【圖式簡單說明】 圖1為顯示習知電路模組的縱截面圖。 圖2為顯示關於本發明的電路模 圖3為^ f . 、、勺要邛縱截面圖。 不弟-絕緣層形成製程的縱截面圖。 圖 為顯示對第一絕緣層施行的第-曝光製程的縱截面 圖 圖5為顯示對第一絕緣層施行的第 顯影製程的縱截面 圖 圖 圖6為為顯示第 圖7為顯示對第 〇 圖8為顯示對第 〇 圖9為顯示對第 縱截面圖 -絕緣層形成製程的縱截面 :絕緣層施行的第二曝光製程的縱截面 •絕緣層施行的第二顯影製程的縱截面 絕緣層施行的導體金屬層形成製程的 圖 磨 圖：為顯示導體金屬層施以化學—機械 製釦的縱截面圖。 幻研 圖】〗為％ + π 面圖。…、>成於基底基板上的多層配線電路部的縱截 圖12為顯示將半導 的縱截面圖。 體晶片封裝於多層配線電路部的製程 85727 -25· 1232574 圖1 3為顯示對半導體晶片和密封樹脂層施以研磨處理的 研磨製程的縱截面圖。 【圖式代表符號說明】 1 電路模組 2 多層配線電路部 2a 第一主面 2b 第二主面 3 母基板 4 封裝用凸起 5 半導體封裝用凸起 6A，6B 半導體晶片 7 密封樹脂層 8 第一層單位配線層 8a 主面 9 第二層單位配線層 10 第三層單位配線層 11 第四層單位配線層 12 第五層單位配線層 13 通道孔 14 電容器元件 15 暫存器元件 16 感應器元件 20 基底基板 20a 主面 85727.doc -26- 1232574 21 剝離層 22 第一絕緣層 23 第二絕緣層 24 導體金屬層 25 通道孔溝 26 配線圖案 27 配線溝 30 第一光罩 30a 遮光部 30b 透光部 31 第二光罩 31a 遮光部 31b 透光部 100 多晶片電路 101 插入物 101a 主面 101a，101b 正反主面 102A, 102B 半導體晶片 103 焊接區 104 填充料 105 焊錫球 S14 85727 -27 -6-B ′ · and ′ sealing resin layer 7: Seal these semiconductor wafers 6A ^ Road core group! The multilayer wiring circuit unit 2 functions as a mounting semiconductor chip 6A, an insert. In addition, as for the circuit module ⑽ ',,,' not shown 'of the present invention, appropriate electronic parts or component parts are also packaged on the second main surface 2b of the multilayer wiring circuit section 2. # Regarding the circuit mold of the present invention, the multi-layer wiring circuit unit 2 is laminated on the main surface of the first unit wiring layer 8 to form a second unit wiring layer 9 through a process described later, and the main surface of the second unit wiring layer 9 is hereinafter The first to fifth unit wiring layers 10 to 5 are sequentially stacked on top of each other to form a five-layer structure. This circuit module 丨 is a multi-layer wiring circuit section 2 for inter-layer connection through a through-hole 13 formed through the entire layer, the upper and lower layers, or a plurality of layers penetrating the first unit wiring layer 8 to the fifth unit wiring layer 丨 2. In addition, the circuit module factory has formed a digital circuit network for miniaturization, miniaturization, and high density in the multilayer wiring circuit unit 2 through a process described later. As will be described later, the circuit module 1 of the present invention has a so-called via hole (Vi a-on-Vi a) structure, which is formed on the first unit wiring layer 8 to the fifth layer of the multilayer wiring circuit portion 2 For the unit wiring layer 12, a via hole on the upper unit wiring layer side is directly formed on the through hole on the lower unit wiring layer side 85727-12-1232574. The circuit module 1 is packaged on the mother substrate 3, and from this circuit portion on the mother substrate 3 side, a multilayer signal is supplied on the circuit board 2 to supply a predetermined signal or power. Therefore, the circuit module 1 of the present invention directly connects the mother substrate 3 and the semiconductor wafers 6 and 6B packaged on the second main surface 2b of the multilayer wiring circuit portion 2 through the channel hole 13 to reduce the wiring length. This circuit module can reduce the attenuation of the transmission signal between the mother substrate 3 and the semiconductor wafers 6 A and 6B, and can make a connection to reduce the signal delay to a minimum. Regarding the circuit module of the present invention, as will be described later, the semiconductor wafers 6 A and 6B and the sealing resin layer 7 are thinned by polishing, thereby reducing the overall thickness. As described later, the circuit module 1 is a multilayer wiring circuit unit 2 in which a first unit wiring layer 8 is formed on a base substrate 20 provided with a release layer 21 on a flat main surface, and a first unit wiring layer 8 is sequentially formed on the first unit wiring layer 8 below. The second unit wiring layer 9 to the fifth unit wiring layer 2. After the multilayer wiring circuit portion 2 undergoes a predetermined process, it is peeled from the base substrate 20 through the release layer 21. The base substrate 20 is reused after being subjected to a treatment such as cleaning. The circuit module 1 of the present invention is a multilayer wiring circuit unit 2 as described later. A first unit wiring layer 8 is formed on a base substrate 20 having a flat surface, and each unit wiring layer including the first unit wiring layer 8 is formed. Each main surface is flattened, and an upper unit wiring layer is sequentially formed. Therefore, the circuit module 1 is the first unit wiring layer 8 to the fifth unit wiring layer 丨 2 to achieve high precision and high density, and to form each wiring pattern ', and to reduce the thickness. The circuit module 1 reduces the thickness of the multilayer wiring circuit portion 2 to shorten the wiring length between the connection and each of the semiconductor wafers 6a and 6B. 85727 -13-1232574, and 1 are formed in the layer wiring circuit section 2 to form a capacitor element 14, and a temporary technology it # 16〇 is stored. . The element 15 or the spiral inductor element 1 is dry 1 6 and the electric valley state element 14 is, for example, the middle 1 σ σ 2 for the purpose of decoupling the electric power source or cutting off the direct current component. Membrane composed of oxidized button (ding a. Chopped in cry-M,) pancreatic tick button (TaN) film, such as a terminal resistor material register, is composed of nitriding group = "This electrical. Road module 1 As described above, the first-layer unit wiring layer 8 to the early-stage wiring layer 12 are sequentially formed on the flat surface of the base substrate 20 or the lower unit wiring layer, so that a high-precision capacitor can be formed. 15 or sensor element 16. f-way module! By forming capacitor elements, register elements, or sensor elements using passive chip components in the multilayer wiring circuit unit 2 using conventional chip components, wiring can be shortened Long and extremely small and high-performance passive components. Although the circuit module i of the present invention is manufactured through a process described later, the first unit wiring layer 8 to the fifth unit wiring layer 12 each include a first The insulating layer 22, the second insulating layer 23, and the conductive metal layer 24. In this circuit module manufacturing process, the first The process of forming the unit wiring layer 8 to the fifth unit wiring layer 12 has a channel hole groove for forming a channel hole 13 for the first insulating layer 22 to form a process, and a part for forming a second insulating layer 23 with a channel hole. The process of forming the wiring grooves 27 of the wiring pattern 26 of the communication portion of the trench 25. In the process of the circuit module 1, the processes of the first unit wiring layer 8 to the fifth unit wiring layer 12 have a process of forming a second insulating layer. The copper plating process of the conductor metal layer 24 of 23 and the chemical-mechanical polishing (CMp • Chemical-Mechanical Polishing) process of polishing the conductor metal layer 24. In the process of the circuit module i ', the first unit wiring layer is passed through the above process. Units 8 to 5 are equipped with 85727 14 1232574 wire layer 12 to form wiring pattern 26 and channel hole 13. Regarding the circuit of the present invention, for the wiring circuit part 2 of the layer, the system layer is formed through the above process In addition, the upper, lower, and upper layers of the 五 -layer unit are composed of five early-stage wiring layers 12 to constitute the upper package semiconductor Ηαλ ^ ^ main surface 2a clothing ~ said semiconductor crystal resin layer 7 of 6A, 6B to seal these Guide clothes% and sealing resin layer used in sealing 〇0, and Japanese film 6A, 6B to form the process 0 circuit module 1 轺 女 1 female monk day / knife 乂 ^. + 4i The polishing process of semiconductor wafers A, 6B, and resin layer 7 is a process in which the base substrate 20 is peeled off from the multi-layer λ circuit section 2_off process to manufacture a circuit module. The process system of the circuit module 1 of the present invention, The-'insulating layer 22 and the first and second layers 23% and 23% form a channel hole trench 25 and a wiring trench 27 by a two-resolution lithography process. Through the process of the circuit module 1, compared with the conventional process, it is processed by k: a hole for a channel hole, and a pattern forming process of an open mask and a wet etching process or an electroplating process are used for the substrate forming the copper foil layer. Etc., forming a circuit module jade having channel holes 13 or wiring patterns 26, which can achieve high precision and sound reliability and homogeneity, miniaturization and miniaturization. With regard to the circuit module of this and the Ming, it is manufactured by using the above-mentioned process, thereby forming each channel hole U in the first unit wiring layer 8 to the fifth unit wiring layer 12 to a few μ 几, and each The wiring pattern% also has a very fine pitch of several steps. The circuit module 丨 can form impedance-controlled wiring patterns 26 by forming microstrip lines sandwiching the upper and lower layers with ground on the first unit wiring layer 8 to the fifth unit wiring layer 12, for example. / Compared with the circuit module manufactured by Shirai manufacturing method, the circuit module 1 manufactured by the manufacturing method of the present invention can reduce the area size to about 85727 -15-1232574, which can increase the use limit band to 20 GHz. . In the circuit mold of the present invention, the first unit wiring layer 8 to the fifth unit wiring layer 12 constituting the multilayer wiring circuit portion 2 are formed to a thickness of, for example, 5. The overall thickness of the multilayer wiring circuit portion 2 can also be reduced to Within a few tens of μιη. ^ Since the circuit module of the present invention, the semiconductor wafers 6A and 6B are also precisely and sharply polished to a thickness of about 0.1 mm, so they are significantly thinned. Each process of the method for manufacturing the circuit module 1 according to the present invention will be described in detail with reference to FIGS. 3 to 12. In the manufacturing process of the circuit module of the present invention, the base substrate 20 formed as shown in FIG. The base substrate 20 is formed of a base material such as a silicon substrate, a glass substrate, or a quartz substrate that has insulating properties, heat resistance, or chemical resistance, can form a high-precision flat surface, and has mechanical rigidity. By using such a substrate material, the base substrate 20 suppresses thermal changes against the surface temperature rise during processing described below, and maintains focus during lithography processing to improve the contact alignment characteristics of masking, and can produce high-precision circuits. Module 丨. In addition, the base substrate 20 is not limited to the above-mentioned substrates, and other appropriate substrate materials that have been subjected to a planarization process may be used. The base substrate 20 used in the manufacturing method of the present invention is subjected to a grinding process on the main surface 20a to form a flat surface having a high accuracy, and a peeling layer 21 film is formed on the main surface. The peeling layer 21 includes a metal thin film layer, which has a degree of about 10 ° on the main surface 20a of the base substrate 20 by, for example, a ore reduction method or a chemical vaporization method (CVD: Chemical Vapor DepOsitiOn). Uniform thickness and spread throughout: copper or Shao etc. formed on the surface; and resin film layer, which is a comprehensively formed thickness on this metal film layer by, for example, spin coating method ... ~ 2_degree poly85727 -16-1232574醯 imine resin and so on. In the peeling layer 21 described later, the multilayer wiring circuit portion 2 is peeled from the base substrate 20 with the first layer wiring layer 8 as a peeling surface. Regarding the manufacturing process of the circuit module of the present invention, a first unit wiring layer 8 is formed on the release layer 21. The manufacturing process of the first unit wiring layer 8 is shown in FIG. 3, and the manufacturing process of forming the first insulating layer 22 thin film on the release layer 21 of the base substrate 20 is the first manufacturing process. The first insulating layer 22 is made of, for example, a polyimide-based or ring 2-based negative-type photosensitive insulating resin material, and a uniform coating or thickness control coating can be applied, for example, a spin coating method, a curtain coating method, or a roll coating method. Or the dip coating method is used to form a film on the release layer 21 over the entire surface. The first insulating layer 22 is formed on the flat base substrate 20 through the flat release layer 21 and can be formed with a uniform thickness. The first unit wiring layer 8 is manufactured by applying a first lithography process and forming a via hole groove on the first insulating layer 22 corresponding to the via hole 13 as a second process. As shown in FIG. 4, the first lithography process includes a process of positioning a first photomask 30 on the surface of the first insulating layer 22, and exposing a first part of the first insulating layer 22 to a predetermined position through the first photomask 30. An exposure process and a first development process for developing the first insulating layer 22. As shown in FIG. 4, the first photomask 30 is made of a sheet-like material, and the sheet-like material is formed with the formation portion of the passage hole groove 25 corresponding to the passage hole 13 as the light-shielding portion 30 a, and other portions as The light-shielding and light-transmitting patterns of the light-transmitting portion 30b are arranged in a state of being positioned on the surface of the first insulating layer 22 and being in close contact with each other. The first exposure processing is performed by a suitable method such as a method of irradiating laser light for controlling operation in the χ-γ direction or a method of irradiating emitted light from a mercury lamp or the like. As shown in FIG. The portion 30b transmits 584 85727 -17-1232574 light [, which selectively exposes the first insulating layer 22. This first exposure process is applied to the first insulating layer 22 as shown by the dashed line in the figure. Except for the formation of one of the channel holes 、, the p knife is selectively exposed over the entire area in the thickness direction to be latent imaged. The first and first development treatments are performed by wrapping the base substrate 20 that has been subjected to, for example, the first exposure treatment: in an alkaline solution, as shown in FIG. 5, to remove the unexposed exposure of the first insulating layer 22: 'that is, forming each channel A part of the hole 13 forms a predetermined channel hole groove 25. The manufacturing process of one unit wiring layer 8 is to form the second insulating layer 23 on the third insulating layer 22 with the channel holes M formed thereon. As shown in FIG. 6, the second insulating layer 23 is formed. 23 is the same as the first insulating layer 22, using, for example, a polyimide-based or epoxy-based negative-type photosensitive insulating resin material, such as a spin coating method and a curtain coating method with a box cloth uniformity characteristic or a thickness control characteristic. The cloth-through method or the coating method is formed on the first insulating layer 22 with a uniform film thickness throughout the entire surface. As shown in FIG. 6, the insulating resin material is also filled in the channel holes 25 formed in the first insulating layer 22 by the first process. The first unit wiring layer 8 is manufactured by applying a second lithography process to form a wiring groove 27 on the first and second edge layers 23 corresponding to the wiring pattern 26 as a fourth process. As shown in FIG. 7, the second lithography process includes a process of disposing a second photomask 31 on the surface of the second insulating layer 23, a second exposure process of exposing a predetermined portion of the second insulating layer 23 through the second photomask 31, and A second development process for developing the second insulating layer u. The second photomask 3U0gj 7 is composed of a sheet material. The portion of the sheet material where the wiring groove corresponding to the wiring pattern 26 is formed is a light shielding portion 3ia, and the other portion is a light transmitting portion 31b. The light-shielding and light-transmitting patterns are arranged on the surface of the second insulating layer 23 and are in a close state. 585 85727 -18-1232574 The second exposure process also uses the same exposure device as the above-mentioned first exposure process, and the second insulating layer 23 is selectively exposed by the processing light transmitted through the light transmitting portion 31b of the second mask 31. The second exposure process is shown in dashed lines in FIG. 7, and the latent image is selectively exposed on the first, second, third, second, and third layers 23 and 3 except for the corresponding portion of the wiring pattern 26 across the entire thickness direction. Into. The second development treatment is performed by soaking the base substrate 20 subjected to, for example, the second exposure treatment in an alkaline solution. As shown in FIG. 8, the unexposed portion of the second insulation layer 23 is removed, that is, the channel holes are filled. The insulating resin material of 25 and the corresponding portion of the wiring pattern% are patterned together with the predetermined channel hole groove 25 to form the wiring groove 27. The first unit wiring layer 8 is manufactured by subjecting the first insulating layer 23 in which the channel holes 25 and the wiring grooves 27 are formed to a metal plating process to form a conductor metal layer 24 as a fifth process. The electro-metallic treatment can also be any of electrolytic plating or electrodeless plating. As shown in FIG. 9, the conductive metal is filled with the conductive metal into the wiring trench 27 together with the channel hole 25 and is completely formed in the second insulating layer η. Conductor metal layer 24 of the same thickness. Specifically, the processing of metal electric money is to apply the conductive metal layer 24 to form a copper film layer with good conductivity and use mineral copper. When the conductive metal layer 24 is formed by electrolytic money, the peeling layer 21 is used as a voltage application electrode. . The manufacturing process of the first early-stage wiring layer 8 is a sixth process in which the process of grinding the conductive metal layer M until the main surface of the second insulating layer 23 is exposed. The polishing process is to grind a part of the second insulating layer together with the conductive metal layer 24. As shown in FIG. 10, the first layer is flat and only the main surface 8a of the wiring layer 8 is formed into a flat surface. The polishing process is to simultaneously grind the second insulating layer 23 and the conductive metal bank 24, which are different in X π material. Therefore, the CMP method is used. The CMP method has an increased conductive metal layer 24 5Θ6 85727 -19- J232574 polishing rate. Grinding selectivity. The manufacturing process of the first unit wiring layer 8 is performed by the above-mentioned polishing process. As shown in FIG. 10, the conductor gold filled in the channel holes 25 and the wiring grooves 27, such as the copper layer and the second insulating layer 23 constitute the same. One unit wiring layer 8 is formed so as to form channel holes 13 and wiring patterns 26, respectively. As described above, the first unit wiring layer 8 is formed on the base substrate 20 with the second insulating layer 22 and the second insulating layer 23 with a high-precision thickness, and the first shadow processing and the second lithography applied with high resolution are used. The formed channel holes 25 and wiring grooves are processed to form the channel holes 13 and the wiring patterns 26. Therefore, the entire first unit wiring layer 8 is thinned and the wiring pattern 26 has a thickness equal to that of the second insulating layer 23, so that sufficient signal transmission characteristics can be maintained. The first unit wiring layer 8 and the channel holes 25 and the wiring grooves 27 are formed in the first insulating layer with high density, miniaturization, and miniaturization. The second insulating layer 23 and the second insulating layer 23 can form via holes 13 or wiring patterns 26 which are required to have a high density and are miniaturized and miniaturized. Although the first unit wiring layer 8 is omitted in detail, it is formed with connection pads or input / output electrodes that are packaged together with the wiring pattern 26 on a mother substrate ^. In the process of the first unit wiring layer §, the first insulating layer 22 and the second insulating layer 23 are formed by forming a negative photosensitive insulating resin material into a film, but a positive photosensitive insulating resin material may also be used. Film formation. In this kind of manufacturing, the first mask 30 or the second mask 31 has a portion corresponding to the passage hole groove 25 or a wiring groove 27 as a light transmitting portion and other portions as light shielding portions. In addition, during the first exposure process of this process, the first insulating layer 22 is exposed, so it is necessary to control the exposure amount. The process of 85727 -20- 1232574 circuit module ^ is a process of applying the second unit wiring layer 9 on the main surface of the first-level unit wiring layer 8 which is flattened. The second layer unit distribution = layer 9 is a process system. After forming the first edge layer 22 thin film on the main surface of the first layer unit wiring layer 8, the above-mentioned channel holes and grooves are formed by the first lithography process. A manufacturing process, a forming process of the second insulating layer 23, a manufacturing process of applying a second lithography process to form the wiring trenches 27, a forming process of the conductive metal layer μ, and a polishing process. Although the details of the manufacturing process of the second unit wiring layer 9 are omitted, the capacitor element 14 and the register element are also formed by an appropriate method. Or passive elements such as sensor element 16. In the manufacturing process of the circuit module 1, the process of applying the third unit wiring layer to the second unit wiring layer 9 is performed, and the formation process of the upper unit wiring layer is sequentially performed below, as shown in Figure 丨 丨A multilayer wiring circuit section 2 is fabricated on the base substrate 20. The multilayer wiring circuit section 2 is a channel hole 13 formed in the first unit wiring layer 8 to the fifth unit wiring layer 12 as shown in FIG. U. The upper-layer channel hole is directly formed on the lower-layer channel hole to form a channel. The hole has a channel hole structure. Therefore, the multilayer wiring circuit unit 2 can be connected between the first unit wiring layer 8 to the fifth unit wiring layer 12 with the shortest wiring length. The multilayer wiring circuit unit 2 forms upper unit wiring layers in order on the flattened lower unit wiring layer, thereby suppressing the influence of the accumulation of the wiring pattern thickness on the lower side. The upper fifth unit wiring layer 12. Therefore, the multilayer wiring circuit unit 2 can further form a high-precision unit wiring layer on the fifth unit wiring layer} 2 to achieve high accumulation. As shown in FIG. 12, in the manufacturing process of the circuit module 1, the main unit surface of the fifth unit wiring layer 12 constituting the second main surface 2 b of the multilayer wiring circuit portion 2 is packaged with a semiconductor chip 6A and 6B. Process. Although the details of the fifth unit wiring layer 12 are omitted, similar to the wiring pattern 26, an appropriate padding method such as a flip-chip packaging method is used to form electrode pads for packaging semiconductor wafers 6A and 6B, or for ordering and other electronics. Connection terminal parts for connection of parts and other modules. In addition, the electrode welding pad or the connection terminal + is subjected to terminal formation by, for example, electrodeless bonding / steel. Although the details of the semiconductor wafer packaging process are omitted, the processes and processes including the process of mounting the bumps 5 for electrode mounting and packaging of the semiconductor wafers 6A and 6B, and positioning and placing the semiconductor wafers 6A and 6B on the fifth unit wiring layer 12 In a process such as reflow soldering. In the manufacturing process of the circuit module 1, as shown in FIG. 12, a sealing process is performed, and the sealed semiconductor wafers 6A and 6B are sealed with a sealing resin layer 7. The sealing resin layer 7 is formed of a series of materials such as epoxy resin and the like having a low thermal curing shrinkage, and is formed by a transfer mold method or a printing method, and suppresses warping of the base substrate 20 or the multilayer wiring circuit portion 2 after curing. Stress such as bending is generated. _ Soil First, the manufacturing process of the circuit module 1 is a process of grinding the semiconductor wafer 6α, dipping, and sealing the resin layer 7 to a predetermined thickness. The polishing process is performed using, for example, a mechanical polishing method using a grinder, a chemical polishing method using a wet process, or a CMP using both a mechanical polishing method and a chemical polishing method. The semiconductor wafers 6A and 6B are aligned with the sealing resin layer 7 together. The surface is polished to the largest extent without hindrance, as shown in FIG. 13. The polishing process is based on the base substrate as a supporting substrate, and the semiconductor wafer 6A is sealed with the sealing resin layer 7, and the state polishing is performed so as to prevent the semiconductor wafers 6A and 6B from being damaged by defects such as edges. Although the manufacturing process of the circuit module 1 is omitted in detail, the 85270 -22-1232574 second base substrate with a release layer is bonded to the sealing resin layer 7 which has been subjected to a polishing treatment, and then the circuit module 1 is peeled off from the base substrate 20 丨Process. The second base substrate is a substrate on which the circuit module 1 is packaged on the mother substrate 3 and the like, and the electrode pads are formed on the main surface 2a-unit wiring layer 8 constituting the multilayer wiring circuit portion 9 or the flattening treatment is performed. The base substrate peeling process is performed by immersing the base substrate 20 forming the circuit module ^ through the above process in an acidic solution such as hydrochloric acid. The circuit module 1 is performed in an acidic solution at the metal thin film layer and the resin thin film boundary of the peeling layer 21, and is peeled from the base substrate 20 with the tree moon thin film layer left on the first unit wiring layer 8 side. . In addition, the peeling process can also be performed by, for example, applying laser elimination 14 to the circuit module! Paste from the base substrate. In addition, the resin thin film layer remaining on the first unit wiring layer 8 side is removed by, for example, a dry type inscription method such as oxygen electrocineration. An electrode formation process is performed on the wiring layer circuit part 2 of the first layer, which is formed on the surface of the connection pads of the first unit wiring layer 8 formed on the main surface 2a of the dew or the input / output terminals by electroless plating to form gold_nickel. Floor. The circuit module 1 is provided with a package bump 4 on a connection pad, and is reflowed in a state of being positioned on the mother substrate 3 to break the package. In addition, the circuit module is a peeling process of the first base substrate before the packaging process of the mother substrate 3. In the above process of the circuit module 丨, although it is explained that one circuit module is fabricated on the base substrate 20! Process, but it is also possible to use a relatively large base substrate 20 and make a plurality of circuit modules. In the manufacturing process of the circuit module 1, in this case, before the peeling process from the base substrate 20, a cutting process for separating the connection portions of the circuit modules 1 is performed. Also, in circuit modules! 85727 -23- 1232574 Although the electrical module 1 is fabricated on a base substrate 20 composed of a silicon substrate or a glass substrate, various organic materials used in the general multilayer substrate manufacturing process such as planarization can also be used. Substrate. The circuit module 1 of the present invention is configured as follows: The multilayer wiring circuit unit 2 also has a function as an insert for packaging the semiconductor wafers 6A and 6B, and it can of course be used as a single multilayer wiring circuit module. It is needless to say that the circuit module 1 may also seal a semiconductor wafer or a package part on the first main surface 2a side of the multilayer wiring circuit portion 2. In this case, the circuit module 1 is also subjected to a planarization process using the second base substrate as a base on the first to main surface 2a sides. In addition, the present invention is not limited to the above-mentioned embodiments described with reference to the drawings, and can be used in various ways without departing from the enclosed application section and installation. Changes, swaps, or equivalents will be apparent to those skilled in the art. The industrial utilization possibility is as described above. Each unit wiring layer of the present invention is made of a photosensitive insulating tree; a first insulating layer formed of a material is subjected to a photolithography process to form a channel hole and groove. ^ On this first insulating layer The wiring trench is formed by the second lithography process using a photosensitive insulating resin material, and the conductive metal formed on the second insulating layer like the channel hole trench and the distribution metal body is subjected to a grinding process so that—纟 g ramie. Κ The main surface of the 濠 seven-thickness layer is exposed, and the conductive metal filled in the channel hole is used to form a high-resolution lithography process for the channel hole. Tiny and subtle channel holes or edge patterns can be used with miniaturization to use the right, s ... on the channel holes, because the principle is clear, the layer, so the wiring length 配线 hole structure to connect the unit wiring with the shortest layer, m To reduce the attenuation of the transmitted signal, and at the same time reduce the delay of ^ > 1 1 85727 -24, 1232574 to the minimum, and also ... / this can be said for reliability, ^ '-noise effects , The response of borrowed buses . τ4 for large capacity, high speed, high density [Brief description of the drawings] Figure 1 is a longitudinal sectional view showing a conventional circuit module. Fig. 2 is a circuit diagram showing the circuit model of the present invention. Fig. 3 is a longitudinal sectional view of 邛 f. Bud-a vertical cross-sectional view of the insulating layer forming process. The figure is a longitudinal cross-sectional view showing the first exposure process performed on the first insulating layer. FIG. 5 is a longitudinal cross-sectional view showing the first development process performed on the first insulating layer. FIG. 6 is a view showing FIG. 8 is a longitudinal cross-sectional view showing the first longitudinal cross-sectional view of the insulating layer forming process: a longitudinal cross-section of the second exposure process performed by the insulating layer, and a longitudinal cross-sectional insulating layer of the second development process performed by the insulating layer. Schematic diagram of the process of forming a conductive metal layer: a longitudinal sectional view showing a chemical-mechanical buckle applied to the conductive metal layer. Magic Research Graph] is the% + π surface graph. ..., > Vertical section of a multilayer wiring circuit portion formed on a base substrate. Fig. 12 is a vertical sectional view showing a semiconductor. Manufacturing process for bulk chip packaging in a multilayer wiring circuit section 85727 -25 · 1232574 Fig. 13 is a longitudinal sectional view showing a polishing process of polishing a semiconductor wafer and a sealing resin layer. [Illustration of Symbols in Drawings] 1 Circuit module 2 Multilayer wiring circuit part 2a First main surface 2b Second main surface 3 Mother substrate 4 Encapsulation bump 5 Semiconductor encapsulation bump 6A, 6B Semiconductor wafer 7 Sealing resin layer 8 First unit wiring layer 8a Main surface 9 Second unit wiring layer 10 Third unit wiring layer 11 Fourth unit wiring layer 12 Fifth unit wiring layer 13 Channel hole 14 Capacitor element 15 Register element 16 Induction Device element 20 base substrate 20a main surface 85727.doc -26- 1232574 21 peeling layer 22 first insulating layer 23 second insulating layer 24 conductive metal layer 25 channel hole 26 wiring pattern 27 wiring groove 30 first mask 30a light shielding portion 30b Light transmitting part 31 Second photomask 31a Light shielding part 31b Light transmitting part 100 Multi-chip circuit 101 Insert 101a Main surface 101a, 101b Front and reverse main surface 102A, 102B Semiconductor wafer 103 Soldering area 104 Filling material 105 Solder ball S14 85727- 27-

Claims (1)

1232574 拾、申請專利範圍： L -種多層配線電路模組，係多數層單位配線層透過多數 個通迢孔互相層間連接而層疊形成，其特徵在於： 上述各單位配線層包含·· 第一絕緣層··用感光性絕緣樹脂材料成膜形成，被 施以微影處理而形成有與上述各通道孔對應的多數個 通道孔溝； 弟—絕緣層··在上述第—絕緣層上用感光性絕緣樹 脂材料成膜形成，被施以微影處理而圖案形成有配線 溝，其與在-部分具有和上述各通道孔溝的連通部的 配線圖案對應；及 導體金屬層··在上述第二絕緣層上，在上述各通道 孔溝和上述配線溝内都填充導體金屬而成膜形成，· *用導體金屬形成上述各通道孔和上述配線圖案，該 導體金屬係填充於施以研磨處理到使上述第二絕緣層 的主面露出，而在此第二絕緣層的主面構成與其同一 面露出的上料體金屬層的上述各通道孔溝和上述配 線溝内者。 2.如申請專利範圍第㈣之多層配線電路模組，其中上述第 絶緣層和第二絕緣層用負型感光性絕緣樹脂材料成膜 形成。 3·如申請專利範圍第1項之多層配線電路模組，其中上述導 體金屬層被施以化學·機械研磨法的研磨處理。 4·如申請專利範圍第1項之多層配線電路模組，其中上述導 85727 1232574 體金屬層係用鍍銅形成的銅膜層。 5.如申請專利範圍第！項之多層配線電路模組，里中最下層 的上述單位配線層形成於基底基板上，其具有成膜職 於平坦主面上的剝離層’層疊形成特定層後，透過上述 剝離層被剝離。 6.1232574 Patent application scope: L-A type of multilayer wiring circuit module, which is formed by stacking a plurality of unit wiring layers through a plurality of through-holes to connect to each other in layers. The characteristics are as follows: each unit wiring layer includes the first insulation The layer is formed by forming a film from a photosensitive insulating resin material, and is subjected to a lithography process to form a plurality of channel holes corresponding to the above-mentioned channel holes. The younger-insulating layer is provided with a photosensitive layer on the first insulating layer. The insulating insulating resin material is formed into a film, and is subjected to a lithography process to form a patterned wiring groove corresponding to a wiring pattern having a communicating portion with the above-mentioned each channel hole in a-portion; and a conductive metal layer. On the two insulating layers, each of the above-mentioned channel holes and the above-mentioned wiring grooves are filled with a conductive metal to form a film, and the * each of the above-mentioned channel holes and the above-mentioned wiring patterns are formed with a conductive metal, and the conductive metal is filled with a polishing The above-mentioned passages until the main surface of the second insulating layer is exposed, and the main surface of the second insulating layer constitutes the upper metal layer exposed on the same surface. Channel hole groove and the inside of the above-mentioned distribution groove. 2. The multilayer wiring circuit module according to the scope of the patent application, wherein the first insulating layer and the second insulating layer are formed by forming a negative photosensitive insulating resin material into a film. 3. The multilayer wiring circuit module according to item 1 of the patent application range, wherein the above-mentioned conductive metal layer is subjected to a polishing treatment by a chemical / mechanical polishing method. 4. The multilayer wiring circuit module according to item 1 of the scope of patent application, wherein the conductive layer 85727 1232574 is a copper film layer formed by copper plating. 5. If the scope of patent application is the first! In the multilayer wiring circuit module of the item, the lowermost unit wiring layer above is formed on a base substrate, and it has a film-forming peeling layer on a flat main surface, which is laminated to form a specific layer, and then peeled through the peeling layer. 6. 如申請專利範圍第！項之多層配線電路模組，其中在最上 層的上述單位配線層安裝有IC晶片、LSI或安褒零件。 -種多層配線電路模組之製造方法，係多數層單位配線 層透過多數個通道孔互相層間連接而層疊形成的多層配 線電路模組之製造方法，其特徵在於： 上述各單位配線層的形成製程包含以下製程： 用感光性絕緣樹脂材料形成第一絕緣層，· 、對於上述第一絕緣層施以微影處理而形成與上述各 通道孔對應的多數個通道孔溝； 在上述第—絕緣層上全面塗佈感光性絕緣樹脂材料 而成膜形成第二絕緣層； 對於上述第二絕緣層施以微影處理而形成配線溝， _在。卩刀具有和上述各通道孔溝的連通部的配線 圖案對應； 、 在上述第一絶緣層上，在上述各通道孔溝和上述配 次溝内都填充導體金屬而全面成膜形成導體金屬層； 及， 出 研磨上述導體金屬層到使上述第 一絕緣層的主面露 85727 1232574 用導體金屬形成上述各 導體金屬係填充於扩以 ^酉己線圖案’該 真充於施以上述研磨處理而 緣層的主面構成盥苴冋 ^ ^ f I弟一、、、巴 菁成…、同-面路出的上述導體金屬層的 上述各通運孔溝和上述配線溝内， 丄L的上述單位配線層係將上述第-絕緣層成膜 ;土 -土反上’上層的上述單位配線層係將各上述第 -絕緣層成膜於下層的上述單位配線層的上述第二絕 緣層上者。 女申明專利乾圍第7項之多層配線電路模組之製造方法 制其中用於上述第一絕緣層形成製程和第二絕緣層形成 2 '專利範圍第7項之多層配線電路模組之製造方法 八中對於上述導體金屬層的研磨製程係化學-機械研磨 法的研磨處理。 士申明專利範圍第7項之多層配線電路模組之製造方法 γ其中在上述各第二絕緣層上形成導體金屬層的製程係 施以鍍銅而形成鋼膜層的製程。 11.如申請專利範圍第7項之多層配線電路模組之製造方法 ，其中第一層的上述單位配線層形成製程係在將剝離層 成膜形成於平坦主面上的基底基板上進行， 形成特定層的上述單位配線層後，具有透過上述剝離 層被剝離的製程。 1 2·如申清專利範圍第7項之多層配線電路模組之製造方法 ’其中具有下述製程：在最上層的上述單位配線層安裝 IC晶片、LSI或安裝零件。 85727Such as the scope of patent application! In the multilayer wiring circuit module of this item, an IC chip, an LSI, or a security component is mounted on the uppermost unit wiring layer. A manufacturing method of a multilayer wiring circuit module, which is a manufacturing method of a multilayer wiring circuit module in which a plurality of unit wiring layers are connected to each other through a plurality of channel holes to be layered with each other, and is characterized in that the formation process of each unit wiring layer is described above. The process includes the following steps: forming a first insulating layer with a photosensitive insulating resin material, and applying a lithographic treatment to the first insulating layer to form a plurality of channel holes corresponding to the respective channel holes; in the first insulating layer The second insulating layer is formed by coating the entire surface with a photosensitive insulating resin material, and a lithography process is performed on the second insulating layer to form a wiring groove. The trowel has a wiring pattern corresponding to the communication portion of each of the channel holes and grooves; and, on the first insulating layer, the channel holes and the distribution grooves are filled with a conductive metal to form a conductive metal layer on the entire surface. And grinding the conductive metal layer to expose the main surface of the first insulating layer 85727 1232574 forming each of the conductive metal with the conductive metal and filling it with a ^ 酉 line pattern; the true charge is subjected to the above-mentioned polishing treatment; The main surface of the edge layer constitutes the following: In the above-mentioned transportation holes and the above-mentioned wiring grooves of the above-mentioned conductive metal layer, the above-mentioned conductor metal layer is the same as the above-mentioned one. The unit wiring layer is formed by forming the above-mentioned first insulation layer; the upper-layer unit wiring layer is formed by forming each of the above-mentioned first insulation layer on the second insulation layer of the unit wiring layer below. . Female declares that the manufacturing method of the multilayer wiring circuit module of the seventh item of the patent patent is the manufacturing method of the multilayer wiring circuit module of the seventh item of the first insulating layer forming process and the second insulating layer forming 2 of the patent scope. The polishing process of the above-mentioned conductive metal layer in the eighth middle is a chemical-mechanical polishing method. The method for manufacturing a multilayer wiring circuit module according to the patent claim No. 7 γ wherein the process of forming a conductive metal layer on each of the above-mentioned second insulation layers is a process of forming a steel film layer by copper plating. 11. The manufacturing method of the multilayer wiring circuit module according to item 7 of the scope of patent application, wherein the above-mentioned unit wiring layer forming process of the first layer is performed on a base substrate formed by forming a release layer on a flat main surface to form After the unit wiring layer of the specific layer is formed, a process of peeling through the release layer is provided. 1 2 · The manufacturing method of the multilayer wiring circuit module as described in item 7 of the Patent Scope, which has the following process: IC chips, LSIs, or mounting parts are mounted on the above-mentioned unit wiring layer. 85727
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7687312B2 (en) 2006-12-06 2010-03-30 Princo Corp. Method of manufacturing hybrid structure of multi-layer substrates

Families Citing this family (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7237217B2 (en) * 2003-11-24 2007-06-26 International Business Machines Corporation Resonant tree driven clock distribution grid
JP2005340655A (en) * 2004-05-28 2005-12-08 Shinko Electric Ind Co Ltd Method for manufacturing semiconductor device, and structure for supporting semiconductor substrate
JP4865197B2 (en) 2004-06-30 2012-02-01 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
SG119230A1 (en) * 2004-07-29 2006-02-28 Micron Technology Inc Interposer including at least one passive element at least partially defined by a recess formed therein method of manufacture system including same and wafer-scale interposer
JP4596846B2 (en) * 2004-07-29 2010-12-15 三洋電機株式会社 Circuit device manufacturing method
JP4431747B2 (en) * 2004-10-22 2010-03-17 富士通株式会社 Manufacturing method of semiconductor device
JP4790297B2 (en) * 2005-04-06 2011-10-12 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US7719103B2 (en) * 2005-06-30 2010-05-18 Semiconductor Energy Laboratory Co., Ltd Semiconductor device
JP4787559B2 (en) * 2005-07-26 2011-10-05 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
JP2007059878A (en) * 2005-07-27 2007-03-08 Seiko Epson Corp Semiconductor device, and oscillator
JP4838068B2 (en) * 2005-09-01 2011-12-14 日本特殊陶業株式会社 Wiring board
US7742314B2 (en) * 2005-09-01 2010-06-22 Ngk Spark Plug Co., Ltd. Wiring board and capacitor
JP4829585B2 (en) * 2005-10-12 2011-12-07 日本電気株式会社 Wiring board and semiconductor device
US7637009B2 (en) 2006-02-27 2009-12-29 Sv Probe Pte. Ltd. Approach for fabricating probe elements for probe card assemblies using a reusable substrate
GB0604026D0 (en) * 2006-02-28 2006-04-12 Airbus Uk Ltd Aircraft wing
US20070257339A1 (en) * 2006-05-08 2007-11-08 Taiwan Semiconductor Manufacturing Co., Ltd. Shield structures
JP4431123B2 (en) * 2006-05-22 2010-03-10 日立電線株式会社 Electronic device substrate and manufacturing method thereof, and electronic device and manufacturing method thereof
JP2008085089A (en) * 2006-09-28 2008-04-10 Matsushita Electric Ind Co Ltd Resin wiring board and semiconductor device
JP2008091639A (en) * 2006-10-02 2008-04-17 Nec Electronics Corp Electronic equipment, and manufacturing method thereof
US7991157B2 (en) * 2006-11-16 2011-08-02 Digimarc Corporation Methods and systems responsive to features sensed from imagery or other data
JP2008258520A (en) * 2007-04-09 2008-10-23 Shinko Electric Ind Co Ltd Method of manufacturing wiring substrate, and wiring substrate
EP1986238A3 (en) * 2007-04-27 2010-12-29 Semiconductor Energy Laboratory Co., Ltd. Resin molded optical semiconductor device and corresponding fabrication method
US7869225B2 (en) * 2007-04-30 2011-01-11 Freescale Semiconductor, Inc. Shielding structures for signal paths in electronic devices
JP5054440B2 (en) * 2007-06-15 2012-10-24 新光電気工業株式会社 Manufacturing method of electronic component built-in substrate and electronic component built-in substrate
US20090094754A1 (en) * 2007-08-31 2009-04-16 Hall Iii Walter Randall Foam core article with flexible heat-resistant knitted fabric
JP4434268B2 (en) * 2007-11-28 2010-03-17 Ｔｄｋ株式会社 Electronic component module
US9460951B2 (en) 2007-12-03 2016-10-04 STATS ChipPAC Pte. Ltd. Semiconductor device and method of wafer level package integration
US10074553B2 (en) * 2007-12-03 2018-09-11 STATS ChipPAC Pte. Ltd. Wafer level package integration and method
JP2009188011A (en) * 2008-02-04 2009-08-20 Nec Electronics Corp Method and apparatus of manufacturing flip chip semiconductor device
JP4981712B2 (en) * 2008-02-29 2012-07-25 新光電気工業株式会社 Wiring board manufacturing method and semiconductor package manufacturing method
IL194967A0 (en) * 2008-10-28 2009-08-03 Orbotech Ltd Producing electrical circuit patterns using multi-population transformation
JP5578797B2 (en) * 2009-03-13 2014-08-27 ルネサスエレクトロニクス株式会社 Semiconductor device
JP5496541B2 (en) * 2009-04-20 2014-05-21 ルネサスエレクトロニクス株式会社 Semiconductor device
JP5171726B2 (en) * 2009-05-11 2013-03-27 ルネサスエレクトロニクス株式会社 Semiconductor device
US20100289132A1 (en) * 2009-05-13 2010-11-18 Shih-Fu Huang Substrate having embedded single patterned metal layer, and package applied with the same, and methods of manufacturing of the substrate and package
JP5275192B2 (en) 2009-09-28 2013-08-28 ローム株式会社 Semiconductor device manufacturing method, semiconductor device, and wafer laminated structure
US8786062B2 (en) 2009-10-14 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package and process for fabricating same
US20110084372A1 (en) * 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Package carrier, semiconductor package, and process for fabricating same
JP5091221B2 (en) * 2009-12-28 2012-12-05 ルネサスエレクトロニクス株式会社 Semiconductor device
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
JP5570855B2 (en) * 2010-03-18 2014-08-13 新光電気工業株式会社 Wiring substrate and manufacturing method thereof, semiconductor device and manufacturing method thereof
TWI411075B (en) 2010-03-22 2013-10-01 Advanced Semiconductor Eng Semiconductor package and manufacturing method thereof
US8698303B2 (en) 2010-11-23 2014-04-15 Ibiden Co., Ltd. Substrate for mounting semiconductor, semiconductor device and method for manufacturing semiconductor device
CN102625603A (en) * 2011-01-13 2012-08-01 讯忆科技股份有限公司 Line layer adding method and structure of multilayer circuit board
TWM408911U (en) * 2011-01-13 2011-08-01 Mao Bang Electronic Co Ltd Multilayer circuit board structure
JP5827476B2 (en) * 2011-03-08 2015-12-02 株式会社東芝 Semiconductor module and manufacturing method thereof
US8552567B2 (en) 2011-07-27 2013-10-08 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
US8937309B2 (en) * 2011-08-08 2015-01-20 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
US10475759B2 (en) * 2011-10-11 2019-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure having dies with connectors of different sizes
JP5516619B2 (en) * 2012-02-27 2014-06-11 イビデン株式会社 Manufacturing method of electronic parts
US9111998B2 (en) 2012-04-04 2015-08-18 Samsung Electronics Co., Ltd Multi-level stack having multi-level contact and method
KR101411813B1 (en) 2012-11-09 2014-06-27 앰코 테크놀로지 코리아 주식회사 Semiconductor device and manufacturing method thereof
US9287162B2 (en) 2013-01-10 2016-03-15 Samsung Austin Semiconductor, L.P. Forming vias and trenches for self-aligned contacts in a semiconductor structure
US10115661B2 (en) * 2013-02-08 2018-10-30 Qualcomm Incorporated Substrate-less discrete coupled inductor structure
US9237648B2 (en) 2013-02-25 2016-01-12 Invensas Corporation Carrier-less silicon interposer
US9502336B2 (en) * 2013-03-13 2016-11-22 Intel Corporation Coreless substrate with passive device pads
JP2015065553A (en) * 2013-09-25 2015-04-09 株式会社東芝 Connection member, semiconductor device, and laminate structure
US9691693B2 (en) 2013-12-04 2017-06-27 Invensas Corporation Carrier-less silicon interposer using photo patterned polymer as substrate
US9679841B2 (en) * 2014-05-13 2017-06-13 Qualcomm Incorporated Substrate and method of forming the same
JP6374338B2 (en) * 2015-03-24 2018-08-15 京セラ株式会社 Wiring board
US10074630B2 (en) * 2015-04-14 2018-09-11 Amkor Technology, Inc. Semiconductor package with high routing density patch
US9437536B1 (en) 2015-05-08 2016-09-06 Invensas Corporation Reversed build-up substrate for 2.5D
US10211160B2 (en) 2015-09-08 2019-02-19 Invensas Corporation Microelectronic assembly with redistribution structure formed on carrier
US9666560B1 (en) * 2015-11-25 2017-05-30 Invensas Corporation Multi-chip microelectronic assembly with built-up fine-patterned circuit structure
TWI652778B (en) * 2016-01-27 2019-03-01 艾馬克科技公司 Semiconductor package and method of manufacturing same
US20180166294A1 (en) * 2016-12-13 2018-06-14 Intel Corporation Apparatus and methods to achieve uniform package thickness
KR102639101B1 (en) * 2017-02-24 2024-02-22 에스케이하이닉스 주식회사 Semiconductor package having electro-magnetic interference shielding structure
JP6826947B2 (en) * 2017-05-18 2021-02-10 新光電気工業株式会社 Wiring board, manufacturing method of wiring board
US20190006457A1 (en) * 2017-06-29 2019-01-03 Intel Corporation Package integrated passives
EP3653027A4 (en) 2017-07-13 2021-04-28 CelLink Corporation Interconnect circuit methods and devices
JP7375274B2 (en) * 2019-06-10 2023-11-08 Ｔｏｐｐａｎホールディングス株式会社 Wiring board and wiring board manufacturing method
JP2021082791A (en) * 2019-11-22 2021-05-27 本田技研工業株式会社 Semiconductor device
US11688668B2 (en) 2019-12-31 2023-06-27 At&S (China) Co. Ltd. Component carrier with low shrinkage dielectric material
CN114245597A (en) * 2020-09-09 2022-03-25 鹏鼎控股(深圳)股份有限公司 Method for manufacturing circuit board with embedded conductive circuit

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4336088A (en) * 1980-06-30 1982-06-22 International Business Machines Corp. Method of fabricating an improved multi-layer ceramic substrate
US5266446A (en) * 1990-11-15 1993-11-30 International Business Machines Corporation Method of making a multilayer thin film structure
CA2059020C (en) * 1991-01-09 1998-08-18 Kohji Kimbara Polyimide multilayer wiring board and method of producing same
US5231751A (en) * 1991-10-29 1993-08-03 International Business Machines Corporation Process for thin film interconnect
JPH06102410A (en) * 1992-09-21 1994-04-15 Matsushita Electric Ind Co Ltd Pattern forming method
US5386627A (en) * 1992-09-29 1995-02-07 International Business Machines Corporation Method of fabricating a multi-layer integrated circuit chip interposer
US5600103A (en) * 1993-04-16 1997-02-04 Kabushiki Kaisha Toshiba Circuit devices and fabrication method of the same
US5485038A (en) * 1993-07-15 1996-01-16 Hughes Aircraft Company Microelectronic circuit substrate structure including photoimageable epoxy dielectric layers
EP0657932B1 (en) * 1993-12-13 2001-09-05 Matsushita Electric Industrial Co., Ltd. Chip package assembly and method of production
JPH08148828A (en) * 1994-11-18 1996-06-07 Hitachi Ltd Thin film multilayered circuit board and its manufacture
US5534466A (en) * 1995-06-01 1996-07-09 International Business Machines Corporation Method of making area direct transfer multilayer thin film structure
JP2748890B2 (en) * 1995-06-14 1998-05-13 日本電気株式会社 Organic resin multilayer wiring board and method of manufacturing the same
JP4095731B2 (en) * 1998-11-09 2008-06-04 株式会社ルネサステクノロジ Semiconductor device manufacturing method and semiconductor device
JP3790063B2 (en) 1999-03-08 2006-06-28 新光電気工業株式会社 Multilayer wiring board, manufacturing method thereof, and semiconductor device
US6400576B1 (en) * 1999-04-05 2002-06-04 Sun Microsystems, Inc. Sub-package bypass capacitor mounting for an array packaged integrated circuit
JP2001044589A (en) * 1999-07-30 2001-02-16 Nitto Denko Corp Circuit board
JP2001077543A (en) * 1999-09-03 2001-03-23 Fujitsu Ltd Multilayer wiring board
TW512653B (en) * 1999-11-26 2002-12-01 Ibiden Co Ltd Multilayer circuit board and semiconductor device
JP2001267747A (en) * 2000-03-22 2001-09-28 Nitto Denko Corp Manufacturing method for multi-layered circuit board
KR20020033190A (en) * 2000-07-21 2002-05-04 후지다 히로미찌 Insulating resin composition for multilayer printed wiring boards, multilayer printed wiring boards made by using the composition and process for the production thereof
JP4701506B2 (en) * 2000-09-14 2011-06-15 ソニー株式会社 Circuit block body manufacturing method, wiring circuit device manufacturing method, and semiconductor device manufacturing method
US6577490B2 (en) * 2000-12-12 2003-06-10 Ngk Spark Plug Co., Ltd. Wiring board
US6753612B2 (en) * 2001-04-05 2004-06-22 International Business Machines Corporation Economical high density chip carrier
JP3861669B2 (en) * 2001-11-22 2006-12-20 ソニー株式会社 Manufacturing method of multichip circuit module
US6891266B2 (en) * 2002-02-14 2005-05-10 Mia-Com RF transition for an area array package
JP4045143B2 (en) * 2002-02-18 2008-02-13 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド Manufacturing method of wiring film connecting member and manufacturing method of multilayer wiring board
TW558823B (en) * 2002-04-10 2003-10-21 Via Tech Inc Through-hole process of integrated circuit substrate
JP4056854B2 (en) * 2002-11-05 2008-03-05 新光電気工業株式会社 Manufacturing method of semiconductor device
JP4072505B2 (en) * 2003-02-28 2008-04-09 エルピーダメモリ株式会社 Stacked semiconductor package
JP4106438B2 (en) * 2003-06-20 2008-06-25 独立行政法人産業技術総合研究所 Multilayer fine wiring interposer and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7687312B2 (en) 2006-12-06 2010-03-30 Princo Corp. Method of manufacturing hybrid structure of multi-layer substrates

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