JP2021082791A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device that enables accurate signal input/output by suppressing the effect of reflected noise due to high signal speeds.SOLUTION: A semiconductor device includes a first semiconductor chip, a second semiconductor chip that controls the first semiconductor chip, and an interposer 4 on which the first semiconductor chip and the second semiconductor chip are mounted. The interposer 4 has a signal line 21 electrically connecting between the first semiconductor chip and the second semiconductor chip, a power line or ground line 22 electrically connected to the signal line 21, and a termination resistor 23 inserted between the signal line 21 and the power line or ground line 22.SELECTED DRAWING: Figure 2

Description

The present invention relates to a semiconductor device.

In recent years, HBM (High Bandwidth Memory), in which DRAM (Dynamic Random Access Memory) chips are laminated to expand the bandwidth and increase the speed, has been attracting attention. The current HBM2 has 4 chips and 1024 I / O channels. In the future, in order to reach the speed of the CPU / GPU, which will be further increased in speed, it is necessary to increase the number of input / output I / Os and increase the speed of the signal line.

As the speed of the signal increases, reflected noise such as overshoot, undershoot, and ringing appears in the voltage between the driver that sends the signal and the receiver that receives the signal. That is, both of them should be almost trapezoidal signals, but reflection occurs and the signals are distorted.

Therefore, due to the influence of such reflected noise, accurate input / output of signals becomes difficult. Also, this electrical problem becomes more pronounced as the signal speeds up.

Japanese Unexamined Patent Publication No. 2010-258301 Japanese Unexamined Patent Publication No. 2003-204016 Japanese Unexamined Patent Publication No. 2001-015655

The present invention has been proposed in view of such conventional circumstances, and is a semiconductor device capable of accurately inputting and outputting signals by suppressing the influence of reflected noise due to high-speed signals. The purpose is to provide.

In order to achieve the above object, the present invention provides the following means.
(1) The semiconductor device according to one aspect of the present invention includes a first semiconductor chip, a second semiconductor chip that controls the first semiconductor chip, the first semiconductor chip, and the second semiconductor chip. The interposer includes a signal line that electrically connects the first semiconductor chip and the second semiconductor chip, and a power supply that is electrically connected to the signal line. It is characterized by having a wire or a ground wire and a termination resistor inserted between the signal wire and the power supply wire or the ground wire.

(2) The semiconductor device according to (1) is provided with a plurality of terminating resistors having different resistance values, and one terminating resistor selected from the plurality of terminating resistors is the signal line and the terminating resistor. It is characterized by being electrically connected to a power line or a ground line.

(3) The semiconductor device according to (1) is provided with a plurality of terminating resistors electrically connected in series, and at least one or more terminating resistors selected from the plurality of terminating resistors. Is electrically connected between the signal line and the power supply line or the ground line.

(4) In the semiconductor device according to any one of (1) to (3), the interposer is provided with a first wiring layer provided with the signal line and the power supply line or ground line. The second wiring layer and the third wiring layer provided with the terminating resistor are each composed of a multilayer wiring board laminated via an interlayer insulating layer, and between the signal line and the terminating resistor. The power supply line or ground line and the terminating resistor are electrically connected to each other via a contact plug penetrating the interlayer insulating layer in the thickness direction.

(5) In the semiconductor device according to (4), the third wiring layer contains polysilicon.

(6) In the semiconductor device according to any one of (1) to (5), the signal line transmits / receives a signal between the first semiconductor chip and the second semiconductor chip. It is a transmission line to be performed, and the terminating resistor is arranged on the terminal side of the transmission line and has a resistance value matched to the characteristic impedance of the transmission line.

As described above, according to the present invention, it is possible to provide a semiconductor device capable of accurately inputting / outputting a signal by suppressing the influence of reflected noise due to the speeding up of the signal.

It is sectional drawing which shows the structure of the semiconductor device which concerns on one Embodiment of this invention. It is a schematic diagram which shows the electrical connection relationship between the 1st semiconductor chip and the 2nd semiconductor chip of the interposer included in the semiconductor device shown in FIG. 1. It is a circuit diagram which shows the arrangement of the terminating resistor provided in the interposer shown in FIG. 2, (A) the configuration which arranged the pull-up type terminating resistor, and (B) the configuration which arranged the pull-down type terminating resistor. .. It is a circuit diagram which shows the structure which arranged the pull-up type and pull-down type terminating resistors. It is a schematic diagram which shows the electrical connection relation when a plurality of terminating resistors having different resistance values are provided. It is a schematic diagram which shows the electrical connection relation when a plurality of terminating resistors connected in series electrically are provided.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In addition, in the drawings used in the following description, in order to make the features easy to understand, the featured parts may be schematically shown for convenience, and the dimensional ratio of each component is not always the same as the actual one. Absent.

As an embodiment of the present invention, for example, the semiconductor device 1 shown in FIG. 1 will be described.
As shown in FIG. 1, the semiconductor device 1 of the present embodiment is a semiconductor package called an HBM, and is a first semiconductor chip 2 and a second semiconductor chip 3, a first semiconductor chip 2 and a second semiconductor. It includes an interposer 4 in which the chip 3 is mounted on one surface (upper surface in the present embodiment), and a package substrate 5 in which the interposer 4 is mounted on one surface (upper surface in the present embodiment).

In the first semiconductor chip 2, for example, a plurality of (four in this embodiment) memory chips 6 on which a DRAM circuit or the like is formed are placed on a logic chip 7 in which a logic circuit or the like for controlling each memory chip 6 is formed. It is composed of a chip laminate laminated on.

The first semiconductor chip 2 includes a plurality of through electrodes (TSVs) 8 that penetrate each of the memory chips 6 and the logic chip 7 in the thickness direction, and bump electrodes provided between the plurality of memory chips 6 and the logic chips 7. Has 9 and. In the first semiconductor chip 2, the through electrodes 8 are electrically connected to each other via the bump electrodes 9.

The second semiconductor chip 3 controls the first semiconductor chip 2, and is composed of, for example, a host processor such as a CPU, GPU, or SoC. The first semiconductor chip 2 and the second semiconductor chip 3 are electrically connected to the interposer 4 via a plurality of bump electrodes 10 arranged in an array on the surface of the interposer 4.

The interposer 4 is composed of, for example, a multilayer wiring board in which a plurality of wiring layers 13 are laminated on a Si substrate 11 via an interlayer insulating layer 12. Further, the wiring layer 13 and the bump electrode 10 are electrically connected via a contact plug 14 penetrating the interlayer insulating layer 12 in the thickness direction. As a result, in the interposer 4, the first semiconductor chip 2 and the second semiconductor chip 3 are electrically connected to each other.

The interposer 4 has a through electrode (TSV) 15 that penetrates the Si substrate 11 in the thickness direction. Further, the wiring layer 13 and the through electrode (TSV) 15 are electrically connected via a contact plug 16 penetrating the interlayer insulating layer 12 in the thickness direction.

The interposer 4 is electrically connected to the package substrate 5 via a plurality of bump electrodes 17 arranged in an array on the surface of the package substrate 5. The wiring layer 13 and the bump electrode 17 are electrically connected via a through electrode (TSV) 15. As a result, in the interposer 4, the first semiconductor chip 2 and the second semiconductor chip 3 are electrically connected to the package substrate 5.

The package substrate 5 is composed of a printed wiring board (PCB), and has a plurality of solder balls 18 called BGAs (Ball Grid Arrays) on the other surface (lower surface in this embodiment) of the package substrate 5 as external connection terminals. doing.

By the way, as shown in FIG. 2, the semiconductor device 1 of the present embodiment has a plurality of signal lines 21 that electrically connect the first semiconductor chip 2 and the second semiconductor chip 3 in the interposer 4. It has a power supply line or ground line 22 that is electrically connected to each signal line 21, and a terminating resistor 23 that is inserted between each signal line 21 and the power supply line or ground line 22.

The signal line 21 forms a transmission line such as an I / O line that inputs / outputs signals between the first semiconductor chip 2 and the second semiconductor chip 3. The power supply line or the ground line 22 forms a power supply line 22 to which the power supply potential Vcc is given and a ground wire 22 to which the ground potential Vss or GND is given. The terminating resistor 23 is arranged on the terminal side of the signal line 21, and the reflection on the signal line 21 is prevented by so-called impedance matching that matches the resistance value with the characteristic impedance of the signal line 21.

In the semiconductor device 1 of the present embodiment, by inserting a terminating resistor 23 between the signal line 21 and the power supply line or the ground line 22, signal input / output can be performed while suppressing the influence of reflected noise due to the speeding up of the signal. It can be done accurately.

In the configuration in which the pull-up type terminating resistor 23 is arranged, as shown in FIG. 3A, when there is no input in the signal line 21, the high (Hi) level voltage (for example, the power supply potential Vcc) is set. Therefore, the power supply line 22 having the power supply potential Vcc and the signal line 21 are electrically connected via the terminating resistor 23.

On the other hand, in the configuration in which the pull-down type terminating resistor 23 is arranged, as shown in FIG. 3 (B), when there is no input in the signal line 21, a low level voltage (for example, ground potential Vss or GND) is used. Therefore, the ground line 22 and the signal line 21 having the ground potential Vss or GND are electrically connected via the terminating resistor 23.

Further, as shown in FIG. 4, both the pull-up type terminating resistor 23 and the pull-down type terminating resistor 23 described above may be arranged.

In the semiconductor device 1 of the present embodiment, as shown in FIG. 5, a plurality of terminating resistors 23 having different resistance values R1, R2, and R3 are provided, and one terminating resistor selected from the plurality of terminating resistors 23. The 23 may be electrically connected between the signal line 21 and the power supply line or the ground line 22.

In the case of this configuration, a terminating resistor 23 having a resistance value matching the characteristic impedance of the signal line 21 is selected from a plurality of terminating resistors 23 having different resistance values R1, R2, and R3, and the signal line 21 and the power supply line or This selected terminating resistor 23 is electrically connected to and from the ground wire 22. This may result in impedance matching.

Further, in the semiconductor device 1 of the present embodiment, as shown in FIG. 6, a plurality of terminating resistors 23 electrically connected in series are provided, and at least one selected from the plurality of terminating resistors 23. The above terminating resistor 23 may be electrically connected between the signal line 21 and the power supply line or the ground line 22.

In the case of this configuration, the signal line 21 and the power supply line or the ground line 22 are connected so that the resistance value matches the characteristic impedance of the signal line 21 from among the plurality of terminating resistors 23 electrically connected in series. Select the number of terminating resistors 23 that are electrically connected between them. This may result in impedance matching. Further, it is effective to change the resistance values of the plurality of terminating resistors 23 in binary numbers.

In the interposer 4, as shown in FIGS. 2, 5 and 6, a first wiring layer 13a forming the signal line 21, a second wiring layer 13b forming the power supply line or the ground line 22, and a terminating resistor are used. The third wiring layer 13c forming the 23 is laminated via the interlayer insulating layer 12, respectively. In the present embodiment, the third wiring layer 13c, the first wiring layer 13a, and the second wiring layer 13b are laminated on the Si substrate 12 (not shown) in this order. .. Further, in FIGS. 2, 5 and 6, the interlayer insulating layer 12 is shown as a space.

The signal line 21 (first wiring layer 13a) and one end of the terminating resistor 23 (third wiring layer 13c) are electrically connected via a contact plug 14a penetrating the interlayer insulating layer 12 in the thickness direction. ing. On the other hand, between the power supply line or the ground line 22 (second wiring layer 13b) and the other end of the terminating resistor 23 (third wiring layer 13c), a contact plug 14b penetrating the interlayer insulating layer 12 in the thickness direction is interposed. Is electrically connected.

The third wiring layer 13c is made of a resistor such as polysilicon as the terminating resistor 23. Contact pads 19a and 19b are provided at one end and the other end of the terminating resistor 23. The signal line 21 is electrically connected to a contact pad 19a provided on one end side of the terminating resistor 23 via a contact plug 14a. The power supply line or ground line 22 is electrically connected to a contact pad 19b provided on the other end side of the terminating resistor 23 via a contact plug 14b.

In the interposer 4, the interposer 4 is increased by arranging the terminating resistor 23 in the lower layer of the first wiring layer 13a forming the signal line 21 and the second wiring layer 13b forming the power supply line or the ground line 22. It is possible to prevent that.

Further, the contact pad 19a is directly below the first wiring layer 13a forming the signal line 21. The contact pad 19b is directly below the second wiring layer 13b forming the power supply line or the ground line 22. As a result, the signal line 21 and the contact pad 19a on one end side of the terminating resistor 23 can be easily connected via the contact plug 14a. Further, it is possible to easily connect the power supply line or the ground line 22 and the contact pad 19b on the other end side of the terminating resistor 23 via the contact plug 14b. Further, the connection with the terminating resistor 23 selected from the plurality of terminating resistors 23 described above can be easily performed via the contact plugs 14a and 14b after the interposer 4 is manufactured.

In order to secure the threshold value and the noise margin while suppressing reflection to some extent, it is preferable to use a higher terminating resistor 23 of about 70Ω instead of the terminating resistor 23 of about 50Ω. Further, it is preferable to determine the resistance value of the terminating resistor 23 while adjusting the reflection and the decrease in the voltage level. For example, in the case of a high-speed I / O line such as a DDR memory, since the output impedance is high, if the resistance value of the terminating resistor 23 is set to 50Ω, it may drop too much.

The present invention is not necessarily limited to that of the above embodiment, and various modifications can be made without departing from the spirit of the present invention.
For example, in the above embodiment, the case where the present invention is applied to a semiconductor package called HBM is illustrated, but the present invention is not necessarily limited to such a configuration, and the first semiconductor chip and the first semiconductor The present invention can be widely applied to a semiconductor device including an interposer on which a second semiconductor chip that controls a chip is mounted.

1 ... Semiconductor device 2 ... First semiconductor chip 3 ... Second semiconductor chip 4 ... Interposer 5 ... Package substrate 6 ... Memory chip 7 ... Logic chip 8 ... Through silicon via (TSV) 9 ... Bump electrode 10 ... Bump electrode 11 ... Si substrate 12 ... Interlayer insulation layer 13 ... Wiring layer 13a ... First wiring layer 13b ... Second wiring layer 13c ... Third wiring layer 14, 14a, 14b ... Contact plug 15 ... Through silicon via (TSV) 16 ... Contact Plug 17 ... Bump electrode 18 ... Solder ball 19a, 19b ... Contact pad 21 ... Signal line 22 ... Power supply line or ground line 23 ... Termination resistance

Claims (6)

The first semiconductor chip and
A second semiconductor chip that controls the first semiconductor chip and
The first semiconductor chip and the interposer on which the second semiconductor chip is mounted are provided.
The interposer includes a signal line that electrically connects the first semiconductor chip and the second semiconductor chip, a power supply line or a ground line that is electrically connected to the signal line, and the signal line. A semiconductor device having a terminating resistor inserted between the power supply line or the ground line. A plurality of the terminating resistors having different resistance values are provided, and the terminating resistors are provided.
The first aspect of the present invention, wherein one terminating resistor selected from the plurality of terminating resistors is electrically connected between the signal line and the power supply line or the ground line. Semiconductor device. A plurality of the terminating resistors electrically connected in series are provided.
Claim 1 is characterized in that at least one or more of the terminating resistors selected from the plurality of terminating resistors are electrically connected between the signal line and the power supply line or the ground line. The semiconductor device described in 1. The interposer has a first conductor layer provided with the signal line, a second conductor layer provided with the power supply line or the ground line, and a third conductor layer provided with the terminating resistor. Each consists of a multi-layer wiring board laminated via an interlayer insulation layer.
The signal line and the terminating resistor, and the power supply line or the ground line and the terminating resistor are electrically connected via a contact plug penetrating the interlayer insulating layer in the thickness direction. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor device is characterized by the above. The semiconductor device according to claim 4, wherein the third conductor layer contains polysilicon. The signal line is a transmission line that inputs / outputs signals between the first semiconductor chip and the second semiconductor chip.
The semiconductor device according to any one of claims 1 to 5, wherein the terminating resistor is arranged on the terminal side of the transmission line and has a resistance value matched to the characteristic impedance of the transmission line.

Images