JP2007011632A - Memory speed optimization method and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory speed optimization method for achieving a sure operation of the memory by arranging a terminator matching with a memory speed of a memory which operates at a high speed and by preventing weakening of a waveform. <P>SOLUTION: A memory speed optimization method for arranging a terminator 4 on a memory signal line 3 connecting between a CPU 1 and a memory 2 prepares a plurality of terminator values of the terminator 4 corresponding to a memory speed or to the memory speed and the signal line 3, and selects an optimum terminator value among the terminator values by a BIOS or an application program. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory speed optimization method that realizes reliable operation of a memory by disposing a terminator corresponding to the memory speed for a memory that operates at high speed and preventing deterioration of waveform quality.

CPUs have been speeded up year by year, and CPU internal clock speeds, CPU bus widths, etc. have been increased. Along with this, speeding up of memory is also required.
For example, AMD's Opteron (trademark) is mainly a CPU for server use, but the current standard of eight memories connected thereto is DDR333. Here, DDR (Double Data Rate) means that both the rising edge and falling edge timing of the external clock signal are used, and double data transfer is realized with the same clock, thereby speeding up the operation. An SDRAM standard, DDR333 corresponds to a memory clock of 333 MHz. However, in a CPU such as Opteron (trademark) that requires high-speed operation, it is desired to use a memory such as DDR400 corresponding to a 400 MHz memory clock.

JP-A-8-272501 JP 2002-82744 A

The signal line connecting the CPU and the memory has the following problems.
FIG. 5 shows a conventional general circuit. A line 103 from the CPU 101 to the memory 102 has an L component (reactance), an R component (resistance), and a C component (stray capacitance). Have Due to the influence of these components, the waveform transmitted through the line 103 becomes distorted, and it may not be possible to determine whether the input signal is “1” or “0”. This does not guarantee a stable operation of the memory.
In order to ensure the waveform quality, it is necessary to make the L, R, and C components of the line 103 from the CPU 101 to the memory 102 as small as possible. For that purpose, consideration must be given to shortening the length of the line 103 or reducing mutual interference with other lines. However, the L, R, and C components are also affected by the substrate material such as the memory board used, the wiring material from the CPU to the memory, the memory connector contact material, the input impedance of the memory itself, the stray capacitance and the input capacitance There are limits to reducing the L, R, and C components.
In consideration of such circumstances, a terminator 104 is provided as a means for ensuring waveform quality. The terminator 104 prevents the waveform from being rounded by cutting unnecessary reflected waves, so that the rising and falling of the waveform can be reliably captured.

Therefore, a terminator is also provided in the memory, and an invention related to this has been proposed in Patent Document 1 and the like.
In the invention described in Patent Document 1, a terminator installed in the vicinity of the most distant memory module from the output end of the bus signal drive IC among the mounted memory modules is operated to ensure good waveform quality.
In the invention described in Patent Document 2, a memory termination circuit is proposed in which a termination circuit is provided for each memory slot.

However, none of the inventions described in Patent Document 1 and Patent Document 2 considers the optimization of the terminator value. From the viewpoint of ensuring good waveform quality, it is desirable not only to provide a terminator in the memory, but also to set an optimum value corresponding to the memory speed as the terminator value.
In addition, even if the memories are mounted on the same substrate, those having different memory speeds may be mixed. Furthermore, even the memories of the same model number produced in the same lot of the same manufacturer may have different stray capacitances. Therefore, it is more preferable if an optimum terminator value is set for each signal line.

For example, in the full spec of Opteron (trademark) of AMD, it is possible to mount up to eight DDR400 memories, but at present, it is possible to stably operate up to six instead of eight. If an optimum terminator is selected and arranged finely for each signal line according to the memory speed, the operation of the memory can be stabilized even if eight memories are mounted.
As described above, by selecting a terminator having an optimum value, it is possible to secure a memory speed that maximizes the CPU capability, that is, to optimize the memory speed for the CPU.

  Therefore, an object of the present invention is to set an optimum value for each terminator arranged for each signal line. Another object of the present invention is to set the optimum value at the time of initial startup of the system by the BIOS and also after startup by the application program in consideration of user convenience.

  In order to realize such an object, the present invention provides a memory speed optimization method in which a terminator is arranged on a memory signal line connecting a CPU and a memory, and a terminator corresponding to the memory speed is prepared, The terminator is selected according to the memory speed.

  The terminator may be prepared for each memory signal line. Further, a plurality of terminator values may be prepared for each memory speed, and an optimum value may be selected from them.

The present invention may be characterized in that the terminator having the optimum terminator value is selected by the BIOS, and the selection of the terminator by the BIOS is based on information extracted from the SPD (Serial Presence Detect) by the BIOS. It may be performed automatically.
Furthermore, a terminator having an optimum terminator value may be selected by an application program instead of the BIOS.

The present invention may be configured as a computer program for optimizing memory speed, wherein an optimum value is selected as a terminator placed on a memory signal line connecting the CPU and the memory.
This computer program includes a case where the computer program is implemented as a BIOS and a program which is stored in various storage media and read out and executed on a memory after activation.

According to the first aspect of the present invention, the terminator corresponding to the memory speed can be arranged on the memory signal line.
According to the invention described in claim 2, since a plurality of terminator values are prepared for each memory signal line in accordance with the memory speed, a more appropriate terminator value is selected for the memory signal line. it can.
Furthermore, according to the third aspect of the present invention, since a plurality of terminator values corresponding to the same memory speed are prepared, an appropriate terminator value can be selected.

According to the fourth aspect of the present invention, since the optimum terminator value is selected at the time of starting the system, the user can use this system in a stable operation state.
According to the invention described in claim 5, since the BIOS automatically selects the optimum terminator value, the burden on the user is saved.

  According to the sixth aspect of the present invention, the optimum terminator value can be selected by the application program after the system is started. Therefore, if any trouble occurs, the terminator value can be reduced without restarting the system. Can be adjusted.

  According to the seventh aspect of the present invention, since the terminator value can be optimized by software, when the optimization method is to be reviewed, the computer program can be used without changing the hardware. It ’s enough to update.

<First Embodiment>
A first embodiment of the present invention will be described with reference to FIG.
A terminator 4 is disposed on the signal line 3 that connects the CPU 1 and the memory module 2. The signal line 3 is connected to the terminal 5 of the memory module 2.

In FIG. 1, only one memory module 2 is shown for convenience of explanation, but there are usually a plurality of memory modules. Similarly, although there are a plurality of signal lines, only two signal lines 3 are shown in FIG.
There are a plurality of types of signal lines such as a data bus and a control bus, and the arrangement of the terminator 4 is not necessarily required for all of them. However, for the stable operation of the memory, it is essential to provide the terminator 4 in each data bus. The n-bit data is input in parallel to the n terminals 5 of the memory module 2 bit by bit. If any one bit is delayed or the waveform is rounded, and as a result, it cannot be determined whether the signal input to the terminal 5 is “0” or “1”, such a memory module 2 A system equipped with will not be reliable. Therefore, it is necessary to provide a terminator 4 for each data bus.

In this embodiment, the optimum value is automatically selected by the BIOS. This automatic setting will be described with reference to the block diagram of FIG.
When the system including the CPU 1 and the memory module 2 according to this embodiment is turned on, the BIOS 6 is activated. The BIOS 6 reads memory identification information with reference to an SPD (not shown) of the memory module 2. This identification information includes the memory speed. For example, the BIOS 6 has a correspondence table (not shown) between the memory speed and the optimum terminator value, and transmits the optimum terminator value obtained by referring to this table to the terminator unit 7.

The configuration of the terminator unit 7 is not particularly limited. For example, a terminator selection circuit 8 and a plurality of terminators 4a, 4b,... Having various values are prepared. Even at the same memory speed, from the viewpoint of optimizing the terminator, a plurality of values such as a standard terminator and a value 1% larger or 1% smaller than this are prepared. It is desirable. This is because if multiple types are prepared, there is more room for selecting the optimum terminator.
When the terminator value is designated by the BIOS 6, the terminator selection circuit 8 selects the terminator having this terminator value by the number of signal lines 3.
When the terminator 4 having the same terminator value is arranged on all the signal lines 3, the BIOS 6 needs to indicate only the terminator value to the terminator unit 7.

The terminator unit 7 may be realized by a circuit on a substrate or may be an IC chip.
The terminator selection by the terminator selection circuit 8 may be performed by an IO instruction or a command.

The terminator 4 may be realized by a resistor or an equivalent resistance of a semiconductor. However, if the terminator selection circuit 8 and the terminator 4 are combined to form an IC chip as the terminator unit 7, it is usually realized by an equivalent resistance of a semiconductor.
Here, the selection method of the terminator 4 is added.
There are a method of connecting / deleting resistors and an active selection method. First, the former will be described with reference to FIG.
The resistors R1 and R2 connected in parallel are connected in series with the resistor R3, and this is defined as one unit RU. The units RU are connected in series or in parallel as necessary. In this way, a terminator having a desired value can be selected.
The active selection method uses a semiconductor as an equivalent resistance, but it goes without saying that these equivalent resistances can be connected in series or in parallel to select a desired value.

<Second Embodiment>
In the first embodiment, the BIOS 6 automatically selects the terminator with reference to the SPD.
The second embodiment is different from the first embodiment only in that the user selects an optimum terminator via the setting screen of the BIOS 6. Therefore, the reference numerals used in FIGS. 1 and 2 also apply to the second embodiment.

In the second embodiment, a terminator value is instructed to the terminator unit 7 by a user's judgment through a setting screen (not shown) of the BIOS 6. The method of instructing may be a method in which the user inputs a numerical value or a method of selecting from a list of selectable terminator values prepared on the BIOS side.
The user may instruct the terminator unit 7 to specify a terminator value common to any signal line, or may instruct the correspondence between the signal line and the terminator value. In the latter case, it is necessary to provide not only the terminator 4 having a plurality of values corresponding to the memory speed but also the terminator 4 corresponding to the signal line. Even the terminals 5 of the same memory module 2 may have variations in L, R, and C components. If the terminator value can be selected for each signal line, these variations can be absorbed and the memory speed can be optimized. Is more convenient for the purposes of the present invention.

<Third Embodiment>
In the first and second embodiments, the terminator value is optimized through the BIOS.
In the third embodiment, as shown in FIG. 3, the terminator value is optimized by the application program 9 after the system is started. In other respects, there is no difference from the second embodiment. Therefore, the difference between FIG. 2 and FIG. 3 is that the application program 9 instructs the terminator unit 7 on the terminator value instead of the BIOS 6.

The advantage of setting the terminator value by the application program 9 in this way is as follows. If any trouble occurs while the computer is running, it must be dealt with by analyzing whether the cause is software or hardware, whether it is memory or other hardware.
If it can be inferred that there is some cause in the memory, for example, the tool can display the waveform of the signal, etc., while displaying the waveform or displaying the presence or absence of an error, fine-tuning the terminator value, It will be work to identify. It is desirable that such work can be performed after startup. Therefore, it is necessary to select a terminator by the application program 9 instead of the BIOS 6 that is executed only at the initial startup.

<Other embodiments>
In the first embodiment, the BIOS automatically optimizes the terminator with reference to the SPD. However, such automatic setting may be performed by an application program regardless of the BIOS. I do not care. In this case, the user does not need an instruction such as a terminator value, and only has to input a command for executing the application program.

  In any of the above-described embodiments, the terminator value is optimized by software. However, a mounting board on which the terminator value has been optimized may be prepared. For example, in the case of server applications, there are many custom-made products, so resistors are mounted on the board in advance, and after receiving an order from the customer, the resistors are connected or disconnected to suit the memory to be installed. The terminator value can be optimized just by doing.

  Further, the present invention is not applied only to a specific CPU, a specific memory module standard, and a specific memory chip standard.

  That is, the embodiment disclosed above is an example in all respects and is not restrictive. Therefore, various modifications are possible. However, as long as the modification is based on the technical idea described in the claims, the modification is included in the technical scope of the present invention.

It is a figure explaining the outline of the embodiment of the present invention. It is a figure explaining selection of the optimal terminator of the 1st and 2nd embodiment. It is a figure explaining selection of the optimal terminator of a 3rd embodiment. It is a figure explaining the selection system of the terminator implement | achieved by resistance. It is a figure which shows a general circuit.

Explanation of symbols

1 CPU
2 Memory 3 Memory signal line 4 Terminator 6 BIOS
9 Application programs

Claims (7)

A memory speed optimization method for arranging a terminator on a memory signal line connecting a CPU and a memory, wherein a terminator corresponding to the memory speed is prepared, and a terminator corresponding to the memory speed of the memory is selected. Memory speed optimization method. The method of claim 1, wherein the terminator is prepared for each memory signal line. 3. The memory speed optimization method according to claim 1, wherein a plurality of terminator values are prepared for each memory speed, and an optimum one is selected from the terminators. 4. The memory speed optimization method according to claim 1, wherein a terminator having an optimum terminator value is selected by the BIOS. 5. The memory speed optimization method according to claim 4, wherein the terminator selection by the BIOS is automatically performed based on information extracted from the SPD by the BIOS. 4. The memory speed optimization method according to claim 1, wherein a terminator having an optimum terminator value is selected by an application program. A computer program for optimizing a memory speed, wherein a terminator having an optimum value is selected as a terminator to be arranged on a memory signal line connecting a CPU and a memory.