JP2007122250A - Memory interface circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory interface circuit capable of reducing a change of signal timing by difference of signal driving capability when using a different kind of memory. <P>SOLUTION: This memory interface circuit has: a reception part 21 receiving an output signal of a DIMM 3; a memory information acquisition part 22 acquiring memory information that is information related to the signal driving capability of the DIMM 3 by accessing an SPD; and a reception buffer changeover part 23 changing a threshold voltage in the reception part 21 by changing over buffers 211, 212, 213 on the basis of the memory information acquired by the memory information acquisition part 22. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory interface circuit that acquires an output signal of a memory.

2. Description of the Related Art Conventionally, in an information processing apparatus using a memory element, when accessing the memory element from an arithmetic circuit such as a CPU (Central Processing Unit) or an ASIC (Application Specific Integrated Circuit), a wiring path between the arithmetic circuit and the memory element There is a problem that timing skew occurs depending on the number of signals, or that a signal is delayed due to wiring capacitance and malfunctions. Therefore, in order to satisfy the timing requirement required when the memory element is normally accessed by the arithmetic circuit, a delay element is provided between the arithmetic circuit and the memory element, and the delay time of the data output signal from the memory element is reduced. When using a technique for improving timing skew by adjusting every bit (for example, see Patent Document 1) or a DIMM (Dual In-line Memory Module) equipped with SPD (Serial Presence Detect) The number of mounted memory elements is read from the SPD, and the timing signal is delayed according to the number of the memory elements, that is, according to the load capacitance added to the signal wiring by connecting the memory elements to the signal wiring. A technique for adjusting time (see, for example, Patent Document 2) is known.
JP 2003-173290 A JP 2002-278825 A

  By the way, when the technique described in Patent Document 1 is applied to a memory that is standardized to some extent and is produced by a plurality of manufacturers, such as a DIMM, a signal is generated if the manufacturer of the memory and the type of the memory are different. Since the timing is slightly different, it is necessary to reset the signal delay time to satisfy the timing specification. In particular, in a device such as a personal computer in which a user purchases the device main body and a DIMM used as the main memory separately, the delay time of the delay element is set in advance according to the signal timing of the DIMM used as the main memory. Since it cannot be set, there is an inconvenience that it is not easy to satisfy signal timing regulations such as timing skew when the type of DIMM used is changed.

  On the other hand, when the signal driving capability of the memory element changes and, for example, the signal driving capability increases, the signal rise time and the falling time are shortened, so that the signal delay becomes small, for example, the signal driving capability decreases. In this case, the signal delay increases because the rise and fall times of the signal are increased. Then, when the type of DIMM to be used is changed, according to the technique described in Patent Document 2, the timing of the signal delay caused by the difference in the number of memory elements mounted on the DIMM is absorbed. Although the specification can be satisfied, the timing specification may not be satisfied because the difference in signal timing caused by the difference in signal drive capability of the memory elements mounted on the DIMM cannot be absorbed. There was an inconvenience.

  The present invention has been made in view of such problems, and provides a memory interface circuit capable of reducing a change in signal timing due to a difference in signal driving ability when different types of memories are used. With the goal.

  In order to achieve the above object, a memory interface circuit according to the present invention includes a receiving unit that receives an output signal of a memory, a memory information acquiring unit that acquires memory information that is information related to the signal driving capability of the memory, A threshold voltage setting unit that changes a threshold voltage in the reception unit based on the memory information acquired by the memory information acquisition unit.

  According to this configuration, the memory information that is information related to the signal driving capability of the memory is acquired by the memory information acquisition unit, and the threshold voltage in the reception unit that receives the output signal of the memory is based on the memory information by the threshold voltage setting unit. Therefore, when different types of memories are used, changes in the reception timing of signals from the memory due to differences in signal driving capability can be reduced.

  In the above-described memory interface circuit, the threshold voltage setting unit increases the threshold voltage of the receiving unit at the rising edge of the output signal in accordance with the increase in the signal driving capability indicated by the memory information, and the signal Decrease according to decrease in driving ability.

  According to this configuration, the threshold voltage setting unit increases or decreases the threshold voltage of the receiving unit at the rise of the output signal of the memory according to the magnitude of the signal driving capability indicated by the memory information. If the value is large, the threshold voltage of the receiving unit is increased and the signal reception timing is delayed. If the signal driving capability of the memory is small, the threshold voltage of the receiving unit is decreased and the signal reception timing is advanced.

  In the above-described memory interface circuit, the threshold voltage setting unit decreases the threshold voltage of the receiving unit at the falling edge of the output signal in accordance with an increase in the signal driving capability indicated by the memory information, Increase according to decrease in signal driving capability.

  According to this configuration, the threshold voltage setting unit decreases the threshold voltage of the receiving unit at the falling edge of the output signal of the memory according to the magnitude of the signal driving capability indicated by the memory information. If the capability is large, the threshold voltage of the receiving unit is decreased and the signal reception timing is delayed, and if the signal driving capability of the memory is small, the threshold voltage of the receiving unit is increased and the signal reception timing is advanced.

  Further, in the above-described memory interface circuit, the threshold voltage setting unit decreases the threshold voltage of the receiving unit at the rise and fall of the output signal in accordance with the increase in the signal driving capability indicated by the memory information. The signal driving capability is increased according to the decrease.

  According to this configuration, the threshold voltage of the receiving unit at the rise and fall of the output signal of the memory is increased according to the magnitude of the signal drive capability indicated by the memory information. Therefore, if the signal drive capability of the memory is large The threshold voltage of the receiving unit is reduced, the received pulse width of the memory output signal is expanded, and the threshold voltage of the receiving unit is increased if the signal driving capability of the memory is small, and the received pulse width of the output signal of the memory is reduced. As a result, when different types of memories are used, it is possible to reduce a change in pulse width in the output signal of the memory due to a difference in signal driving capability.

  In the memory interface circuit described above, the memory is a DIMM including an SPD, and the memory information acquisition unit acquires the memory information by accessing the SPD.

  According to this configuration, since the memory information is acquired from the SPD provided in the DIMM by the memory information acquisition unit, the memory information of the DIMM can be automatically acquired.

  According to the memory interface circuit having such a configuration, the memory information that is information on the signal driving capability of the memory is acquired, and the threshold voltage in the receiving unit that receives the output signal of the memory is changed based on the memory information. Therefore, when different types of memories are used, it is possible to reduce the change in the reception timing of signals from the memory due to the difference in signal driving capability.

  Embodiments according to the present invention will be described below with reference to the drawings. In addition, the structure which attached | subjected the same code | symbol in each figure shows that it is the same structure, The description is abbreviate | omitted. FIG. 1 is a block diagram showing an example of an information processing apparatus using a memory interface circuit according to an embodiment of the present invention. An information processing apparatus 1 shown in FIG. 1 shows an example of a basic configuration of a data processing unit in an image forming apparatus such as a personal computer, a copying machine, a facsimile, or other information processing apparatus that processes various data. It is.

  The information processing apparatus 1 illustrated in FIG. 1 includes, for example, a memory interface circuit 2, a DIMM 3, and a CPU 4. The CPU 4 only needs to access the DIMM 3, and may be, for example, an ASIC or other dedicated circuit.

  The DIMM 3 is an example of a memory and is a memory module defined by, for example, JEDEC (Joint Electron Device Engineering Council), and includes a memory element 31 made of, for example, a DRAM (Dynamic Random Access Memory), and an SPD 32. . The memory is not limited to DIMM, and various memory modules such as a memory card conforming to a standard defined by PCMCIA (Personal Computer Memory Card International Association) and SDA (SD Card Association) can be used.

  The SPD 32 is configured by using, for example, an EEPROM (Electrically Erasable and Programmable Read Only Memory) having a serial interface, and the memory element 31 includes information regarding the manufacturer name and model of the DIMM 3 and other electrical characteristics of the memory element 31 in advance. Information that serves as a clue to know the signal driving capability of the device is stored. Note that the information regarding the signal driving capability may be held in the memory by another method, for example, by storing information regarding the signal driving capability in advance using, for example, a non-volatile storage element as the memory element 31 without using the SPD 32. .

  The memory interface circuit 2 outputs a signal output from the CPU 4, for example, a data signal, an address signal, and an output signal SOUT1, which is another control signal, to the DIMM 3, and adjusts the timing of the output signal DIN1, which is a data signal of the DIMM 3, for example. A circuit unit that performs output to the CPU 4 as the output signal DIN3, for example, a receiving unit 21 that receives the output signal DIN1 of the DIMM 3, a memory information acquisition unit 22 that acquires memory information that is information related to the signal driving capability of the DIMM 3, Based on the memory information acquired by the memory information acquisition unit 22, the reception buffer switching unit 23 (threshold voltage setting unit) that changes the threshold voltage in the reception unit 21 and the output signal SOUT 1 of the CPU 4 are received and output to the DIMM 3. Buffer 24 that outputs as SOUT2 It is configured to include a.

  The receiving unit 21 includes, for example, buffers 211, 212, and 213, a changeover switch SW1, and a signal holding unit 214. The buffers 211, 212, and 213 are buffer circuits that receive the output signal DIN1 of the DIMM 3 and output it to the changeover switch SW1, respectively. As shown in FIG. 2, output signals that are signals input to the buffers 211, 212, and 213 The threshold voltages for DIN1 are set to Vth1, Vth2, and Vth3, respectively. Further, the threshold voltages Vth1, Vth2, and Vth3 have a relationship of, for example, Vth1> Vth2> Vth3. The buffers 211, 212, and 213 may have the same operating power supply voltage and only different threshold voltages, or may have different threshold voltages by making the operating power supply voltages different.

  Note that the number of buffers in the receiving unit 21 is not limited to three, and may be two or four or more, for example, and the threshold voltage is not limited to three stages. The receiving unit 21 is not limited to the example of switching the threshold voltage in the receiving unit 21 by switching buffers having different threshold voltages. For example, the threshold voltage can be changed by changing the operating power supply voltage of the buffer using one buffer. May be changed.

  The change-over switch SW1 selects any one of the output signals from the buffers 211, 212, and 213 according to the control signal from the reception buffer switching unit 23, and the signal holding unit 214 and the reception buffer switching unit 23 as the selection signal DIN2. Output to. The signal holding unit 214 outputs the signal output from the changeover switch SW1 to the CPU 4 as the output signal DIN3. Further, the signal holding unit 214 switches the changeover switch SW1 by holding the output signal level of the output signal DIN3 in accordance with a signal indicating the switching timing of the changeover switch SW1 from the reception buffer switching unit 23 by, for example, a latch circuit. This prevents the signal level of the output signal DIN3 from being disturbed during operation.

  The memory information acquisition unit 22 is configured using, for example, a sequential circuit, a CPU, a serial communication circuit, and the like. For example, by executing serial communication with the SPD 32, the manufacturer name of the DIMM 3 stored in the SPD 32, Memory information such as the model is acquired and output to the reception buffer switching unit 23. The reception buffer switching unit 23 switches the connection of the changeover switch SW1 according to the memory information output from the memory information acquisition unit 22 and the selection signal DIN2 output from the changeover switch SW1.

  FIG. 3 is an explanatory diagram in the form of a table showing an example of the relationship between the DIMM 3 model and the output current value. The output current value of the signal in the DIMM 3 is determined for each model of the DIMM 3. For example, the output current value of the model “DIMM (1)” is 14 mA, the output current value of the model “DIMM (2)” is 10 mA, and the model “DIMM”. If the output current value of (3) ”is 8 mA and the output current value of 10 mA is standard, for example, the signal drive capability of the model“ DIMM (2) ”is standard, and the model“ DIMM (1) ” The signal driving capability of “DIMM (3)” is smaller than the standard. That is, as shown in FIG. 3, if the signal output current value for each DIMM3 type is confirmed in advance, the information indicating the DIMM3 type stored in the SPD 32 is the signal output current value of the DIMM3, that is, the signal drive. It has significance as information indicating ability.

  In addition, although the example which uses the information which shows the type of DIMM3 memorize | stored in SPD32 as memory information which is the information regarding the signal drive capability of a memory was shown, the output current of memory is shown in nonvolatile memory elements, such as SPD32, for example The value itself may be stored as memory information, or the magnitude of the signal driving capability may be expressed by symbols such as A, B, and C, for example.

  Next, the operation of the memory interface circuit 2 configured as described above will be described. FIG. 4 is a flowchart showing an example of the operation of the memory interface circuit 2. First, the memory information acquisition unit 22 reads information indicating the type of DIMM 3 from the SPD 32 as memory information, and the memory information is output to the reception buffer switching unit 23 (step S1).

  FIG. 5 is a signal waveform diagram showing an example of signal waveforms of the output signal DIN1 and the output signal DIN3. 5A shows the output signal DIN1 of the type “DIMM (1)”, FIG. 5B shows the output signal DIN1 of the type “DIMM (2)”, and FIG. 5C shows the type “DIMM ( 3) ”, and FIG. 5D shows the signal waveform of the output signal DIN3 output from the receiving unit 21. As shown in FIG. 5, for the output signal DIN1 of the type “DIMM (2)” having a standard signal driving capability, the output of the type “DIMM (1)” having a signal driving capability larger than that of “DIMM (2)”. The signal DIN1 has a steep rise and fall of the signal, while the output signal DIN1 of the type “DIMM (3)” having a signal driving capability smaller than “DIMM (2)” has a slow rise and fall of the signal.

  Next, the connection of the changeover switch SW1 is switched by the reception buffer switching unit 23 in accordance with the memory information output from the memory information acquisition unit 22 (step S2). FIG. 6 is an explanatory diagram for explaining an example of the switching operation of the selector switch SW1 by the reception buffer switching unit 23. FIG. 7 is a state transition diagram showing transition of the switching state of the selector switch SW1.

  As shown in FIG. 6, first, when the memory information output from the memory information acquisition unit 22 indicates that the DIMM 3 is a model “DIMM (2)” with a standard signal driving capability, The changeover switch SW1 is switched to the buffer 212 by the reception buffer switching unit 23, and the output signal DIN1 output from the DIMM 3 is received by the buffer 212 regardless of the signal level of the selection signal DIN2. The output signal of the buffer 212 is output to the signal holding unit 214 as the selection signal DIN2, and is output from the signal holding unit 214 to the CPU 4 as the output signal DIN3.

  Then, as shown in FIG. 5B, the signal level of the output signal DIN1 is determined by the buffer 212 at the threshold voltage Vth2 at both rising and falling edges, and the timing is output from the buffer 212 via the changeover switch SW1. A selection signal DIN2 that rises at T1 and falls at timing T2 is output to the signal holding unit 214. Then, as shown in FIG. 5D, an output signal DIN3 that rises at timing T1 and falls at timing T2 is output from the signal holding unit 214 to the CPU 4.

  Next, when the memory information output from the memory information acquisition unit 22 indicates that the DIMM 3 is the type “DIMM (1)” having a large signal driving capability, the selection signal DIN2 is at the low level. If there is, the switch SW1 is switched to the buffer 211 by the reception buffer switching unit 23, while the switch SW1 is switched to the buffer 213 by the reception buffer switching unit 23 if the selection signal DIN2 is at a high level.

  That is, as shown in FIG. 7A, when the output signal level of the buffer 211 becomes high (buffer 211 = 1) by the reception buffer switching unit 23, the switch SW1 is switched to the buffer 213, and the output signal of the buffer 213 is displayed. When the level becomes low (buffer 213 = 0), the changeover switch SW1 is switched to the buffer 211.

  Then, as shown in FIG. 5A, as a result of the signal level being determined at the threshold voltage Vth1 by the buffer 211 at the rising edge of the output signal DIN1 by the changeover switch SW1, the signal rising at the timing T1 is signaled as the selection signal DIN2. When the output signal DIN1 falls, the buffer 213 determines the signal level based on the threshold voltage Vth3. As a result, the signal falling at the timing T2 is output to the signal holding unit 214 as the selection signal DIN2. In the signal holding unit 214, the signal level of the output signal DIN3 is held at the switching timing of the changeover switch SW1, and as shown in FIG. 5D, the output that rises from the signal holding unit 214 at the timing T1 and falls at the timing T2. The signal DIN3, that is, the output signal DIN3 adjusted at substantially the same timing as when the DIMM3 is of the type “DIMM (2)” is output to the CPU 4.

  Next, as shown in FIG. 6, when the memory information output from the memory information acquisition unit 22 indicates that the DIMM 3 is a type “DIMM (3)” having a small signal driving capability, If the selection signal DIN2 is at a low level, the reception buffer switching unit 23 switches the switch SW1 to the buffer 213. If the selection signal DIN2 is at a high level, the reception buffer switching unit 23 causes the switching switch SW1 to be switched to the buffer 211. Can be switched.

  That is, as shown in FIG. 7B, when the output signal level of the buffer 211 becomes low level (buffer 211 = 0) by the reception buffer switching unit 23, the switch SW1 is switched to the buffer 213, and the output signal of the buffer 213 is displayed. When the level becomes high (buffer 213 = 1), the changeover switch SW1 is switched to the buffer 211.

  Then, as shown in FIG. 5C, as a result of the signal level being determined at the threshold voltage Vth3 by the buffer 213 by the changeover switch SW1 at the rise of the output signal DIN1, the signal that rises at the timing T1 is signaled as the selection signal DIN2. As a result of the signal level being determined by the buffer 211 at the threshold voltage Vth1 when the output signal DIN1 falls, the signal falling at the timing T2 is outputted to the signal holding unit 214 as the selection signal DIN2. In the signal holding unit 214, the signal level of the output signal DIN3 is held at the switching timing of the changeover switch SW1, and as shown in FIG. 5D, the output that rises from the signal holding unit 214 at the timing T1 and falls at the timing T2. The signal DIN3, that is, the output signal DIN3 adjusted at substantially the same timing as when the DIMM3 is the type “DIMM (1)” or “DIMM (2)” is output to the CPU 4.

  Thereby, the threshold voltage of the reception unit 21 at the rising edge of the output signal DIN1 is increased or decreased by the reception buffer switching unit 23 according to the signal driving capability of the DIMM 3 indicated by the memory information acquired by the memory information acquisition unit 22. The threshold voltage of the receiving unit 21 at the falling edge of the output signal DIN1 is increased or decreased according to the signal driving capability of the DIMM 3 indicated by the memory information.

  When the CPU 4 accesses the DIMM 3, a signal output from the CPU 4, for example, an output signal SOUT 1, which is another control signal, is output to the memory element 31 as an output signal SOUT 2 through the buffer 24 and output. An output signal DIN1 output from the memory element 31 in response to the signal SOUT2 is output to the receiving unit 21.

  Further, since the timing of the output signal DIN1 is adjusted by the receiving unit 21 as described above and output to the CPU 4 as the output signal DIN3, the signal timing due to the difference in signal driving capability when different types of memories are used. The change can be reduced, and the reliability of memory access in the information processing apparatus 1 using the memory interface circuit 2 can be improved.

  When the signal driving capability of the DIMM 3 is larger or smaller than the standard, the threshold voltage of the receiving unit 21 at the rising edge of the output signal DIN1 is different from the threshold voltage of the receiving unit 21 at the falling edge of the output signal DIN1. Although an example of setting is shown, the threshold voltage of the reception unit 21 at the rise and fall of the output signal DIN1 is decreased in accordance with the increase in signal driving capability indicated by the memory information acquired by the memory information acquisition unit 22. For example, when the signal driving capability of the DIMM 3 is larger or smaller than the standard, the threshold voltage of the receiving unit 21 at the rising edge of the output signal DIN1 and the falling edge of the output signal DIN1 are increased. Even if the threshold voltage of the receiver 21 is set to the same voltage There.

  In this case, when the signal drive capability of the memory is large, that is, when the rise and fall of the memory output signal is steep and the pulse width of the signal is reduced, the threshold voltage of the receiving unit is reduced and the memory output signal is received. When the pulse width is expanded and the signal drive capability of the memory is small, that is, when the rise and fall of the memory output signal is slow and the pulse width of the signal is expanded, the threshold voltage of the receiver is increased and the memory output is increased. Since the received pulse width of the signal is reduced, when a different type of memory is used, a change in the pulse width in the output signal of the memory due to a difference in signal driving capability is reduced, and a change in signal timing related to the pulse width is reduced. be able to.

  The memory interface circuit 2 may be configured without the buffer 24. In FIG. 1, for ease of explanation, the output signal DIN3 and the output signal SOUT1 input to and output from the CPU 4 and the output signal DIN1 and the output signal SOUT2 input to and output from the DIMM 3 are transmitted and received via different signal lines. However, the output signal DIN3 and the output signal SOUT1, and the output signal DIN1 and the output signal SOUT2 may be transmitted and received via a common signal line.

  In addition, the memory interface circuit 2 is provided outside the CPU 4. However, the memory interface circuit 2 may be provided in an arithmetic device such as the CPU 4 or ASIC. Moreover, although the memory information acquisition part 22 showed the example which accesses SPD32 and acquires memory information, you may make it a user set memory information using setting switches, such as a dip switch, for example.

It is a block diagram which shows an example of the information processing apparatus using the memory interface circuit which concerns on one Embodiment of this invention. It is explanatory drawing of the table format which shows an example of the threshold voltage of the buffer shown in FIG. It is explanatory drawing of the table format which shows an example of the relationship between the model of DIMM shown in FIG. 1, and an output electric current value. 3 is a flowchart showing an example of the operation of the memory interface circuit shown in FIG. 1. It is a signal waveform diagram for demonstrating an example of operation | movement of the receiving part shown in FIG. It is explanatory drawing of the table format for demonstrating an example of switching operation | movement of the changeover switch by the receiving buffer switching part shown in FIG. FIG. 2 is a state transition diagram illustrating transition of a switching state of the changeover switch illustrated in FIG. 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Information processing apparatus 2 Memory interface circuit 3 DIMM
4 CPU
21 receiving unit 22 memory information obtaining unit 23 receiving buffer switching unit 24 buffer 31 memory element 32 SPD
211, 212, 213 Buffer 214 Signal holding unit SW1 changeover switch

Claims (5)

A receiver for receiving the output signal of the memory;
A memory information acquisition unit for acquiring memory information which is information relating to the signal driving capability of the memory;
A memory interface circuit comprising: a threshold voltage setting unit that changes a threshold voltage in the reception unit based on the memory information acquired by the memory information acquisition unit.   The threshold voltage setting unit increases the threshold voltage of the receiving unit at the rising edge of the output signal according to an increase in the signal driving capability indicated by the memory information, and decreases according to a decrease in the signal driving capability. The memory interface circuit according to claim 1.   The threshold voltage setting unit decreases the threshold voltage of the receiving unit at the falling edge of the output signal according to an increase in the signal driving capability indicated by the memory information, and increases according to a decrease in the signal driving capability. The memory interface circuit according to claim 1 or 2, wherein   The threshold voltage setting unit decreases the threshold voltage of the receiving unit at the rise and fall of the output signal according to the increase in the signal driving capability indicated by the memory information, and according to the decrease in the signal driving capability. The memory interface circuit according to claim 1, wherein the memory interface circuit is increased. The memory is a DIMM with an SPD;
The memory interface circuit according to claim 1, wherein the memory information acquisition unit acquires the memory information by accessing the SPD.

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