TWI230984B - Method for forming a masking layer on a substrate - Google Patents

Method for forming a masking layer on a substrate Download PDF

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Publication number
TWI230984B
TWI230984B TW092118254A TW92118254A TWI230984B TW I230984 B TWI230984 B TW I230984B TW 092118254 A TW092118254 A TW 092118254A TW 92118254 A TW92118254 A TW 92118254A TW I230984 B TWI230984 B TW I230984B
Authority
TW
Taiwan
Prior art keywords
layer
substrate
scope
patent application
item
Prior art date
Application number
TW092118254A
Other languages
English (en)
Chinese (zh)
Other versions
TW200403756A (en
Inventor
Stefan Tegen
Peter Moll
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of TW200403756A publication Critical patent/TW200403756A/zh
Application granted granted Critical
Publication of TWI230984B publication Critical patent/TWI230984B/zh

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2002—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image
    • G03F7/201—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image characterised by an oblique exposure; characterised by the use of plural sources; characterised by the rotation of the optical device; characterised by a relative movement of the optical device, the light source, the sensitive system or the mask
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Chemically Coating (AREA)
TW092118254A 2002-08-16 2003-07-03 Method for forming a masking layer on a substrate TWI230984B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10237508A DE10237508A1 (de) 2002-08-16 2002-08-16 Verfahren zum Bilden einer Maskierschicht auf einem Substrat

Publications (2)

Publication Number Publication Date
TW200403756A TW200403756A (en) 2004-03-01
TWI230984B true TWI230984B (en) 2005-04-11

Family

ID=31501774

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092118254A TWI230984B (en) 2002-08-16 2003-07-03 Method for forming a masking layer on a substrate

Country Status (3)

Country Link
DE (1) DE10237508A1 (fr)
TW (1) TWI230984B (fr)
WO (1) WO2004019133A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10355225B3 (de) * 2003-11-26 2005-03-31 Infineon Technologies Ag Herstellungsverfahren für einen Grabenkondensator mit einem Isolationskragen, der über einen vergrabenen Kontakt einseitig mit einem Substrat elektrisch verbunden ist, insbesondere für eine Halbleiterspeicherzelle

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4821094A (en) * 1985-11-08 1989-04-11 Lockheed Missiles & Space Company, Inc. Gate alignment procedure in fabricating semiconductor devices
JP2786307B2 (ja) * 1990-04-19 1998-08-13 三菱電機株式会社 電界効果トランジスタ及びその製造方法
US6426253B1 (en) * 2000-05-23 2002-07-30 Infineon Technologies A G Method of forming a vertically oriented device in an integrated circuit

Also Published As

Publication number Publication date
TW200403756A (en) 2004-03-01
WO2004019133A2 (fr) 2004-03-04
WO2004019133A3 (fr) 2004-10-07
DE10237508A1 (de) 2004-03-11

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees